rtio/dma: fix previous commit

2020-07-12 10:14:22 +08:00 · 2020-07-12 10:14:22 +08:00 · 4340a5cfc1
parent f2e0d27334
commit 4340a5cfc1
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/rtio/dma.py
+++ b/artiq/gateware/rtio/dma.py
@ -12,7 +12,7 @@ def _reverse_bytes(s, g):


 class WishboneReader(Module):
-    def __init__(self):
+    def __init__(self, bus):
        self.bus = bus

        aw = len(bus.adr)