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rtio/dma: remove dead/broken code

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This commit is contained in:
Sebastien Bourdeauducq 2020-07-12 10:13:18 +08:00
parent 901be75ba4
commit f2e0d27334
1 changed files with 1 additions and 3 deletions
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4
artiq/gateware/rtio/dma.py
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@ -12,9 +12,7 @@ def _reverse_bytes(s, g):
class WishboneReader(Module):
def __init__(self, bus=None):
if bus is None:
bus = wishbone.Interface
def __init__(self):
self.bus = bus
aw = len(bus.adr)