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rtio: support direct 64-bit now CSR in KernelInitiator
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parent
251a0101a6
commit
3a7819704a
@ -60,11 +60,14 @@ class Interface(Record):
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class KernelInitiator(Module, AutoCSR):
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def __init__(self, tsc, cri=None):
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def __init__(self, tsc, cri=None, now64=False):
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self.target = CSRStorage(32)
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# not using CSRStorage atomic_write feature here to make storage reset_less
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self.now_hi = CSR(32)
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self.now_lo = CSR(32)
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if now64:
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self.now = CSRStorage(64)
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else:
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# not using CSRStorage atomic_write feature here to make storage reset_less
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self.now_hi = CSR(32)
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self.now_lo = CSR(32)
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# Writing target clears o_data. This implements automatic
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# zero-extension of output event data by the gateware. When staging an
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@ -87,16 +90,19 @@ class KernelInitiator(Module, AutoCSR):
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# # #
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now_hi_backing = Signal(32)
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now = Signal(64, reset_less=True)
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self.sync += [
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If(self.now_hi.re, now_hi_backing.eq(self.now_hi.r)),
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If(self.now_lo.re, now.eq(Cat(self.now_lo.r, now_hi_backing)))
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]
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self.comb += [
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self.now_hi.w.eq(now[32:]),
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self.now_lo.w.eq(now[:32])
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]
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if now64:
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now = self.now.storage
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else:
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now = Signal(64, reset_less=True)
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now_hi_backing = Signal(32)
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self.sync += [
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If(self.now_hi.re, now_hi_backing.eq(self.now_hi.r)),
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If(self.now_lo.re, now.eq(Cat(self.now_lo.r, now_hi_backing)))
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]
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self.comb += [
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self.now_hi.w.eq(now[32:]),
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self.now_lo.w.eq(now[:32])
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]
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self.comb += [
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self.cri.cmd.eq(commands["nop"]),
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