sayma: drive filtered_clk_sel on master variant

2020-02-06 22:28:49 +08:00 · 2020-02-06 22:28:49 +08:00 · 6d26def3ce
parent 52ec849008
commit 6d26def3ce
1 changed files with 1 additions and 0 deletions
--- a/artiq/gateware/targets/sayma_amc.py
+++ b/artiq/gateware/targets/sayma_amc.py
@ -388,6 +388,7 @@ class Master(MiniSoC, AMPSoC):
        self.config["SI5324_AS_SYNTHESIZER"] = None
        self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)

+        self.comb += platform.request("filtered_clk_sel").eq(1)
        self.comb += platform.request("sfp_tx_disable", 0).eq(0)
        self.submodules.drtio_transceiver = gth_ultrascale.GTH(
            clock_pads=platform.request("cdr_clk_clean", 0),