mirror of https://github.com/m-labs/artiq.git
kc705: revive DRTIO satellite with updated syntax, update GTX
* Multi-channel has not been implemented yet.
This commit is contained in:
parent
cff7bcc122
commit
f25e86e934
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@ -5,17 +5,18 @@ from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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from artiq.gateware.drtio.transceiver.clock_aligner import BruteforceClockAligner
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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class GTX_20X(Module, TransceiverInterface):
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# Only one channel is supported.
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#
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# The transceiver clock on clock_pads must be at the RTIO clock
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# frequency when clock_div2=False, and 2x that frequency when
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# clock_div2=True.
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
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clock_div2=False):
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# Settings:
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# * GTX reference clock (at clock_pads) @ 125MHz == coarse RTIO frequency
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# * GTX data width = 20
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# * GTX PLL frequency @ 2.5GHz
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# * GTX line rate (TX & RX) @ 2.5Gb/s
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# * GTX TX/RX USRCLK @ 125MHz == coarse RTIO frequency
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq):
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encoder = ClockDomainsRenamer("rtio")(
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Encoder(2, True))
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self.submodules += encoder
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@ -33,21 +34,17 @@ class GTX_20X(Module, TransceiverInterface):
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# # #
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refclk = Signal()
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if clock_div2:
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_ODIV2=refclk
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)
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else:
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk
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)
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stable_clkin_n = Signal()
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self.stable_clkin.storage.attr.add("no_retiming")
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self.comb += stable_clkin_n.eq(~self.stable_clkin.storage)
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=stable_clkin_n,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk
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)
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cpllreset = Signal()
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cplllock = Signal()
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# TX generates RTIO clock, init must be in system domain
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tx_init = GTXInit(sys_clk_freq, False)
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@ -55,8 +52,11 @@ class GTX_20X(Module, TransceiverInterface):
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rx_init = ClockDomainsRenamer("rtio")(
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GTXInit(self.rtio_clk_freq, True))
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self.submodules += tx_init, rx_init
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self.comb += tx_init.cplllock.eq(cplllock), \
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rx_init.cplllock.eq(cplllock)
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self.comb += [
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cpllreset.eq(tx_init.cpllreset),
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tx_init.cplllock.eq(cplllock),
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rx_init.cplllock.eq(cplllock)
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]
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txdata = Signal(20)
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rxdata = Signal(20)
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@ -64,12 +64,11 @@ class GTX_20X(Module, TransceiverInterface):
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Instance("GTXE2_CHANNEL",
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# PMA Attributes
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p_PMA_RSV=0x00018480,
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p_PMA_RSV2=0x2050,
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p_PMA_RSV2=0x2050, # PMA_RSV2[5] = 0: Eye scan feature disabled
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p_PMA_RSV3=0,
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p_PMA_RSV4=0,
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p_RX_BIAS_CFG=0b100,
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p_RX_CM_TRIM=0b010,
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p_RX_OS_CFG=0b10000000,
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p_PMA_RSV4=1, # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
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p_RX_BIAS_CFG=0b000000000100,
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p_RX_OS_CFG=0b0000010000000,
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p_RX_CLK25_DIV=5,
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p_TX_CLK25_DIV=5,
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@ -85,6 +84,8 @@ class GTX_20X(Module, TransceiverInterface):
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p_CPLL_REFCLK_DIV=1,
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p_RXOUT_DIV=2,
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p_TXOUT_DIV=2,
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i_CPLLRESET=cpllreset,
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i_CPLLPD=cpllreset,
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o_CPLLLOCK=cplllock,
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i_CPLLLOCKEN=1,
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i_CPLLREFCLKSEL=0b001,
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@ -105,6 +106,9 @@ class GTX_20X(Module, TransceiverInterface):
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o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
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o_TXPHALIGNDONE=tx_init.Xxphaligndone,
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i_TXUSERRDY=tx_init.Xxuserrdy,
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p_TXPMARESET_TIME=1,
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p_TXPCSRESET_TIME=1,
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i_TXINHIBIT=~self.txenable.storage,
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# TX data
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p_TX_DATA_WIDTH=20,
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@ -126,24 +130,36 @@ class GTX_20X(Module, TransceiverInterface):
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o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
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o_RXPHALIGNDONE=rx_init.Xxphaligndone,
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i_RXUSERRDY=rx_init.Xxuserrdy,
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p_RXPMARESET_TIME=1,
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p_RXPCSRESET_TIME=1,
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# RX AFE
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p_RX_DFE_XYD_CFG=0,
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p_RX_CM_SEL=0b11, # RX_CM_SEL = 0b11: Common mode is programmable
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p_RX_CM_TRIM=0b010, # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
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i_RXDFEXYDEN=1,
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i_RXDFEXYDHOLD=0,
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i_RXDFEXYDOVRDEN=0,
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i_RXLPMEN=0,
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i_RXLPMEN=0, # RXLPMEN = 0: DFE mode is enabled
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p_RX_DFE_GAIN_CFG=0x0207EA,
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p_RX_DFE_VP_CFG=0b00011111100000011,
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p_RX_DFE_UT_CFG=0b10001000000000000,
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p_RX_DFE_KL_CFG=0b0000011111110,
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p_RX_DFE_KL_CFG2=0x3788140A,
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p_RX_DFE_H2_CFG=0b000110000000,
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p_RX_DFE_H3_CFG=0b000110000000,
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p_RX_DFE_H4_CFG=0b00011100000,
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p_RX_DFE_H5_CFG=0b00011100000,
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p_RX_DFE_LPM_CFG=0x0904, # RX_DFE_LPM_CFG = 0x0904: linerate <= 6.6Gb/s
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# = 0x0104: linerate > 6.6Gb/s
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# RX clock
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p_RXBUF_EN="FALSE",
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p_RX_XCLK_SEL="RXUSR",
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i_RXDDIEN=1,
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx0"),
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i_RXUSRCLK2=ClockSignal("rtio_rx0"),
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p_RXCDR_CFG=0x03000023FF10100020,
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# RX Clock Correction Attributes
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p_CLK_CORRECT_USE="FALSE",
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@ -159,11 +175,77 @@ class GTX_20X(Module, TransceiverInterface):
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o_RXCHARISK=Cat(rxdata[8], rxdata[18]),
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o_RXDATA=Cat(rxdata[:8], rxdata[10:18]),
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# RX Byte and Word Alignment Attributes
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p_ALIGN_COMMA_DOUBLE="FALSE",
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p_ALIGN_COMMA_ENABLE=0b1111111111,
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p_ALIGN_COMMA_WORD=1,
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p_ALIGN_MCOMMA_DET="TRUE",
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p_ALIGN_MCOMMA_VALUE=0b1010000011,
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p_ALIGN_PCOMMA_DET="TRUE",
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p_ALIGN_PCOMMA_VALUE=0b0101111100,
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p_SHOW_REALIGN_COMMA="FALSE",
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p_RXSLIDE_AUTO_WAIT=7,
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p_RXSLIDE_MODE="PCS",
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p_RX_SIG_VALID_DLY=10,
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# RX 8B/10B Decoder Attributes
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p_RX_DISPERR_SEQ_MATCH="FALSE",
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p_DEC_MCOMMA_DETECT="TRUE",
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p_DEC_PCOMMA_DETECT="TRUE",
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p_DEC_VALID_COMMA_ONLY="FALSE",
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# RX Buffer Attributes
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p_RXBUF_ADDR_MODE="FAST",
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p_RXBUF_EIDLE_HI_CNT=0b1000,
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p_RXBUF_EIDLE_LO_CNT=0b0000,
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p_RXBUF_EN="FALSE",
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p_RX_BUFFER_CFG=0b000000,
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p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
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p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
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p_RXBUF_RESET_ON_EIDLE="FALSE", # RXBUF_RESET_ON_EIDLE = FALSE: OOB is disabled
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p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
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p_RXBUFRESET_TIME=0b00001,
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p_RXBUF_THRESH_OVFLW=61,
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p_RXBUF_THRESH_OVRD="FALSE",
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p_RXBUF_THRESH_UNDFLW=4,
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p_RXDLY_CFG=0x001F,
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p_RXDLY_LCFG=0x030,
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p_RXDLY_TAP_CFG=0x0000,
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p_RXPH_CFG=0xC00002,
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p_RXPHDLY_CFG=0x084020,
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p_RXPH_MONITOR_SEL=0b00000,
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p_RX_XCLK_SEL="RXUSR",
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p_RX_DDI_SEL=0b000000,
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p_RX_DEFER_RESET_BUF_EN="TRUE",
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# CDR Attributes
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p_RXCDR_CFG=0x03000023FF20400020, # DFE @ <= 6.6Gb/s, scrambled, CDR setting < +/- 200ppm
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# (See UG476 (v1.12.1), p.206)
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p_RXCDR_FR_RESET_ON_EIDLE=0b0,
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p_RXCDR_HOLD_DURING_EIDLE=0b0,
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p_RXCDR_PH_RESET_ON_EIDLE=0b0,
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p_RXCDR_LOCK_CFG=0b010101,
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# # RX Initialization and Reset Attributes
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# p_RXCDRFREQRESET_TIME=0b00001,
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# p_RXCDRPHRESET_TIME=0b00001,
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# p_RXISCANRESET_TIME=0b00001,
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# p_RXPCSRESET_TIME=0b00001,
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# p_RXPMARESET_TIME=0b00011,
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# Pads
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i_GTXRXP=rx_pads.p,
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i_GTXRXN=rx_pads.n,
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o_GTXTXP=tx_pads.p,
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o_GTXTXN=tx_pads.n,
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# Other parameters
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p_PCS_RSVD_ATTR=0x000, # PCS_RSVD_ATTR[1] = 0: TX Single Lane Auto Mode
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# [2] = 0: RX Single Lane Auto Mode
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# [8] = 0: OOB is disabled
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i_RXELECIDLEMODE=0b11, # RXELECIDLEMODE = 0b11: OOB is disabled
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p_RX_DFE_LPM_HOLD_DURING_EIDLE=0b0,
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p_ES_EYE_SCAN_EN="TRUE", # Must be TRUE for GTX
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)
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tx_reset_deglitched = Signal()
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@ -199,7 +281,7 @@ class GTX_20X(Module, TransceiverInterface):
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class GTX_1000BASE_BX10(GTX_20X):
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rtio_clk_freq = 62.5e6
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rtio_clk_freq = 125e6
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class RXSynchronizer(Module, AutoCSR):
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@ -16,6 +16,7 @@ class GTXInit(Module):
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# GTX signals
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self.cplllock = Signal()
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self.cpllreset = Signal()
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self.gtXxreset = Signal()
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self.Xxresetdone = Signal()
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self.Xxdlysreset = Signal()
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@ -53,6 +54,12 @@ class GTXInit(Module):
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startup_timer = WaitTimer(startup_cycles)
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self.submodules += startup_timer
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# PLL reset should be 1 period of refclk
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# (i.e. 1/(125MHz) for the case of RTIO @ 125MHz)
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pll_reset_cycles = ceil(sys_clk_freq/125e6)
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pll_reset_timer = WaitTimer(pll_reset_cycles)
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self.submodules += pll_reset_timer
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startup_fsm = FSM(reset_state="INITIAL")
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self.submodules += startup_fsm
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@ -67,27 +74,29 @@ class GTXInit(Module):
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startup_fsm.act("INITIAL",
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startup_timer.wait.eq(1),
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If(startup_timer.done, NextState("RESET_GTX"))
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If(startup_timer.done, NextState("RESET_ALL"))
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)
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startup_fsm.act("RESET_GTX",
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startup_fsm.act("RESET_ALL",
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gtXxreset.eq(1),
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NextState("WAIT_CPLL")
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self.cpllreset.eq(1),
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pll_reset_timer.wait.eq(1),
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If(pll_reset_timer.done, NextState("RELEASE_PLL_RESET"))
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)
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startup_fsm.act("WAIT_CPLL",
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startup_fsm.act("RELEASE_PLL_RESET",
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gtXxreset.eq(1),
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If(cplllock, NextState("RELEASE_RESET"))
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If(cplllock, NextState("RELEASE_GTH_RESET"))
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)
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# Release GTX reset and wait for GTX resetdone
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# (from UG476, GTX is reset on falling edge
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# of gttxreset)
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if rx:
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startup_fsm.act("RELEASE_RESET",
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startup_fsm.act("RELEASE_GTH_RESET",
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Xxuserrdy.eq(1),
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cdr_stable_timer.wait.eq(1),
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If(Xxresetdone & cdr_stable_timer.done, NextState("ALIGN"))
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)
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else:
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startup_fsm.act("RELEASE_RESET",
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startup_fsm.act("RELEASE_GTH_RESET",
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Xxuserrdy.eq(1),
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If(Xxresetdone, NextState("ALIGN"))
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)
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@ -115,7 +124,7 @@ class GTXInit(Module):
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startup_fsm.act("READY",
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Xxuserrdy.eq(1),
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self.done.eq(1),
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If(self.restart, NextState("RESET_GTX"))
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If(self.restart, NextState("RESET_ALL"))
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)
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@ -5,6 +5,9 @@ import os
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from migen import *
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from migen.build.generic_platform import *
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from migen.build.xilinx.vivado import XilinxVivadoToolchain
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from migen.build.xilinx.ise import XilinxISEToolchain
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.builder import *
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@ -13,27 +16,101 @@ from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio import DRTIOSatellite
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from artiq import __version__ as artiq_version
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from artiq import __artiq_dir__ as artiq_dir
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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# DEBUG
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from microscope import *
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class Satellite(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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"drtioaux": 0x50000000,
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, **kwargs):
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def __init__(self, gateware_identifier_str=None, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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ident=artiq_version,
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integrated_sram_size=8192,
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**kwargs)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = platform.request("sfp_tx")
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rx_pads = platform.request("sfp_rx")
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# 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
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self.submodules.drtio_transceiver = gtx_7series.GTX_1000BASE_BX10(
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clock_pads=platform.request("si5324_clkout"),
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tx_pads=tx_pads,
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rx_pads=rx_pads,
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sys_clk_freq=self.clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
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cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
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self.submodules.drtiosat = cdr(DRTIOSatellite(
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self.rtio_tsc, self.drtio_transceiver.channels[0], self.rx_synchronizer))
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self.csr_devices.append("drtiosat")
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self.submodules.drtioaux0 = cdr(DRTIOAuxController(
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self.drtiosat.link_layer))
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self.csr_devices.append("drtioaux0")
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self.add_wb_slave(self.mem_map["drtioaux"], 0x800,
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self.drtioaux0.bus)
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self.add_memory_region("drtioaux0_mem", self.mem_map["drtioaux"] | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtiosat"])
|
||||
self.add_csr_group("drtioaux", ["drtioaux0"])
|
||||
self.add_memory_group("drtioaux_mem", ["drtioaux0_mem"])
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
|
||||
# Si5324 Phaser
|
||||
self.submodules.siphaser = SiPhaser7Series(
|
||||
si5324_clkin=platform.request("si5324_clkin"),
|
||||
rx_synchronizer=self.rx_synchronizer,
|
||||
ultrascale=False,
|
||||
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
|
||||
self.csr_devices.append("siphaser")
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
|
||||
]
|
||||
|
||||
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
|
||||
platform.add_period_constraint(self.drtio_transceiver.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(self.drtio_transceiver.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
self.drtio_transceiver.txoutclk, self.drtio_transceiver.rxoutclk)
|
||||
|
||||
rtio_channels = []
|
||||
for i in range(8):
|
||||
phy = ttl_simple.Output(platform.request("user_led", i))
|
||||
|
|
@ -47,54 +124,9 @@ class Satellite(BaseSoC):
|
|||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.comb += platform.request("sfp_tx_disable_n").eq(1)
|
||||
|
||||
# 1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
|
||||
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
tx_pads=platform.request("sfp_tx"),
|
||||
rx_pads=platform.request("sfp_rx"),
|
||||
sys_clk_freq=self.clk_freq)
|
||||
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
|
||||
self.submodules.rx_synchronizer0 = rx0(gtx_7series.RXSynchronizer(
|
||||
self.transceiver.rtio_clk_freq, initial_phase=180.0))
|
||||
self.submodules.drtio0 = rx0(DRTIOSatellite(
|
||||
self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0))
|
||||
self.csr_devices.append("rx_synchronizer0")
|
||||
self.csr_devices.append("drtio0")
|
||||
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
|
||||
self.drtio0.aux_controller.bus)
|
||||
self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
|
||||
self.config["HAS_DRTIO"] = None
|
||||
self.add_csr_group("drtio", ["drtio0"])
|
||||
self.add_memory_group("drtio_aux", ["drtio0_aux"])
|
||||
|
||||
self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6)
|
||||
si5324_clkin = platform.request("si5324_clkin")
|
||||
self.specials += \
|
||||
Instance("OBUFDS",
|
||||
i_I=ClockSignal("rtio_rx0"),
|
||||
o_O=si5324_clkin.p, o_OB=si5324_clkin.n
|
||||
)
|
||||
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
|
||||
self.csr_devices.append("si5324_rst_n")
|
||||
i2c = self.platform.request("i2c")
|
||||
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
|
||||
self.csr_devices.append("i2c")
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
|
||||
]
|
||||
|
||||
rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
|
||||
platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
platform.lookup_request("clk200"),
|
||||
self.transceiver.txoutclk, self.transceiver.rxoutclk)
|
||||
self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
|
||||
self.comb += self.drtiosat.async_errors.eq(self.local_io.async_errors)
|
||||
self.comb += self.drtiosat.cri.connect(self.local_io.cri)
|
||||
|
||||
|
||||
def main():
|
||||
|
|
@ -102,12 +134,11 @@ def main():
|
|||
description="ARTIQ device binary builder / KC705 DRTIO satellite")
|
||||
builder_args(parser)
|
||||
soc_kc705_args(parser)
|
||||
parser.set_defaults(output_dir="artiq_kc705/satellite")
|
||||
args = parser.parse_args()
|
||||
|
||||
soc = Satellite(**soc_kc705_argdict(args))
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder.add_software_package("satman", os.path.join(artiq_dir, "firmware", "satman"))
|
||||
builder.build()
|
||||
build_artiq_soc(soc, builder_argdict(args))
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
|
|
|||
Loading…
Reference in New Issue