fastlink: fix crc vs data width

artiq/gateware/rtio/phy/fastlink.py

@@ -100,7 +100,7 @@ class SerDes(Module):
             ),
             If(i == t_frame//2 - 2,
                 # inject crc for the last cycle
-                Cat(crc_data).eq(self.crc.next),
+                Cat(crc_data[-n_crc:]).eq(self.crc.next),
             ),
         ]
 

artiq/gateware/rtio/phy/phaser.py

@@ -46,7 +46,7 @@ class Phaser(Module):
                 header.we.eq(~self.config.o.address[-1]),
                 header.addr.eq(self.config.o.address),
                 header.data.eq(self.config.o.data),
-                header.type.eq(0),  # reserved
+                header.type.eq(1),  # reserved
             ),
         ]