mirror of https://github.com/m-labs/artiq
gateware: make 7-series EEM handling functions shareable
parent
1213f78ee9
commit
f7a33a1f99
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@ -0,0 +1,127 @@
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from artiq.gateware import eem
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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def peripheral_dio(module, peripheral):
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ttl_classes = {
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"input": ttl_serdes_7series.InOut_8X,
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"output": ttl_serdes_7series.Output_8X
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}
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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if peripheral["edge_counter"]:
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edge_counter_cls = edge_counter.SimpleEdgeCounter
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else:
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edge_counter_cls = None
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eem.DIO.add_std(module, peripheral["ports"][0],
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ttl_classes[peripheral["bank_direction_low"]],
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ttl_classes[peripheral["bank_direction_high"]],
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edge_counter_cls=edge_counter_cls)
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def peripheral_urukul(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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if peripheral["synchronization"]:
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sync_gen_cls = ttl_simple.ClockGen
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else:
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sync_gen_cls = None
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eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
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sync_gen_cls)
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def peripheral_novogorny(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Novogorny.add_std(module, peripheral["ports"][0], ttl_serdes_7series.Output_8X)
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def peripheral_sampler(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X)
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def peripheral_suservo(module, peripheral):
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if len(peripheral["sampler_ports"]) != 2:
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raise ValueError("wrong number of Sampler ports")
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urukul_ports = []
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if len(peripheral["urukul0_ports"]) != 2:
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raise ValueError("wrong number of Urukul #0 ports")
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urukul_ports.append(peripheral["urukul0_ports"])
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if "urukul1_ports" in peripheral:
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if len(peripheral["urukul1_ports"]) != 2:
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raise ValueError("wrong number of Urukul #1 ports")
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urukul_ports.append(peripheral["urukul1_ports"])
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eem.SUServo.add_std(module,
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peripheral["sampler_ports"],
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urukul_ports)
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def peripheral_zotino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Zotino.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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def peripheral_grabber(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port = peripheral["ports"][0]
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port_aux = None
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port_aux2 = None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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port_aux2 = None
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elif len(peripheral["ports"]) == 3:
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port, port_aux, port_aux2 = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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eem.Grabber.add_std(module, port, port_aux, port_aux2)
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def peripheral_mirny(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Mirny.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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def peripheral_fastino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Fastino.add_std(module, peripheral["ports"][0],
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peripheral["log2_width"])
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def peripheral_phaser(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Phaser.add_std(module, peripheral["ports"][0])
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peripheral_processors = {
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"dio": peripheral_dio,
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"urukul": peripheral_urukul,
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"novogorny": peripheral_novogorny,
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"sampler": peripheral_sampler,
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"suservo": peripheral_suservo,
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"zotino": peripheral_zotino,
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"grabber": peripheral_grabber,
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"mirny": peripheral_mirny,
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"fastino": peripheral_fastino,
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"phaser": peripheral_phaser,
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}
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def add_peripherals(module, peripherals):
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for peripheral in peripherals:
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peripheral_processors[peripheral["type"]](module, peripheral)
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@ -6,137 +6,12 @@ from misoc.integration.builder import builder_args, builder_argdict
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from misoc.targets.kasli import soc_kasli_args, soc_kasli_argdict
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from artiq.coredevice import jsondesc
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from artiq.gateware import rtio, eem
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from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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from artiq.gateware import rtio, eem_7series
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.targets.kasli import StandaloneBase, MasterBase, SatelliteBase
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from artiq.build_soc import *
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def peripheral_dio(module, peripheral):
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ttl_classes = {
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"input": ttl_serdes_7series.InOut_8X,
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"output": ttl_serdes_7series.Output_8X
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}
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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if peripheral["edge_counter"]:
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edge_counter_cls = edge_counter.SimpleEdgeCounter
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else:
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edge_counter_cls = None
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eem.DIO.add_std(module, peripheral["ports"][0],
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ttl_classes[peripheral["bank_direction_low"]],
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ttl_classes[peripheral["bank_direction_high"]],
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edge_counter_cls=edge_counter_cls)
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def peripheral_urukul(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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if peripheral["synchronization"]:
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sync_gen_cls = ttl_simple.ClockGen
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else:
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sync_gen_cls = None
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eem.Urukul.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X,
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sync_gen_cls)
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def peripheral_novogorny(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Novogorny.add_std(module, peripheral["ports"][0], ttl_serdes_7series.Output_8X)
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def peripheral_sampler(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port, port_aux = peripheral["ports"][0], None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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eem.Sampler.add_std(module, port, port_aux, ttl_serdes_7series.Output_8X)
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def peripheral_suservo(module, peripheral):
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if len(peripheral["sampler_ports"]) != 2:
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raise ValueError("wrong number of Sampler ports")
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urukul_ports = []
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if len(peripheral["urukul0_ports"]) != 2:
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raise ValueError("wrong number of Urukul #0 ports")
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urukul_ports.append(peripheral["urukul0_ports"])
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if "urukul1_ports" in peripheral:
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if len(peripheral["urukul1_ports"]) != 2:
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raise ValueError("wrong number of Urukul #1 ports")
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urukul_ports.append(peripheral["urukul1_ports"])
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eem.SUServo.add_std(module,
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peripheral["sampler_ports"],
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urukul_ports)
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def peripheral_zotino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Zotino.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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def peripheral_grabber(module, peripheral):
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if len(peripheral["ports"]) == 1:
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port = peripheral["ports"][0]
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port_aux = None
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port_aux2 = None
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elif len(peripheral["ports"]) == 2:
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port, port_aux = peripheral["ports"]
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port_aux2 = None
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elif len(peripheral["ports"]) == 3:
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port, port_aux, port_aux2 = peripheral["ports"]
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else:
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raise ValueError("wrong number of ports")
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eem.Grabber.add_std(module, port, port_aux, port_aux2)
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def peripheral_mirny(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Mirny.add_std(module, peripheral["ports"][0],
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ttl_serdes_7series.Output_8X)
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def peripheral_fastino(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Fastino.add_std(module, peripheral["ports"][0],
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peripheral["log2_width"])
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def peripheral_phaser(module, peripheral):
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if len(peripheral["ports"]) != 1:
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raise ValueError("wrong number of ports")
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eem.Phaser.add_std(module, peripheral["ports"][0])
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peripheral_processors = {
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"dio": peripheral_dio,
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"urukul": peripheral_urukul,
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"novogorny": peripheral_novogorny,
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"sampler": peripheral_sampler,
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"suservo": peripheral_suservo,
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"zotino": peripheral_zotino,
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"grabber": peripheral_grabber,
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"mirny": peripheral_mirny,
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"fastino": peripheral_fastino,
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"phaser": peripheral_phaser,
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}
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def add_peripherals(module, peripherals):
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for peripheral in peripherals:
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peripheral_processors[peripheral["type"]](module, peripheral)
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class GenericStandalone(StandaloneBase):
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def __init__(self, description, hw_rev=None,**kwargs):
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if hw_rev is None:
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@ -159,7 +34,7 @@ class GenericStandalone(StandaloneBase):
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self.grabber_csr_group = []
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self.rtio_channels = []
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add_peripherals(self, description["peripherals"])
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eem_7series.add_peripherals(self, description["peripherals"])
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if hw_rev in ("v1.0", "v1.1"):
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for i in (1, 2):
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print("SFP LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
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@ -204,7 +79,7 @@ class GenericMaster(MasterBase):
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self.grabber_csr_group = []
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self.rtio_channels = []
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add_peripherals(self, description["peripherals"])
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eem_7series.add_peripherals(self, description["peripherals"])
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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@ -237,7 +112,7 @@ class GenericSatellite(SatelliteBase):
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self.grabber_csr_group = []
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self.rtio_channels = []
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add_peripherals(self, description["peripherals"])
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eem_7series.add_peripherals(self, description["peripherals"])
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
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self.rtio_channels.append(rtio.LogChannel())
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