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https://github.com/m-labs/artiq.git
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jesd204_tools: use new syntax from jesd204b core
* requires jesd204b changes as in https://github.com/HarryMakes/jesd204b/tree/gth
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@ -8,14 +8,19 @@ from misoc.interconnect.csr import *
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from jesd204b.common import (JESD204BTransportSettings,
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JESD204BPhysicalSettings,
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JESD204BSettings)
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from jesd204b.phy.gth import GTHChannelPLL as JESD204BGTHChannelPLL
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from jesd204b.phy.gth import (GTHChannelPLL as JESD204BGTHChannelPLL,
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GTHQuadPLL as JESD204BGTHQuadPLL,
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GTHTransmitter as JESD204BGTHTransmitter,
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GTHInit as JESD204BGTHInit,
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GTHTransmitterInterconnect as JESD204BGTHTransmitterInterconnect)
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from jesd204b.phy import JESD204BPhyTX
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from jesd204b.core import JESD204BCoreTX
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from jesd204b.core import JESD204BCoreTXControl
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class UltrascaleCRG(Module, AutoCSR):
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linerate = int(6e9)
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linerate = int(6e9) # linerate = 20*data_rate*4/8 = data_rate*10
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# data_rate = dac_rate/interp_factor
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refclk_freq = int(150e6)
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fabric_freq = int(125e6)
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@ -45,27 +50,96 @@ PhyPads = namedtuple("PhyPads", "txp txn")
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class UltrascaleTX(Module, AutoCSR):
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def __init__(self, platform, sys_crg, jesd_crg, dac):
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def __init__(self, platform, sys_crg, jesd_crg, dac, pll_type="cpll", tx_half=False):
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# Note: In general, the choice between channel and quad PLLs can be made based on the "nominal operating ranges", which are (see UG576, Ch.2):
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# CPLL: 2.0 - 6.25 GHz
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# QPLL0: 9.8 - 16.375 GHz
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# QPLL1: 8.0 - 13.0 GHz
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# However, the exact frequency and/or linerate range should be checked according to the model and speed grade from their corresponding datasheets.
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pll_cls = {
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"cpll": JESD204BGTHChannelPLL,
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"qpll": JESD204BGTHQuadPLL
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}[pll_type]
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ps = JESD204BPhysicalSettings(l=8, m=4, n=16, np=16)
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ts = JESD204BTransportSettings(f=2, s=2, k=16, cs=0)
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settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
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jesd_pads = platform.request("dac_jesd", dac)
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plls = []
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phys = []
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for i in range(len(jesd_pads.txp)):
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cpll = JESD204BGTHChannelPLL(
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jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate)
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self.submodules += cpll
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pll = pll_cls(
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jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate)
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self.submodules += pll
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plls.append(pll)
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# QPLL quads
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if pll_type == "qpll":
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gthe3_common_cfgs = []
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for i in range(0, len(plls), 4):
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# GTHE3_COMMON common signals
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qpll_clk = Signal()
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qpll_refclk = Signal()
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qpll_reset = Signal()
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qpll_lock = Signal()
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# GTHE3_COMMON
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self.specials += pll_cls.get_gthe3_common(
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jesd_crg.refclk, jesd_crg.refclk_freq, jesd_crg.linerate,
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qpll_clk, qpll_refclk, qpll_reset, qpll_lock)
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gthe3_common_cfgs.append({
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"clk": qpll_clk,
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"refclk": qpll_refclk,
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"reset": qpll_reset,
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"lock": qpll_lock
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})
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# Per-channel PLL phys
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for i, pll in enumerate(plls):
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# PhyTX
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phy = JESD204BPhyTX(
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cpll, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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jesd_crg.fabric_freq, transceiver="gth")
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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sys_crg.cd_sys.clk,
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jesd_crg.cd_jesd.clk,
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phy.transmitter.cd_tx.clk)
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pll, jesd_crg.refclk, PhyPads(jesd_pads.txp[i], jesd_pads.txn[i]),
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jesd_crg.fabric_freq, transceiver="gth", tx_half=tx_half)
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phys.append(phy)
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if tx_half:
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platform.add_period_constraint(phy.transmitter.cd_tx_half.clk,
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80*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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sys_crg.cd_sys.clk,
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jesd_crg.cd_jesd.clk,
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phy.transmitter.cd_tx_half.clk)
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else:
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platform.add_period_constraint(phy.transmitter.cd_tx.clk,
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40*1e9/jesd_crg.linerate)
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platform.add_false_path_constraints(
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sys_crg.cd_sys.clk,
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jesd_crg.cd_jesd.clk,
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phy.transmitter.cd_tx.clk)
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# CHANNEL & init interconnects
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for i, (pll, phy) in enumerate(zip(plls, phys)):
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# CPLLs: 1 init per channel
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if pll_type == "cpll":
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phy_channel_cfg = {}
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# Connect reset/lock to init
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pll_reset = pll.reset
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pll_lock = pll.lock
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self.submodules += JESD204BGTHTransmitterInterconnect(
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pll_reset, pll_lock, phy.transmitter, phy.transmitter.init)
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# QPLL: 4 inits and 4 channels per quad
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elif pll_type == "qpll":
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# Connect clk/refclk to CHANNEL
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phy_cfg = gthe3_common_cfgs[int(i//4)]
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phy_channel_cfg = {
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"qpll_clk": phy_cfg["clk"],
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"qpll_refclk": phy_cfg["refclk"]
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}
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# Connect reset/lock to init
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pll_reset = phy_cfg["reset"]
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pll_lock = phy_cfg["lock"]
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if i % 4 == 0:
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self.submodules += JESD204BGTHTransmitterInterconnect(
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pll_reset, pll_lock, phy.transmitter,
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[phys[j].transmitter.init for j in range(i, min(len(phys), i+4))])
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# GTHE3_CHANNEL
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self.specials += JESD204BGTHTransmitter.get_gthe3_channel(
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pll, phy.transmitter, **phy_channel_cfg)
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self.submodules.core = JESD204BCoreTX(
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phys, settings, converter_data_width=64)
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