mirror of https://github.com/m-labs/artiq.git
kasli: integrate WRPLL
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60e5f1c18e
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@ -175,7 +175,10 @@ mod si549 {
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use board_misoc::clock;
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use super::i2c;
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#[cfg(any(soc_platform = "metlino", soc_platform = "sayma_amc", soc_platform = "sayma_rtm"))]
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pub const ADDRESS: u8 = 0x55;
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#[cfg(soc_platform = "kasli")]
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pub const ADDRESS: u8 = 0x67;
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pub fn write(dcxo: i2c::Dcxo, reg: u8, val: u8) -> Result<(), &'static str> {
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i2c::start(dcxo);
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@ -6,6 +6,7 @@ pub struct IoExpander {
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port: u8,
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address: u8,
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virtual_led_mapping: &'static [(u8, u8, u8)],
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iodir: [u8; 2],
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out_current: [u8; 2],
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out_target: [u8; 2],
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}
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@ -22,6 +23,7 @@ impl IoExpander {
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port: 11,
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address: 0x40,
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virtual_led_mapping: &VIRTUAL_LED_MAPPING0,
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iodir: [0xff; 2],
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out_current: [0; 2],
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out_target: [0; 2],
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},
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@ -30,6 +32,7 @@ impl IoExpander {
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port: 11,
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address: 0x42,
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virtual_led_mapping: &VIRTUAL_LED_MAPPING1,
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iodir: [0xff; 2],
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out_current: [0; 2],
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out_target: [0; 2],
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},
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@ -54,15 +57,19 @@ impl IoExpander {
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Ok(())
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}
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fn update_iodir(&self) -> Result<(), &'static str> {
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self.write(0x00, self.iodir[0])?;
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self.write(0x01, self.iodir[1])?;
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Ok(())
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}
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pub fn init(&mut self) -> Result<(), &'static str> {
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self.select()?;
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let mut iodir = [0xffu8; 2];
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for (_led, port, bit) in self.virtual_led_mapping.iter() {
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iodir[*port as usize] &= !(1 << *bit);
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self.iodir[*port as usize] &= !(1 << *bit);
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}
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self.write(0x00, iodir[0])?;
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self.write(0x01, iodir[1])?;
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self.update_iodir()?;
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self.out_current[0] = 0x00;
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self.write(0x12, 0x00)?;
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@ -71,6 +78,12 @@ impl IoExpander {
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Ok(())
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}
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pub fn set_oe(&mut self, port: u8, outputs: u8) -> Result<(), &'static str> {
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self.iodir[port as usize] &= !outputs;
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self.update_iodir()?;
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Ok(())
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}
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pub fn set(&mut self, port: u8, bit: u8, high: bool) {
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if high {
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self.out_target[port as usize] |= 1 << bit;
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@ -464,6 +464,17 @@ pub extern fn main() -> i32 {
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io_expander1 = board_misoc::io_expander::IoExpander::new(1);
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io_expander0.init().expect("I2C I/O expander #0 initialization failed");
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io_expander1.init().expect("I2C I/O expander #1 initialization failed");
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#[cfg(has_wrpll)]
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{
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io_expander0.set_oe(1, 1 << 7).unwrap();
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io_expander0.set(1, 7, true);
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io_expander0.service().unwrap();
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io_expander1.set_oe(0, 1 << 7).unwrap();
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io_expander1.set_oe(1, 1 << 7).unwrap();
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io_expander1.set(0, 7, true);
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io_expander1.set(1, 7, true);
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io_expander1.service().unwrap();
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}
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}
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#[cfg(has_si5324)]
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@ -20,6 +20,7 @@ from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, edge_counter
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from artiq.gateware import eem
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from artiq.gateware.drtio.transceiver import gtp_7series
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from artiq.gateware.drtio.siphaser import SiPhaser7Series
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from artiq.gateware.drtio.wrpll import WRPLL, DDMTDSamplerGTP
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from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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@ -452,7 +453,7 @@ class SatelliteBase(BaseSoC):
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, **kwargs):
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def __init__(self, rtio_clk_freq=125e6, enable_sata=False, *, with_wrpll=False, **kwargs):
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BaseSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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@ -556,24 +557,38 @@ class SatelliteBase(BaseSoC):
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0"
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else platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.clk125_div2, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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rtio_clk_period = 1e9/rtio_clk_freq
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if with_wrpll:
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self.submodules.wrpll_sampler = DDMTDSamplerGTP(
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self.drtio_transceiver,
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platform.request("cdr_clk_clean_fabric"))
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self.submodules.wrpll = WRPLL(
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helper_clk_pads=platform.request("ddmtd_helper_clk"),
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main_dcxo_i2c=platform.request("ddmtd_main_dcxo_i2c"),
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helper_dxco_i2c=platform.request("ddmtd_helper_dcxo_i2c"),
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ddmtd_inputs=self.wrpll_sampler)
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self.csr_devices.append("wrpll")
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platform.add_period_constraint(self.wrpll.cd_helper.clk, rtio_clk_period*0.99)
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platform.add_false_path_constraints(self.crg.cd_sys.clk, self.wrpll.cd_helper.clk)
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else:
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk") if platform.hw_rev == "v2.0"
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else platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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ref_clk=self.crg.clk125_div2, ref_div2=True,
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rtio_clk_freq=rtio_clk_freq)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
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self.csr_devices.append("siphaser")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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gtp = self.drtio_transceiver.gtps[0]
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platform.add_period_constraint(gtp.txoutclk, rtio_clk_period)
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platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
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@ -658,15 +673,20 @@ def main():
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parser.add_argument("-V", "--variant", default="tester",
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help="variant: {} (default: %(default)s)".format(
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"/".join(sorted(VARIANTS.keys()))))
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parser.add_argument("--with-wrpll", default=False, action="store_true")
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args = parser.parse_args()
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argdict = dict()
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if args.with_wrpll:
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argdict["with_wrpll"] = True
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variant = args.variant.lower()
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try:
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cls = VARIANTS[variant]
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except KeyError:
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raise SystemExit("Invalid variant (-V/--variant)")
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soc = cls(**soc_kasli_argdict(args))
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soc = cls(**soc_kasli_argdict(args), **argdict)
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build_artiq_soc(soc, builder_argdict(args))
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