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wrpll: fix run signal

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cw-mlabs 2020-07-27 12:55:50 +08:00 committed by Sébastien Bourdeauducq
parent 8dd9a6d024
commit e4b16428f5
1 changed files with 1 additions and 1 deletions
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artiq/gateware/drtio/wrpll/si549.py
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@ -115,7 +115,7 @@ class I2CMasterMachine(Module):
run = Signal()
idle = Signal()
self.comb += [
run.eq(self.start | self.stop | self.write),
run.eq((self.start | self.stop | self.write) & self.ready),
idle.eq(~run & fsm.ongoing("IDLE")),
self.cg.ce.eq(~idle),
fsm.ce.eq(run | self.cg.clk2x),