M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

wrpll: fix run signal

pull/1499/head
cw-mlabs 2020-07-27 12:55:50 +08:00 committed by Sébastien Bourdeauducq
parent 8dd9a6d024
commit e4b16428f5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/drtio/wrpll/si549.py
View File

@ -115,7 +115,7 @@ class I2CMasterMachine(Module):
run = Signal()
idle = Signal()
self.comb += [
run.eq(self.start | self.stop | self.write),
run.eq((self.start | self.stop | self.write) & self.ready),
idle.eq(~run & fsm.ongoing("IDLE")),
self.cg.ce.eq(~idle),
fsm.ce.eq(run | self.cg.clk2x),