kasli2: add false path constraint for wrpll helper clock

2020-10-08 16:19:44 +08:00 · 2020-10-08 16:19:44 +08:00 · 96a5df0dc6
parent 6248970ef8
commit 96a5df0dc6
1 changed files with 3 additions and 0 deletions
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@ -614,6 +614,9 @@ class SatelliteBase(BaseSoC):
        platform.add_false_path_constraints(
            self.crg.cd_sys.clk,
            gtp.txoutclk, gtp.rxoutclk)
+        if with_wrpll:
+            platform.add_false_path_constraints(
+                self.wrpll.cd_helper.clk, gtp.rxoutclk)
        for gtp in self.drtio_transceiver.gtps[1:]:
            platform.add_period_constraint(gtp.rxoutclk, rtio_clk_period)
            platform.add_false_path_constraints(