drtio_tuple -> drtio_context

This avoids reallocation while transfering binaries.

.gitignore

@@ -3,3 +3,11 @@ examples/*.elf
 __pycache__
 
 build
+
+src/libboard_artiq/Cargo.toml
+src/libc/Cargo.toml
+src/libdyld/Cargo.toml
+src/libio/Cargo.toml
+src/libksupport/Cargo.toml
+src/runtime/Cargo.toml
+src/satman/Cargo.toml

LICENSE

@@ -0,0 +1,165 @@
+                   GNU LESSER GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+
+  This version of the GNU Lesser General Public License incorporates
+the terms and conditions of version 3 of the GNU General Public
+License, supplemented by the additional permissions listed below.
+
+  0. Additional Definitions.
+
+  As used herein, "this License" refers to version 3 of the GNU Lesser
+General Public License, and the "GNU GPL" refers to version 3 of the GNU
+General Public License.
+
+  "The Library" refers to a covered work governed by this License,
+other than an Application or a Combined Work as defined below.
+
+  An "Application" is any work that makes use of an interface provided
+by the Library, but which is not otherwise based on the Library.
+Defining a subclass of a class defined by the Library is deemed a mode
+of using an interface provided by the Library.
+
+  A "Combined Work" is a work produced by combining or linking an
+Application with the Library.  The particular version of the Library
+with which the Combined Work was made is also called the "Linked
+Version".
+
+  The "Minimal Corresponding Source" for a Combined Work means the
+Corresponding Source for the Combined Work, excluding any source code
+for portions of the Combined Work that, considered in isolation, are
+based on the Application, and not on the Linked Version.
+
+  The "Corresponding Application Code" for a Combined Work means the
+object code and/or source code for the Application, including any data
+and utility programs needed for reproducing the Combined Work from the
+Application, but excluding the System Libraries of the Combined Work.
+
+  1. Exception to Section 3 of the GNU GPL.
+
+  You may convey a covered work under sections 3 and 4 of this License
+without being bound by section 3 of the GNU GPL.
+
+  2. Conveying Modified Versions.
+
+  If you modify a copy of the Library, and, in your modifications, a
+facility refers to a function or data to be supplied by an Application
+that uses the facility (other than as an argument passed when the
+facility is invoked), then you may convey a copy of the modified
+version:
+
+   a) under this License, provided that you make a good faith effort to
+   ensure that, in the event an Application does not supply the
+   function or data, the facility still operates, and performs
+   whatever part of its purpose remains meaningful, or
+
+   b) under the GNU GPL, with none of the additional permissions of
+   this License applicable to that copy.
+
+  3. Object Code Incorporating Material from Library Header Files.
+
+  The object code form of an Application may incorporate material from
+a header file that is part of the Library.  You may convey such object
+code under terms of your choice, provided that, if the incorporated
+material is not limited to numerical parameters, data structure
+layouts and accessors, or small macros, inline functions and templates
+(ten or fewer lines in length), you do both of the following:
+
+   a) Give prominent notice with each copy of the object code that the
+   Library is used in it and that the Library and its use are
+   covered by this License.
+
+   b) Accompany the object code with a copy of the GNU GPL and this license
+   document.
+
+  4. Combined Works.
+
+  You may convey a Combined Work under terms of your choice that,
+taken together, effectively do not restrict modification of the
+portions of the Library contained in the Combined Work and reverse
+engineering for debugging such modifications, if you also do each of
+the following:
+
+   a) Give prominent notice with each copy of the Combined Work that
+   the Library is used in it and that the Library and its use are
+   covered by this License.
+
+   b) Accompany the Combined Work with a copy of the GNU GPL and this license
+   document.
+
+   c) For a Combined Work that displays copyright notices during
+   execution, include the copyright notice for the Library among
+   these notices, as well as a reference directing the user to the
+   copies of the GNU GPL and this license document.
+
+   d) Do one of the following:
+
+       0) Convey the Minimal Corresponding Source under the terms of this
+       License, and the Corresponding Application Code in a form
+       suitable for, and under terms that permit, the user to
+       recombine or relink the Application with a modified version of
+       the Linked Version to produce a modified Combined Work, in the
+       manner specified by section 6 of the GNU GPL for conveying
+       Corresponding Source.
+
+       1) Use a suitable shared library mechanism for linking with the
+       Library.  A suitable mechanism is one that (a) uses at run time
+       a copy of the Library already present on the user's computer
+       system, and (b) will operate properly with a modified version
+       of the Library that is interface-compatible with the Linked
+       Version.
+
+   e) Provide Installation Information, but only if you would otherwise
+   be required to provide such information under section 6 of the
+   GNU GPL, and only to the extent that such information is
+   necessary to install and execute a modified version of the
+   Combined Work produced by recombining or relinking the
+   Application with a modified version of the Linked Version. (If
+   you use option 4d0, the Installation Information must accompany
+   the Minimal Corresponding Source and Corresponding Application
+   Code. If you use option 4d1, you must provide the Installation
+   Information in the manner specified by section 6 of the GNU GPL
+   for conveying Corresponding Source.)
+
+  5. Combined Libraries.
+
+  You may place library facilities that are a work based on the
+Library side by side in a single library together with other library
+facilities that are not Applications and are not covered by this
+License, and convey such a combined library under terms of your
+choice, if you do both of the following:
+
+   a) Accompany the combined library with a copy of the same work based
+   on the Library, uncombined with any other library facilities,
+   conveyed under the terms of this License.
+
+   b) Give prominent notice with the combined library that part of it
+   is a work based on the Library, and explaining where to find the
+   accompanying uncombined form of the same work.
+
+  6. Revised Versions of the GNU Lesser General Public License.
+
+  The Free Software Foundation may publish revised and/or new versions
+of the GNU Lesser General Public License from time to time. Such new
+versions will be similar in spirit to the present version, but may
+differ in detail to address new problems or concerns.
+
+  Each version is given a distinguishing version number. If the
+Library as you received it specifies that a certain numbered version
+of the GNU Lesser General Public License "or any later version"
+applies to it, you have the option of following the terms and
+conditions either of that published version or of any later version
+published by the Free Software Foundation. If the Library as you
+received it does not specify a version number of the GNU Lesser
+General Public License, you may choose any version of the GNU Lesser
+General Public License ever published by the Free Software Foundation.
+
+  If the Library as you received it specifies that a proxy can decide
+whether future versions of the GNU Lesser General Public License shall
+apply, that proxy's public statement of acceptance of any version is
+permanent authorization for you to choose that version for the
+Library.

README.md

@@ -1,26 +1,120 @@
-Configure Nix channels:
+ARTIQ on Zynq
+=============
+
+How to use
+----------
+
+1. [Install ARTIQ](https://m-labs.hk/artiq/manual/installing.html). Get the corresponding version to the ``artiq-zynq`` version you are targeting.
+2. To obtain firmware binaries, use AFWS or build your own; see [the ARTIQ manual](https://m-labs.hk/artiq/manual/building_developing.html) for detailed instructions or skip to "Development" below. ZC706 variants only can also be downloaded from latest successful build on [Hydra](https://nixbld.m-labs.hk/).
+3. Place ``boot.bin`` file at the root ``/`` of a FAT-formatted SD card.
+4. Optionally, create a ``config.txt`` configuration file containing ``key=value`` pairs on each line and place it at the root of the SD card. See below for valid keys. The ``ip``, ``ip6`` and ``mac`` keys can be used to set networking information. If these keys are not found, the firmware will use default values which may or may not be compatible with your network.
+5. Insert the SD card into the board and set the board to boot from the SD card. For ZC706, this is achieved by placing the large DIP switch SW11 into the 00110 position. On Kasli-SoC, place the BOOT MODE switches to SD.
+6. Power up the board. After successful boot the firmware should respond to ping at its IP addresses. Boot output can be observed from UART at 115200bps 8-N-1.
+7. Create and use an ARTIQ device database as usual.
+
+Configuration
+-------------
+
+Configuring the device is done using the ``config.txt`` text file at the root of the SD card plus optionally a ``config`` folder. When searching for a configuration key, the firmware first looks for a file named ``/config/[key].bin`` and, if it exists, returns the contents of that file. If not, it looks into ``/config.txt``, which should contain a list of ``key=value`` pairs, one per line. ``config.txt`` should be used for most keys but the ``config`` folder allows for setting configuration values which consist of binary data, such as the startup kernel.
+
+The following configuration keys are available among others:
+
+- ``mac``: Ethernet MAC address.
+- ``ip``: IPv4 address.
+- ``ip6``: IPv6 address.
+- ``idle_kernel``: idle kernel in ELF format (as produced by ``artiq_compile``).
+- ``startup_kernel``: startup kernel in ELF format (as produced by ``artiq_compile``).
+- ``rtio_clock``: source of RTIO clock; valid values are ``ext0_bypass`` and ``int_125``.
+
+See [ARTIQ manual](https://m-labs.hk/artiq/manual-beta/core_device.html#configuration-storage) for full list. Configurations can be read/written/removed with ``artiq_coremgmt``. Config erase is not implemented, as it isn't particularly useful.
+
+For convenience, the ``boot`` key can be used with ``artiq_coremgmt`` and a ``boot.bin`` file to replace firmware/gateware in a running system. This key is read-only. When loading ``boot.bin`` onto the SD card directly, place it at the root and not in the ``config`` folder.
+
+Development instructions
+------------------------
+
+ARTIQ on Zynq is packaged using [Nix](https://nixos.org) Flakes. Install Nix 2.8+ and enable flakes by adding ``experimental-features = nix-command flakes`` to ``nix.conf`` (e.g. ``~/.config/nix/nix.conf``).
+
+**Pure build with Nix:**
 
 ```shell
-nix-channel --add https://nixbld.m-labs.hk/channel/custom/artiq/fast-beta/artiq-fast
-nix-channel --update
+nix build .#zc706-nist_clock-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock-sd or etc
 ```
 
-Pure build with Nix:
+Run ``nix flake show`` to see all valid build targets. Targets suffixed with ``-jtag`` produce separate firmware and gateware files, intended for use in booting via JTAG server/Ethernet, e.g. ``./remote_run.sh -i`` with a remote JTAG server. Targets suffixed with ``-sd`` will produce ``boot.bin`` file suitable for SD card boot. ``-firmware`` and ``-gateware`` respectively build firmware and gateware only.
+
+The Kasli-SoC target requires a system description file as input. See ARTIQ manual for exact instructions or use incremental build.
+
+**Impure incremental build:**
+
+For boards with fixed variants, i.e. ZC706, etc. :
 
 ```shell
-nix-build -A zc706-simple-jtag  # or zc706-nist_qc2-jtag or zc706-nist_clock-jtag
-./remote_run.sh
-```
-
-Impure incremental build:
-
-```shell
-nix-shell
+nix develop
 cd src
-./zc706.py -g ../build/gateware  # build gateware
-make                             # build firmware
-cd ..
-./remote_run.sh -i
+gateware/<board>.py -g ../build/gateware -V <variant> # gateware
+make GWARGS="-V <variant>" <runtime/satman>    # firmware
 ```
 
-The impure build process can also be used on non-Nix systems.
+For boards with system descriptions, i.e. Kasli-SoC, etc. :
+
+```shell
+nix develop
+cd src
+gateware/<board>.py -g ../build/gateware <description.json> # gateware
+make TARGET=<board> GWARGS="path/to/description.json" <runtime/satman> # firmware
+```
+
+``szl.elf`` can be obtained with:
+
+```shell
+nix build git+https://git.m-labs.hk/m-labs/zynq-rs#<board>-szl
+```
+
+To generate ``boot.bin`` use ``mkbootimage``, e.g.:
+
+```shell
+echo "the_ROM_image:
+    {
+        [bootloader]result/szl.elf
+        gateware/top.bit
+        firmware/armv7-none-eabihf/release/<runtime/satman>
+    }
+    EOF" >> boot.bif
+mkbootimage boot.bif boot.bin
+```
+
+Notes:
+
+- The impure build process is also compatible with non-Nix systems.
+- Firmware type must be either ``runtime`` for DRTIO-less or DRTIO master variants, or ``satman`` for DRTIO satellite.
+- If the board is connected to the local machine by JTAG, use the ``local_run.sh`` script.
+- A known Xilinx hardware bug prevents repeatedly loading the bootloader over JTAG without a POR reset. If booting over JTAG, install a jumper on ``PS_POR_B`` and use the POR reset script [here](https://git.m-labs.hk/M-Labs/zynq-rs/src/branch/master/kasli_soc_por.py).
+
+Pre-Commit Hooks
+----------------
+
+You are strongly recommended to use the provided pre-commit hooks to automatically reformat files and check for non-optimal Rust/C/C++ practices. Run `pre-commit install` to install the hook and `pre-commit` will automatically run `cargo fmt`, `cargo clippy`, and `clang-format` for you.
+
+Several things to note:
+
+- If `cargo fmt`, `cargo clippy`, or `clang-format` returns an error, the pre-commit hook will fail. You should fix all errors before trying to commit again.
+- If `cargo fmt` or `clang-format` reformats some files, the pre-commit hook will also fail. You should review the changes and, if satisfied, try to commit again.
+
+License
+-------
+
+Copyright (C) 2019-2024 M-Labs Limited.
+
+ARTIQ is free software: you can redistribute it and/or modify
+it under the terms of the GNU Lesser General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+ARTIQ is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU Lesser General Public License for more details.
+
+You should have received a copy of the GNU Lesser General Public License
+along with ARTIQ.  If not, see <http://www.gnu.org/licenses/>.

default.nix

@@ -1,125 +0,0 @@
-{
-  mozillaOverlay ? import (builtins.fetchTarball https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz),
-}:
-
-let
-  pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
-  rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
-  artiqpkgs = import <artiq-fast/default.nix> { inherit pkgs; };
-  vivado = import <artiq-fast/vivado.nix> { inherit pkgs; };
-  zc706-fsbl = import ./fsbl.nix { inherit pkgs; };
-  mkbootimage = (import ./mkbootimage.nix { inherit pkgs; });
-  build-zc706 = { variant }: let
-    firmware = rustPlatform.buildRustPackage rec {
-      name = "zc706-${variant}-firmware";
-      version = "0.1.0";
-
-      src = ./src;
-      cargoSha256 = "05x9l6vrppvhr4qphpjklq4jlhyid1y9xg6qa52s7p7564gcvg4w";
-
-      nativeBuildInputs = [
-        pkgs.gnumake
-        (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
-        pkgs.cargo-xbuild
-        pkgs.llvm_9
-        pkgs.clang_9
-      ];
-      buildPhase = ''
-        export XARGO_RUST_SRC="${rustPlatform.rust.rustc.src}/src"
-        export CARGO_HOME=$(mktemp -d cargo-home.XXX)
-        make VARIANT=${variant}
-      '';
-
-      installPhase = ''
-        mkdir -p $out $out/nix-support
-        cp ../build/firmware/armv7-none-eabihf/release/runtime $out/runtime.elf
-        cp ../build/firmware/armv7-none-eabihf/release/szl $out/szl.elf
-        echo file binary-dist $out/runtime.elf >> $out/nix-support/hydra-build-products
-        echo file binary-dist $out/szl.elf >> $out/nix-support/hydra-build-products
-      '';
-
-      doCheck = false;
-      dontFixup = true;
-    };
-    gateware = pkgs.runCommand "zc706-${variant}-gateware"
-      {
-        nativeBuildInputs = [ 
-          (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
-          vivado
-        ];
-      }
-      ''
-        python ${./src/zc706.py} -g build -V ${variant}
-        mkdir -p $out $out/nix-support
-        cp build/top.bit $out
-        echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
-      '';
-
-    # SZL startup
-    jtag = pkgs.runCommand "zc706-${variant}-jtag" {}
-      ''
-        mkdir $out
-        ln -s ${firmware}/szl.elf $out
-        ln -s ${gateware}/top.bit $out
-      '';
-    sd = pkgs.runCommand "zc706-${variant}-sd"
-      {
-        buildInputs = [ mkbootimage ];
-      }
-      ''
-      # Do not use "long" paths in boot.bif, because embedded developers
-      # can't write software (mkbootimage will segfault).
-      bifdir=`mktemp -d`
-      cd $bifdir
-      ln -s ${firmware}/szl.elf szl.elf
-      ln -s ${gateware}/top.bit top.bit
-      cat > boot.bif << EOF
-      the_ROM_image:
-      {
-        [bootloader]szl.elf
-        top.bit
-      }
-      EOF
-      mkdir $out $out/nix-support
-      mkbootimage boot.bif $out/boot.bin
-      echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
-      '';
-
-    # FSBL startup
-    fsbl-sd = pkgs.runCommand "zc706-${variant}-fsbl-sd"
-      {
-        buildInputs = [ mkbootimage ];
-      }
-      ''
-      # TODO: use self-built fsbl
-      bifdir=`mktemp -d`
-      cd $bifdir
-      ln -s ${zc706-fsbl}/fsbl.elf fsbl.elf
-      ln -s ${gateware}/top.bit top.bit
-      ln -s ${firmware}/runtime.elf runtime.elf
-      cat > boot.bif << EOF
-      the_ROM_image:
-      {
-        [bootloader]fsbl.elf
-        top.bit
-        runtime.elf
-      }
-      EOF
-      mkdir $out $out/nix-support
-      mkbootimage boot.bif $out/boot.bin
-      echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
-      '';
-  in {
-    "zc706-${variant}-firmware" = firmware;
-    "zc706-${variant}-gateware" = gateware;
-    "zc706-${variant}-jtag" = jtag;
-    "zc706-${variant}-sd" = sd;
-    "zc706-${variant}-fsbl-sd" = fsbl-sd;
-  };
-in
-  (
-    (build-zc706 { variant = "simple"; }) //
-    (build-zc706 { variant = "nist_clock"; }) //
-    (build-zc706 { variant = "nist_qc2"; }) //
-    { inherit zc706-fsbl; }
-  )

demo.json

@@ -0,0 +1,60 @@
+{
+    "target": "kasli_soc",
+    "variant": "demo",
+    "hw_rev": "v1.0",
+    "base": "standalone",
+    "peripherals": [
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}

examples/device_db.py

@@ -1,3 +1,5 @@
+# For NIST_QC2
+
 device_db = {
     "core": {
         "type": "local",
@@ -6,33 +8,69 @@ device_db = {
         "arguments": {
             "host": "192.168.1.52",
             "ref_period": 1e-9,
-            "ref_multiplier": 1,
+            "ref_multiplier": 8,
             "target": "cortexa9"
         }
     },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache"
+    },
+    "core_dma": {
+        "type": "local",
+        "module": "artiq.coredevice.dma",
+        "class": "CoreDMA"
+    },
+
+    "i2c_switch": {
+        "type": "local",
+        "module": "artiq.coredevice.i2c",
+        "class": "PCA9548"
+    },
 
     "led0": {
         "type": "local",
         "module": "artiq.coredevice.ttl",
         "class": "TTLOut",
-        "arguments": {"channel": 0},
-    },
-    "led1": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 1},
-    },
-    "led2": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 2}
-    },
-    "led3": {
-        "type": "local",
-        "module": "artiq.coredevice.ttl",
-        "class": "TTLOut",
-        "arguments": {"channel": 3}
+        "arguments": {"channel": 41},
     },
 }
+
+# TTLs on QC2 backplane
+for i in range(40):
+    device_db["ttl" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": i}
+    }
+
+device_db["ad9914dds0"] = {
+    "type": "local",
+    "module": "artiq.coredevice.ad9914",
+    "class": "AD9914",
+    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 0},
+}
+device_db["ad9914dds1"] = {
+    "type": "local",
+    "module": "artiq.coredevice.ad9914",
+    "class": "AD9914",
+    "arguments": {"sysclk": 3e9, "bus_channel": 50, "channel": 1},
+}
+
+for i in range(4):
+    device_db["ttl"+str(i)+"_counter"] = {
+        "type": "local",
+        "module": "artiq.coredevice.edge_counter",
+        "class": "EdgeCounter",
+        "arguments": {"channel": 52+i}
+    }
+
+# for ARTIQ test suite
+device_db.update(
+    loop_out="ttl0",
+    loop_in="ttl1",
+    ttl_out="ttl2",
+    ttl_out_serdes="ttl2",
+)

examples/dma.py

@@ -0,0 +1,26 @@
+from artiq.experiment import *
+
+class DMAPulses(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("core_dma")
+        self.setattr_device("led0")
+
+    @kernel
+    def record(self):
+        with self.core_dma.record("pulse"):
+            delay(200*ms)
+            # all RTIO operations now go to the "pulse"
+            # DMA buffer, instead of being executed immediately.
+            self.led0.pulse(500*ms)
+
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.record()
+        # prefetch the address of the DMA buffer
+        # for faster playback trigger
+        pulse_handle = self.core_dma.get_handle("pulse")
+        self.core.break_realtime()
+        self.core_dma.playback_handle(pulse_handle)

examples/ebaz4205/device_db.py

@@ -0,0 +1,78 @@
+core_addr = "192.168.1.57"
+
+device_db = {
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {
+            "host": core_addr,
+            "ref_period": 1e-9,
+            "target": "cortexa9",
+        },
+    },
+    "core_log": {
+        "type": "controller",
+        "host": "::1",
+        "port": 1068,
+        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr,
+    },
+    "core_moninj": {
+        "type": "controller",
+        "host": "::1",
+        "port_proxy": 1383,
+        "port": 1384,
+        "command": "aqctl_moninj_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} "
+        + core_addr,
+    },
+    "core_analyzer": {
+        "type": "controller",
+        "host": "::1",
+        "port_proxy": 1385,
+        "port": 1386,
+        "command": "aqctl_coreanalyzer_proxy --port-proxy {port_proxy} --port-control {port} --bind {bind} "
+        + core_addr,
+    },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache",
+    },
+    "core_dma": {"type": "local", "module": "artiq.coredevice.dma", "class": "CoreDMA"},
+    "led0": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 0},
+    },
+    "led1": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 1},
+    },
+}
+
+# TTLs starting at RTIO channel 2, ending at RTIO channel 15
+for i in range(2, 16):
+    device_db["ttl" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLInOut",
+        "arguments": {"channel": i},
+    }
+
+device_db.update(
+    spi0={
+        "type": "local",
+        "module": "artiq.coredevice.spi2",
+        "class": "SPIMaster",
+        "arguments": {"channel": 16},
+    },
+    dds0={
+        "type": "local",
+        "module": "artiq.coredevice.ad9834",
+        "class": "AD9834",
+        "arguments": {"spi_device": "spi0"},
+    },
+)

examples/exception.py

@@ -0,0 +1,38 @@
+from artiq.experiment import *
+from artiq.language.core import TerminationRequested
+
+class ExceptionDemo(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("led0")
+
+    def foo(self):
+        print("raise error")
+        raise Exception
+
+    def termination(self):
+        raise TerminationRequested
+
+    @rpc
+    def remote(self):
+        raise Exception
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        try:
+            try:
+                self.foo()
+            except ValueError as e:
+                print("should not trigger this")
+        except:
+            print("catch all")
+
+        try:
+            self.remote()
+        except:
+            print("Error!")
+
+        print("Uncaught error at last")
+        self.termination()
+

flake.lock

@@ -0,0 +1,248 @@
+{
+  "nodes": {
+    "artiq": {
+      "inputs": {
+        "artiq-comtools": "artiq-comtools",
+        "nixpkgs": "nixpkgs",
+        "rust-overlay": "rust-overlay",
+        "sipyco": "sipyco",
+        "src-migen": "src-migen",
+        "src-misoc": "src-misoc",
+        "src-pythonparser": "src-pythonparser"
+      },
+      "locked": {
+        "lastModified": 1731734344,
+        "narHash": "sha256-2vLRo9D5wDs5FArpc2pOfuKFrhnqIKjtZos88VJahhc=",
+        "ref": "refs/heads/master",
+        "rev": "27d54cb8f3a394b4f4adcbb3c2c9160c5bf3df47",
+        "revCount": 9049,
+        "type": "git",
+        "url": "https://github.com/m-labs/artiq.git"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://github.com/m-labs/artiq.git"
+      }
+    },
+    "artiq-comtools": {
+      "inputs": {
+        "flake-utils": "flake-utils",
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ],
+        "sipyco": [
+          "artiq",
+          "sipyco"
+        ]
+      },
+      "locked": {
+        "lastModified": 1720768567,
+        "narHash": "sha256-3VoK7o5MtHtbHLrc6Pv+eQWFtaz5Gd/YWyV5TD3c5Ss=",
+        "owner": "m-labs",
+        "repo": "artiq-comtools",
+        "rev": "f93570d8f2ed5a3cfb3e1c16ab00f2540551e994",
+        "type": "github"
+      },
+      "original": {
+        "owner": "m-labs",
+        "repo": "artiq-comtools",
+        "type": "github"
+      }
+    },
+    "flake-utils": {
+      "inputs": {
+        "systems": "systems"
+      },
+      "locked": {
+        "lastModified": 1710146030,
+        "narHash": "sha256-SZ5L6eA7HJ/nmkzGG7/ISclqe6oZdOZTNoesiInkXPQ=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "b1d9ab70662946ef0850d488da1c9019f3a9752a",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    },
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1731319897,
+        "narHash": "sha256-PbABj4tnbWFMfBp6OcUK5iGy1QY+/Z96ZcLpooIbuEI=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "dc460ec76cbff0e66e269457d7b728432263166c",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixos-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "artiq": "artiq",
+        "zynq-rs": "zynq-rs"
+      }
+    },
+    "rust-overlay": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1719454714,
+        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "oxalica",
+        "ref": "snapshot/2024-08-01",
+        "repo": "rust-overlay",
+        "type": "github"
+      }
+    },
+    "rust-overlay_2": {
+      "inputs": {
+        "nixpkgs": [
+          "zynq-rs",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1719454714,
+        "narHash": "sha256-MojqG0lyUINkEk0b3kM2drsU5vyaF8DFZe/FAlZVOGs=",
+        "owner": "oxalica",
+        "repo": "rust-overlay",
+        "rev": "d1c527659cf076ecc4b96a91c702d080b213801e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "oxalica",
+        "ref": "snapshot/2024-08-01",
+        "repo": "rust-overlay",
+        "type": "github"
+      }
+    },
+    "sipyco": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ]
+      },
+      "locked": {
+        "lastModified": 1728371104,
+        "narHash": "sha256-PPnAyDedUQ7Og/Cby9x5OT9wMkNGTP8GS53V6N/dk4w=",
+        "owner": "m-labs",
+        "repo": "sipyco",
+        "rev": "094a6cd63ffa980ef63698920170e50dc9ba77fd",
+        "type": "github"
+      },
+      "original": {
+        "owner": "m-labs",
+        "repo": "sipyco",
+        "type": "github"
+      }
+    },
+    "src-migen": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1727677091,
+        "narHash": "sha256-Zg3SQnTwMM/VkOGKogbPyuCC2NhLy8HB2SPEUWWNgCU=",
+        "owner": "m-labs",
+        "repo": "migen",
+        "rev": "c19ae9f8ae162ffe2d310a92bfce53ac2a821bc8",
+        "type": "github"
+      },
+      "original": {
+        "owner": "m-labs",
+        "repo": "migen",
+        "type": "github"
+      }
+    },
+    "src-misoc": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1729234629,
+        "narHash": "sha256-TLsTCXV5AC2xh+bS7EhBVBKqdqIU3eKrnlWcFF9LtAM=",
+        "ref": "refs/heads/master",
+        "rev": "6085a312bca26adeca6584e37d08c8ba2e1d6e38",
+        "revCount": 2460,
+        "submodules": true,
+        "type": "git",
+        "url": "https://github.com/m-labs/misoc.git"
+      },
+      "original": {
+        "submodules": true,
+        "type": "git",
+        "url": "https://github.com/m-labs/misoc.git"
+      }
+    },
+    "src-pythonparser": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1628745371,
+        "narHash": "sha256-p6TgeeaK4NEmbhimEXp31W8hVRo4DgWmcCoqZ+UdN60=",
+        "owner": "m-labs",
+        "repo": "pythonparser",
+        "rev": "5413ee5c9f8760e95c6acd5d6e88dabb831ad201",
+        "type": "github"
+      },
+      "original": {
+        "owner": "m-labs",
+        "repo": "pythonparser",
+        "type": "github"
+      }
+    },
+    "systems": {
+      "locked": {
+        "lastModified": 1681028828,
+        "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
+        "owner": "nix-systems",
+        "repo": "default",
+        "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-systems",
+        "repo": "default",
+        "type": "github"
+      }
+    },
+    "zynq-rs": {
+      "inputs": {
+        "nixpkgs": [
+          "artiq",
+          "nixpkgs"
+        ],
+        "rust-overlay": "rust-overlay_2"
+      },
+      "locked": {
+        "lastModified": 1731749494,
+        "narHash": "sha256-WGigAhvVCGN5YZ1dHPyvoqAh47W1Gtph036O1aKFlLE=",
+        "ref": "refs/heads/master",
+        "rev": "12975de2e110d7948bf47b768559f727d0abc8fc",
+        "revCount": 655,
+        "type": "git",
+        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
+      },
+      "original": {
+        "type": "git",
+        "url": "https://git.m-labs.hk/m-labs/zynq-rs"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}

flake.nix

@@ -0,0 +1,399 @@
+{
+  description = "ARTIQ port to the Zynq-7000 platform";
+
+  inputs.artiq.url = git+https://github.com/m-labs/artiq.git;
+  inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
+  inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
+
+  outputs = { self, zynq-rs, artiq }:
+  let
+    pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import zynq-rs.inputs.rust-overlay) ]; };
+    zynqpkgs = zynq-rs.packages.x86_64-linux;
+    artiqpkgs = artiq.packages.x86_64-linux;
+    llvmPackages_11 = zynq-rs.llvmPackages_11;
+
+    rust = zynq-rs.rust;
+    rustPlatform = zynq-rs.rustPlatform;
+
+    fastnumbers = pkgs.python3Packages.buildPythonPackage rec {
+      pname = "fastnumbers";
+      version = "5.1.0";
+
+      src = pkgs.python3Packages.fetchPypi {
+        inherit pname version;
+        sha256 = "sha256-4JLTP4uVwxcaL7NOV57+DFSwKQ3X+W/6onYkN2AdkKc=";
+      };
+    };
+
+    artiq-netboot = pkgs.python3Packages.buildPythonPackage rec {
+      pname = "artiq-netboot";
+      version = "unstable-2020-10-15";
+
+      src = pkgs.fetchgit {
+        url = "https://git.m-labs.hk/m-labs/artiq-netboot.git";
+        rev = "04f69eb07df73abe4b89fde2c24084f7664f2104";
+        sha256 = "0ql4fr8m8gpb2yql8aqsdqsssxb8zqd6l65kl1f6s9845zy7shs9";
+      };
+    };
+
+    ramda = pkgs.python3Packages.buildPythonPackage {
+      pname = "ramda";
+      version = "unstable-2020-04-11";
+
+      src = pkgs.fetchFromGitHub {
+        owner = "peteut";
+        repo = "ramda.py";
+        rev = "d315a9717ebd639366bf3fe26bad9e3d08ec3c49";
+        sha256 = "sha256-bmSt/IHDnULsZjsC6edELnNH7LoJSVF4L4XhwBAXRkY=";
+      };
+
+      nativeBuildInputs = with pkgs.python3Packages; [ pbr ];
+      propagatedBuildInputs = with pkgs.python3Packages; [ future fastnumbers ];
+
+      checkInputs = with pkgs.python3Packages; [ pytest ];
+      checkPhase = "pytest";
+      doCheck = false;
+
+      preBuild = ''
+        export PBR_VERSION=0.5.5
+      '';
+    };
+
+    migen-axi = pkgs.python3Packages.buildPythonPackage {
+      pname = "migen-axi";
+      version = "unstable-2023-01-06";
+
+      src = pkgs.fetchFromGitHub {
+        owner = "peteut";
+        repo = "migen-axi";
+        rev = "27eaa84a70a3abfe1930c86c36c4de2cd652da35";
+        sha256 = "sha256-3Y9W5ns+1wbVd14iePzgSBzE+LxnGMUDtUw3BccFt80=";
+      };
+
+      format = "pyproject";
+
+      propagatedBuildInputs = with pkgs.python3Packages; [ setuptools click numpy toolz jinja2 ramda artiqpkgs.migen artiqpkgs.misoc ];
+
+      checkInputs = with pkgs.python3Packages; [ pytestCheckHook pytest-timeout ];
+
+      # migen/misoc version checks are broken with pyproject for some reason
+      postPatch = ''
+        sed -i "1,4d" pyproject.toml
+        substituteInPlace pyproject.toml \
+          --replace '"migen@git+https://github.com/m-labs/migen",' ""
+        substituteInPlace pyproject.toml \
+          --replace '"misoc@git+https://github.com/m-labs/misoc.git",' ""
+        # pytest-flake8 is broken with recent flake8. Re-enable after fix.
+        substituteInPlace setup.cfg --replace '--flake8' ""
+      '';
+    };
+    binutils = { platform, target, zlib }: pkgs.stdenv.mkDerivation rec {
+      basename = "binutils";
+      version = "2.30";
+      name = "${basename}-${platform}-${version}";
+      src = pkgs.fetchurl {
+        url = "https://ftp.gnu.org/gnu/binutils/binutils-${version}.tar.bz2";
+        sha256 = "028cklfqaab24glva1ks2aqa1zxa6w6xmc8q34zs1sb7h22dxspg";
+      };
+      configureFlags =
+        [ "--enable-shared" "--enable-deterministic-archives" "--target=${target}"];
+      outputs = [ "out" "info" "man" ];
+      depsBuildBuild = [ pkgs.buildPackages.stdenv.cc ];
+      buildInputs = [ zlib ];
+      enableParallelBuilding = true;
+    };
+    binutils-arm = pkgs.callPackage binutils { platform = "arm"; target = "armv7-unknown-linux-gnueabihf"; };
+
+    # FSBL configuration supplied by Vivado 2020.1 for these boards:
+    fsblTargets = ["zc702" "zc706" "zed"];
+    sat_variants = [
+      # kasli-soc satellite variants
+      "satellite"
+      # zc706 satellite variants
+      "nist_clock_satellite" "nist_qc2_satellite" "acpki_nist_clock_satellite" "acpki_nist_qc2_satellite" 
+      "nist_clock_satellite_100mhz" "nist_qc2_satellite_100mhz" "acpki_nist_clock_satellite_100mhz" "acpki_nist_qc2_satellite_100mhz"
+    ];
+    board-package-set = { target, variant, json ? null }: let
+      szl = zynqpkgs."${target}-szl";
+      fsbl = zynqpkgs."${target}-fsbl";
+      fwtype = if builtins.elem variant sat_variants then "satman" else "runtime";
+
+      firmware = rustPlatform.buildRustPackage rec {
+        name = "firmware";
+        src = ./src;
+        cargoLock = { 
+          lockFile = src/Cargo.lock;
+          outputHashes = {
+              "tar-no-std-0.1.8" = "sha256-xm17108v4smXOqxdLvHl9CxTCJslmeogjm4Y87IXFuM=";
+              "nalgebra-0.32.6" = "sha256-L/YudkVOtfGYoNQKBD7LMk/sMYgRDzPDdpGL5rO7G2I=";
+            };
+        };
+
+        nativeBuildInputs = [
+          pkgs.gnumake
+          (pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
+          zynqpkgs.cargo-xbuild
+          llvmPackages_11.llvm
+          llvmPackages_11.clang-unwrapped
+        ];
+        buildPhase = ''
+          export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
+          export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
+          export CARGO_HOME=$(mktemp -d cargo-home.XXX)
+          export ZYNQ_RS=${zynq-rs}
+          make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
+        '';
+
+        installPhase = ''
+          mkdir -p $out $out/nix-support
+          cp ../build/${fwtype}.bin $out/${fwtype}.bin
+          cp ../build/firmware/armv7-none-eabihf/release/${fwtype} $out/${fwtype}.elf
+          echo file binary-dist $out/${fwtype}.bin >> $out/nix-support/hydra-build-products
+          echo file binary-dist $out/${fwtype}.elf >> $out/nix-support/hydra-build-products
+        '';
+
+        doCheck = false;
+        dontFixup = true;
+        auditable = false;
+      };
+      gateware = pkgs.runCommand "${target}-${variant}-gateware"
+        {
+          nativeBuildInputs = [ 
+            (pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
+            artiqpkgs.vivado
+          ];
+        }
+        ''
+          python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
+          mkdir -p $out $out/nix-support
+          cp build/top.bit $out
+          echo file binary-dist $out/top.bit >> $out/nix-support/hydra-build-products
+        '';
+
+      # SZL startup
+      jtag = pkgs.runCommand "${target}-${variant}-jtag" {}
+        ''
+          mkdir $out
+          ln -s ${szl}/szl.elf $out
+          ln -s ${firmware}/${fwtype}.bin $out
+          ln -s ${gateware}/top.bit $out
+        '';
+      sd = pkgs.runCommand "${target}-${variant}-sd"
+        {
+          buildInputs = [ zynqpkgs.mkbootimage ];
+        }
+        ''
+          # Do not use "long" paths in boot.bif, because embedded developers
+          # can't write software (mkbootimage will segfault).
+          bifdir=`mktemp -d`
+          cd $bifdir
+          ln -s ${szl}/szl.elf szl.elf
+          ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
+          ln -s ${gateware}/top.bit top.bit
+          cat > boot.bif << EOF
+          the_ROM_image:
+          {
+            [bootloader]szl.elf
+            top.bit
+            ${fwtype}.elf
+          }
+          EOF
+          mkdir $out $out/nix-support
+          mkbootimage boot.bif $out/boot.bin
+          echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
+        '';
+
+      # FSBL startup
+      fsbl-sd = pkgs.runCommand "${target}-${variant}-fsbl-sd"
+        {
+          buildInputs = [ zynqpkgs.mkbootimage ];
+        }
+        ''
+          bifdir=`mktemp -d`
+          cd $bifdir
+          ln -s ${fsbl}/fsbl.elf fsbl.elf
+          ln -s ${gateware}/top.bit top.bit
+          ln -s ${firmware}/${fwtype}.elf ${fwtype}.elf
+          cat > boot.bif << EOF
+          the_ROM_image:
+          {
+            [bootloader]fsbl.elf
+            top.bit
+            ${fwtype}.elf
+          }
+          EOF
+          mkdir $out $out/nix-support
+          mkbootimage boot.bif $out/boot.bin
+          echo file binary-dist $out/boot.bin >> $out/nix-support/hydra-build-products
+        '';
+    in {
+      "${target}-${variant}-firmware" = firmware;
+      "${target}-${variant}-gateware" = gateware;
+      "${target}-${variant}-jtag" = jtag;
+      "${target}-${variant}-sd" = sd;
+    } // (
+      if builtins.elem target fsblTargets
+      then {
+        "${target}-${variant}-fsbl-sd" = fsbl-sd;
+      }
+      else {}
+    );
+
+    gateware-sim = pkgs.stdenv.mkDerivation {
+      name = "gateware-sim";
+      
+      nativeBuildInputs = [ 
+        (pkgs.python3.withPackages(ps: [ artiqpkgs.migen migen-axi artiqpkgs.artiq ]))
+      ];
+
+      phases = [ "buildPhase" ];
+
+      buildPhase =
+        ''
+        python -m unittest discover ${self}/src/gateware -v
+        touch $out
+        '';
+    };
+
+    fmt-check = pkgs.stdenvNoCC.mkDerivation {
+      name = "fmt-check";
+
+      src = ./src;
+
+      nativeBuildInputs = [ rust pkgs.gnumake ];
+
+      phases = [ "unpackPhase" "buildPhase" ];
+
+      buildPhase =
+        ''
+        export ZYNQ_RS=${zynq-rs}
+        make manifests
+        cargo fmt -- --check
+        touch $out
+        '';
+    };
+
+    # for hitl-tests
+    zc706-nist_qc2 = (board-package-set { target = "zc706"; variant = "nist_qc2"; });
+    zc706-hitl-tests = pkgs.stdenv.mkDerivation {
+      name = "zc706-hitl-tests";
+
+      __networked = true;  # compatibility with old patched Nix
+      # breaks hydra, https://github.com/NixOS/hydra/issues/1216
+      #__impure = true;     # Nix 2.8+
+
+      buildInputs = [
+        pkgs.netcat pkgs.openssh pkgs.rsync artiqpkgs.artiq artiq-netboot zynqpkgs.zc706-szl
+      ];
+      phases = [ "buildPhase" ];
+
+      buildPhase =
+        ''
+        export NIX_SSHOPTS="-F /dev/null -o StrictHostKeyChecking=no -o UserKnownHostsFile=/dev/null -o LogLevel=ERROR -i /opt/hydra_id_ed25519"
+        LOCKCTL=$(mktemp -d)
+        mkfifo $LOCKCTL/lockctl
+
+        cat $LOCKCTL/lockctl | ${pkgs.openssh}/bin/ssh \
+        $NIX_SSHOPTS \
+        rpi-4 \
+        'mkdir -p /tmp/board_lock && flock /tmp/board_lock/zc706-1 -c "echo Ok; cat"' \
+        | (
+          # End remote flock via FIFO
+          atexit_unlock() {
+            echo > $LOCKCTL/lockctl
+          }
+          trap atexit_unlock EXIT
+
+          # Read "Ok" line when remote successfully locked
+          read LOCK_OK
+
+          echo Power cycling board...
+          (echo b; sleep 5; echo B; sleep 5) | nc -N -w6 192.168.1.31 3131
+          echo Power cycle done.
+
+          export USER=hydra
+          export OPENOCD_ZYNQ=${zynq-rs}/openocd
+          export SZL=${zynqpkgs.szl}
+          bash ${self}/remote_run.sh -h rpi-4 -o "$NIX_SSHOPTS" -d ${zc706-nist_qc2.zc706-nist_qc2-jtag}
+
+          echo Waiting for the firmware to boot...
+          sleep 15
+
+          echo Running test kernel...
+          artiq_run --device-db ${self}/examples/device_db.py ${self}/examples/mandelbrot.py
+
+          echo Running ARTIQ unit tests...
+          export ARTIQ_ROOT=${self}/examples
+          export ARTIQ_LOW_LATENCY=1
+          python -m unittest discover artiq.test.coredevice -v
+
+          touch $out
+
+          echo Completed
+
+          (echo b; sleep 5) | nc -N -w6 192.168.1.31 3131
+          echo Board powered off
+        )
+        '';
+    };
+  in rec {
+    packages.x86_64-linux =
+      {
+        inherit fastnumbers artiq-netboot ramda migen-axi binutils-arm;
+      } //
+      (board-package-set { target = "zc706"; variant = "nist_clock"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_clock_master"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_clock_master_100mhz"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_clock_satellite"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_clock_satellite_100mhz"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_qc2"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_qc2_master"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_qc2_master_100mhz"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_qc2_satellite"; }) //
+      (board-package-set { target = "zc706"; variant = "nist_qc2_satellite_100mhz"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_clock"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_clock_master"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_clock_master_100mhz"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_clock_satellite"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_clock_satellite_100mhz"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_qc2"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_qc2_master"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_qc2_master_100mhz"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_qc2_satellite"; }) //
+      (board-package-set { target = "zc706"; variant = "acpki_nist_qc2_satellite_100mhz"; }) //
+      (board-package-set { target = "kasli_soc"; variant = "demo"; json = ./demo.json; }) //
+      (board-package-set { target = "kasli_soc"; variant = "master"; json = ./kasli-soc-master.json; }) //
+      (board-package-set { target = "kasli_soc"; variant = "satellite"; json = ./kasli-soc-satellite.json; }) //
+      (board-package-set { target = "ebaz4205"; variant = "base"; });
+
+    hydraJobs = packages.x86_64-linux // { inherit zc706-hitl-tests; inherit gateware-sim; inherit fmt-check; };
+
+    devShell.x86_64-linux = pkgs.mkShell {
+      name = "artiq-zynq-dev-shell";
+      buildInputs = with pkgs; [
+        rust
+        llvmPackages_11.llvm
+        llvmPackages_11.clang-unwrapped
+        gnumake
+        cacert
+        zynqpkgs.cargo-xbuild
+        zynqpkgs.mkbootimage
+        openocd  
+        openssh rsync
+        (python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq artiq-netboot ps.jsonschema ps.pyftdi ])))
+        artiqpkgs.artiq
+        artiqpkgs.vivado
+        binutils-arm
+        pre-commit
+      ];
+      XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
+      CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
+      ZYNQ_RS = "${zynq-rs}";
+      OPENOCD_ZYNQ = "${zynq-rs}/openocd";
+      SZL = "${zynqpkgs.szl}";
+    };
+
+    makeArtiqZynqPackage = board-package-set;
+
+  };
+}

fsbl.nix

@@ -1,37 +0,0 @@
-{ pkgs, board ? "zc706" }:
-let
-  gnutoolchain = import ./gnutoolchain.nix { inherit pkgs; };
-in
-pkgs.stdenv.mkDerivation {
-  name = "${board}-fsbl";
-  src = pkgs.fetchFromGitHub {
-    owner = "Xilinx";
-    repo = "embeddedsw";
-    rev = "65c849ed46c88c67457e1fc742744f96db968ff1";
-    sha256 = "1rvl06ha40dzd6s9aa4sylmksh4xb9dqaxq462lffv1fdk342pda";
-  };
-  patches = [ ./fsbl.patch ];
-  nativeBuildInputs = [
-    pkgs.gnumake
-    gnutoolchain.binutils
-    gnutoolchain.gcc
-  ];
-  patchPhase =
-    ''
-    patch -p1 -i ${./fsbl.patch}
-    patchShebangs lib/sw_apps/zynq_fsbl/misc/copy_bsp.sh
-    echo 'SEARCH_DIR("${gnutoolchain.newlib}/arm-none-eabi/lib");' >> lib/sw_apps/zynq_fsbl/src/lscript.ld
-    '';
-  buildPhase =
-    ''
-    cd lib/sw_apps/zynq_fsbl/src
-    make BOARD=${board} "CFLAGS=-DFSBL_DEBUG_INFO -g"
-    '';
-  installPhase = 
-    ''
-    mkdir $out
-    cp fsbl.elf $out
-    '';
-  doCheck = false;
-  dontFixup = true;
-}

fsbl.patch

@@ -1,31 +0,0 @@
-diff --git a/lib/sw_apps/zynq_fsbl/src/Makefile b/lib/sw_apps/zynq_fsbl/src/Makefile
-index 0e3ccdf1c5..a5b02f386e 100644
---- a/lib/sw_apps/zynq_fsbl/src/Makefile
-+++ b/lib/sw_apps/zynq_fsbl/src/Makefile
-@@ -71,11 +71,14 @@ endif
- all: $(EXEC)
- 
- $(EXEC): $(LIBS) $(OBJS) $(INCLUDES)
--	cp $(BSP_DIR)/$(BOARD)/ps7_init.* .
- 	$(LINKER) $(LD1FLAGS)  -o $@ $(OBJS) $(LDFLAGS)
- 	rm -rf $(OBJS)
--	
--	
-+
-+.PHONY: ps7_init
-+
-+ps7_init:
-+	cp $(BSP_DIR)/$(BOARD)/ps7_init.* .
-+
- $(LIBS): 
- 	echo "Copying BSP files"
- 	$(BSP_DIR)/copy_bsp.sh $(BOARD) $(CC)
-@@ -86,7 +89,7 @@ $(LIBS):
-         make -C $(BSP_DIR) -k all "CC=armcc" "AR=armar" "C_FLAGS= -O2 -c" "EC_FLAGS=--debug --wchar32"; \
- 	fi;
- 
--%.o:%.c
-+%.o:%.c ps7_init
- 	$(CC) $(CC_FLAGS) $(CFLAGS) $(ECFLAGS) -c $< -o $@ $(INCLUDEPATH)
- 
- %.o:%.S

gnutoolchain.nix

@@ -1,134 +0,0 @@
-{ pkgs ? import <nixpkgs> }:
-let 
-
-platform = "arm-none-eabi";
-
-binutils-pkg = { stdenv, buildPackages
-, fetchurl, zlib
-, extraConfigureFlags ? []
-}:
-
-stdenv.mkDerivation rec {
-  basename = "binutils";
-  version = "2.30";
-  name = "${basename}-${platform}-${version}";
-  src = fetchurl {
-    url = "https://ftp.gnu.org/gnu/binutils/binutils-${version}.tar.bz2";
-    sha256 = "028cklfqaab24glva1ks2aqa1zxa6w6xmc8q34zs1sb7h22dxspg";
-  };
-  configureFlags = [
-    "--enable-deterministic-archives"
-    "--target=${platform}"
-    "--with-cpu=cortex-a9"
-    "--with-fpu=vfpv3"
-    "--with-float=hard"
-    "--with-mode=thumb"
-  ] ++ extraConfigureFlags;
-  outputs = [ "out" "info" "man" ];
-  depsBuildBuild = [ buildPackages.stdenv.cc ];
-  buildInputs = [ zlib ];
-  enableParallelBuilding = true;
-  meta = {
-    description = "Tools for manipulating binaries (linker, assembler, etc.)";
-    longDescription = ''
-      The GNU Binutils are a collection of binary tools.  The main
-      ones are `ld' (the GNU linker) and `as' (the GNU assembler).
-      They also include the BFD (Binary File Descriptor) library,
-      `gprof', `nm', `strip', etc.
-    '';
-    homepage = http://www.gnu.org/software/binutils/;
-    license = stdenv.lib.licenses.gpl3Plus;
-    /* Give binutils a lower priority than gcc-wrapper to prevent a
-       collision due to the ld/as wrappers/symlinks in the latter. */
-    priority = "10";
-  };
-};
-
-
-gcc-pkg = { stdenv, buildPackages
-, fetchurl, gmp, mpfr, libmpc, platform-binutils
-, extraConfigureFlags ? []
-}:
-
-stdenv.mkDerivation rec {
-  basename = "gcc";
-  version = "9.1.0";
-  name = "${basename}-${platform}-${version}";
-  src = fetchurl {
-    url = "https://ftp.gnu.org/gnu/gcc/gcc-${version}/gcc-${version}.tar.xz";
-    sha256 = "1817nc2bqdc251k0lpc51cimna7v68xjrnvqzvc50q3ax4s6i9kr";
-  };
-  preConfigure =
-    ''
-    mkdir build
-    cd build
-    '';
-  configureScript = "../configure";
-  configureFlags =
-    [ "--target=${platform}"
-      "--with-arch=armv7-a"
-      "--with-tune=cortex-a9"
-      "--with-fpu=vfpv3"
-      "--with-float=hard"
-      "--disable-libssp"
-      "--enable-languages=c"
-      "--with-as=${platform-binutils}/bin/${platform}-as"
-      "--with-ld=${platform-binutils}/bin/${platform}-ld" ] ++ extraConfigureFlags;
-  outputs = [ "out" "info" "man" ];
-  hardeningDisable = [ "format" "pie" ];
-  propagatedBuildInputs = [ gmp mpfr libmpc platform-binutils ];
-  enableParallelBuilding = true;
-  dontFixup = true;
-};
-
-
-newlib-pkg = { stdenv, fetchurl, buildPackages, platform-binutils, platform-gcc }:
-
-stdenv.mkDerivation rec {
-  pname = "newlib";
-  version = "3.1.0";
-  src = fetchurl {
-    url = "ftp://sourceware.org/pub/newlib/newlib-${version}.tar.gz";
-    sha256 = "0ahh3n079zjp7d9wynggwrnrs27440aac04340chf1p9476a2kzv";
-  };
-
-  nativeBuildInputs = [ platform-binutils platform-gcc ];
-
-  configureFlags = [
-    "--target=${platform}"
-
-    "--with-cpu=cortex-a9"
-    "--with-fpu=vfpv3"
-    "--with-float=hard"
-    "--with-mode=thumb"
-    "--enable-interwork"
-    "--disable-multilib"
-
-    "--disable-newlib-supplied-syscalls"
-    "--with-gnu-ld"
-    "--with-gnu-as"
-    "--disable-newlib-io-float"
-    "--disable-werror"
-  ];
-  dontFixup = true;
-};
-
-
-in rec {
-  binutils-bootstrap = pkgs.callPackage binutils-pkg { };
-  gcc-bootstrap = pkgs.callPackage gcc-pkg {
-    platform-binutils = binutils-bootstrap;
-    extraConfigureFlags = [ "--disable-libgcc" ];
-  };
-  newlib = pkgs.callPackage newlib-pkg {
-    platform-binutils = binutils-bootstrap;
-    platform-gcc = gcc-bootstrap;
-  };
-  binutils = pkgs.callPackage binutils-pkg {
-    extraConfigureFlags = [ "--with-lib-path=${newlib}/arm-none-eabi/lib" ];
-  };
-  gcc = pkgs.callPackage gcc-pkg {
-    platform-binutils = binutils;
-    extraConfigureFlags = [ "--enable-newlib" "--with-headers=${newlib}/arm-none-eabi/include" ];
-  };
-}

kasli-soc-master.json

@@ -0,0 +1,60 @@
+{
+    "target": "kasli_soc",
+    "variant": "master",
+    "hw_rev": "v1.0",
+    "base": "master",
+    "peripherals": [
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}

kasli-soc-satellite.json

@@ -0,0 +1,60 @@
+{
+    "target": "kasli_soc",
+    "variant": "satellite",
+    "hw_rev": "v1.0",
+    "base": "satellite",
+    "peripherals": [
+        {
+            "type": "grabber",
+            "ports": [0]
+        },
+        {
+            "type": "dio",
+            "ports": [1],
+            "bank_direction_low": "input",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "dio",
+            "ports": [2],
+            "bank_direction_low": "output",
+            "bank_direction_high": "output"
+        },
+        {
+            "type": "urukul",
+            "dds": "ad9910",
+            "ports": [3, 4],
+            "clk_sel": 2
+        },
+        {
+            "type": "zotino",
+            "ports": [5]
+        },
+        {
+            "type": "sampler",
+            "ports": [6, 7]
+        },
+        {
+            "type": "mirny",
+            "ports": [8],
+            "clk_sel": 1,
+            "refclk": 125e6
+        },
+        {
+            "type": "fastino",
+            "ports": [9]
+        },
+        {
+            "type": "dio",
+            "ports": [10],
+            "bank_direction_low": "input",
+            "bank_direction_high": "input"
+        },
+        {
+            "type": "dio",
+            "ports": [11],
+            "bank_direction_low": "output",
+            "bank_direction_high": "input"
+        }
+    ]
+}

local_run.sh

@@ -2,20 +2,60 @@
 
 set -e
 
-impure=0
+if [ -z "$OPENOCD_ZYNQ" ]; then
+    echo "OPENOCD_ZYNQ environment variable must be set"
+    exit 1
+fi
+if [ -z "$SZL" ]; then
+    echo "SZL environment variable must be set"
+    exit 1
+fi
 
-while getopts "h:i" opt; do
+impure=0
+load_bitstream=1
+board_type="kasli_soc"
+fw_type="runtime"
+
+while getopts "ilb:t:f:" opt; do
     case "$opt" in
-    \?) exit 0
+    \?) exit 1
         ;;
     i)  impure=1
         ;;
+    l)  load_bitstream=0
+        ;;
+    b)  board_host=$OPTARG
+        ;;
+    t)  board_type=$OPTARG
+        ;;
+    f)  fw_type=$OPTARG
+        ;;
     esac
 done
 
-cd openocd
-if [ $impure -eq 1 ]; then
-    openocd -f zc706.cfg -c 'pld load 0 ../build/gateware/top.bit; load_image ../build/firmware/armv7-none-eabihf/release/szl; resume 0; exit'
-else
-    openocd -f zc706.cfg -c 'pld load 0 ../result/top.bit; load_image ../result/szl.elf; resume 0; exit'
+if [ -z "$board_host" ]; then
+    case $board_type in
+    kasli_soc) board_host="192.168.1.56";;
+    zc706) board_host="192.168.1.52";;
+    *) echo "Unknown board type"; exit 1;;
+    esac
+fi
+
+load_bitstream_cmd=""
+
+build_dir=`pwd`/build
+result_dir=`pwd`/result
+cd $OPENOCD_ZYNQ
+openocd -f $board_type.cfg -c "load_image $SZL/szl-$board_type.elf; resume 0; exit"
+sleep 5
+if [ $impure -eq 1 ]; then
+    if [ $load_bitstream -eq 1 ]; then
+        load_bitstream_cmd="-g $build_dir/gateware/top.bit"
+    fi
+    artiq_netboot $load_bitstream_cmd -f $build_dir/$fw_type.bin -b $board_host
+else
+    if [ $load_bitstream -eq 1 ]; then
+        load_bitstream_cmd="-g $result_dir/top.bit"
+    fi
+    artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
 fi

mkbootimage.nix

@@ -1,24 +0,0 @@
-{ pkgs }:
-
-pkgs.stdenv.mkDerivation {
-  pname = "mkbootimage";
-  version = "2.2";
-
-  src = pkgs.fetchFromGitHub {
-    owner = "antmicro";
-    repo = "zynq-mkbootimage";
-    rev = "4ee42d782a9ba65725ed165a4916853224a8edf7";
-    sha256 = "1k1mbsngqadqihzjgvwvsrkvryxy5ladpxd9yh9iqn2s7fxqwqa9";
-  };
-
-  propagatedBuildInputs = [ pkgs.libelf pkgs.pcre ];
-  patchPhase =
-    ''
-    substituteInPlace Makefile --replace "git rev-parse --short HEAD" "echo nix"
-    '';
-  installPhase =
-    ''
-    mkdir -p $out/bin
-    cp mkbootimage $out/bin
-    '';
-}

openocd/digilent_jtag_smt2_nc.cfg

@@ -1,18 +0,0 @@
-#
-# Digilent JTAG-SMT2-NC
-#
-# http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/
-# https://reference.digilentinc.com/_media/jtag_smt2nc/jtag-smt2-nc_rm.pdf
-#
-# Based on reference sheet (above) and Xilinx KCU105 schematics
-# https://www.xilinx.com/products/boards-and-kits/kcu105.html#documentation
-#
-# Note that the digilent_jtag_smt2 layout does not work and hangs while
-# the ftdi_device_desc from digilent_hs2 is wrong.
-
-interface ftdi
-ftdi_device_desc "Digilent USB Device"
-ftdi_vid_pid 0x0403 0x6014
-ftdi_channel 0
-ftdi_layout_init 0x00e8 0x60eb
-ftdi_layout_signal nSRST -data 0x2000

openocd/ps7_init.tcl

@@ -1,771 +0,0 @@
-proc ps7_pll_init_data_3_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000110 0x003FFFF0 0x000FA220
-    mask_write 0XF8000100 0x0007F000 0x00028000
-    mask_write 0XF8000100 0x00000010 0x00000010
-    mask_write 0XF8000100 0x00000001 0x00000001
-    mask_write 0XF8000100 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000001
-    mask_write 0XF8000100 0x00000010 0x00000000
-    mask_write 0XF8000120 0x1F003F30 0x1F000200
-    mask_write 0XF8000114 0x003FFFF0 0x0012C220
-    mask_write 0XF8000104 0x0007F000 0x00020000
-    mask_write 0XF8000104 0x00000010 0x00000010
-    mask_write 0XF8000104 0x00000001 0x00000001
-    mask_write 0XF8000104 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000002
-    mask_write 0XF8000104 0x00000010 0x00000000
-    mask_write 0XF8000124 0xFFF00003 0x0C200003
-    mask_write 0XF8000118 0x003FFFF0 0x001452C0
-    mask_write 0XF8000108 0x0007F000 0x0001E000
-    mask_write 0XF8000108 0x00000010 0x00000010
-    mask_write 0XF8000108 0x00000001 0x00000001
-    mask_write 0XF8000108 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000004
-    mask_write 0XF8000108 0x00000010 0x00000000
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_3_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000128 0x03F03F01 0x00700F01
-    mask_write 0XF8000138 0x00000011 0x00000001
-    mask_write 0XF8000140 0x03F03F71 0x00100801
-    mask_write 0XF800014C 0x00003F31 0x00000501
-    mask_write 0XF8000150 0x00003F33 0x00001401
-    mask_write 0XF8000154 0x00003F33 0x00001402
-    mask_write 0XF8000168 0x00003F31 0x00000501
-    mask_write 0XF8000170 0x03F03F30 0x00200500
-    mask_write 0XF80001C4 0x00000001 0x00000001
-    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_3_0 {} {
-    mask_write 0XF8006000 0x0001FFFF 0x00000080
-    mask_write 0XF8006004 0x0007FFFF 0x00001081
-    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
-    mask_write 0XF800600C 0x03FFFFFF 0x02001001
-    mask_write 0XF8006010 0x03FFFFFF 0x00014001
-    mask_write 0XF8006014 0x001FFFFF 0x0004159B
-    mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
-    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
-    mask_write 0XF8006020 0x7FDFFFFC 0x270872D0
-    mask_write 0XF8006024 0x0FFFFFC3 0x00000000
-    mask_write 0XF8006028 0x00003FFF 0x00002007
-    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
-    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
-    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
-    mask_write 0XF8006038 0x00000003 0x00000000
-    mask_write 0XF800603C 0x000FFFFF 0x00000777
-    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
-    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
-    mask_write 0XF8006048 0x0003F03F 0x0003C008
-    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
-    mask_write 0XF8006058 0x00010000 0x00000000
-    mask_write 0XF800605C 0x0000FFFF 0x00005003
-    mask_write 0XF8006060 0x000017FF 0x0000003E
-    mask_write 0XF8006064 0x00021FE0 0x00020000
-    mask_write 0XF8006068 0x03FFFFFF 0x00284141
-    mask_write 0XF800606C 0x0000FFFF 0x00001610
-    mask_write 0XF8006078 0x03FFFFFF 0x00466111
-    mask_write 0XF800607C 0x000FFFFF 0x00032222
-    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
-    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
-    mask_write 0XF80060AC 0x000001FF 0x000001FE
-    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
-    mask_write 0XF80060B4 0x00000200 0x00000200
-    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
-    mask_write 0XF80060C4 0x00000003 0x00000000
-    mask_write 0XF80060C8 0x000000FF 0x00000000
-    mask_write 0XF80060DC 0x00000001 0x00000000
-    mask_write 0XF80060F0 0x0000FFFF 0x00000000
-    mask_write 0XF80060F4 0x0000000F 0x00000008
-    mask_write 0XF8006114 0x000000FF 0x00000000
-    mask_write 0XF8006118 0x7FFFFFCF 0x40000001
-    mask_write 0XF800611C 0x7FFFFFCF 0x40000001
-    mask_write 0XF8006120 0x7FFFFFCF 0x40000001
-    mask_write 0XF8006124 0x7FFFFFCF 0x40000001
-    mask_write 0XF800612C 0x000FFFFF 0x00033C03
-    mask_write 0XF8006130 0x000FFFFF 0x00034003
-    mask_write 0XF8006134 0x000FFFFF 0x0002F400
-    mask_write 0XF8006138 0x000FFFFF 0x00030400
-    mask_write 0XF8006140 0x000FFFFF 0x00000035
-    mask_write 0XF8006144 0x000FFFFF 0x00000035
-    mask_write 0XF8006148 0x000FFFFF 0x00000035
-    mask_write 0XF800614C 0x000FFFFF 0x00000035
-    mask_write 0XF8006154 0x000FFFFF 0x00000083
-    mask_write 0XF8006158 0x000FFFFF 0x00000083
-    mask_write 0XF800615C 0x000FFFFF 0x00000080
-    mask_write 0XF8006160 0x000FFFFF 0x00000080
-    mask_write 0XF8006168 0x001FFFFF 0x00000124
-    mask_write 0XF800616C 0x001FFFFF 0x00000125
-    mask_write 0XF8006170 0x001FFFFF 0x00000112
-    mask_write 0XF8006174 0x001FFFFF 0x00000116
-    mask_write 0XF800617C 0x000FFFFF 0x000000C3
-    mask_write 0XF8006180 0x000FFFFF 0x000000C3
-    mask_write 0XF8006184 0x000FFFFF 0x000000C0
-    mask_write 0XF8006188 0x000FFFFF 0x000000C0
-    mask_write 0XF8006190 0x6FFFFEFE 0x00040080
-    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
-    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
-    mask_write 0XF8006208 0x000703FF 0x000003FF
-    mask_write 0XF800620C 0x000703FF 0x000003FF
-    mask_write 0XF8006210 0x000703FF 0x000003FF
-    mask_write 0XF8006214 0x000703FF 0x000003FF
-    mask_write 0XF8006218 0x000F03FF 0x000003FF
-    mask_write 0XF800621C 0x000F03FF 0x000003FF
-    mask_write 0XF8006220 0x000F03FF 0x000003FF
-    mask_write 0XF8006224 0x000F03FF 0x000003FF
-    mask_write 0XF80062A8 0x00000FF5 0x00000000
-    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
-    mask_write 0XF80062B0 0x003FFFFF 0x00005125
-    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
-    mask_poll 0XF8000B74 0x00002000
-    mask_write 0XF8006000 0x0001FFFF 0x00000081
-    mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_3_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000B40 0x00000FFF 0x00000600
-    mask_write 0XF8000B44 0x00000FFF 0x00000600
-    mask_write 0XF8000B48 0x00000FFF 0x00000672
-    mask_write 0XF8000B4C 0x00000FFF 0x00000672
-    mask_write 0XF8000B50 0x00000FFF 0x00000674
-    mask_write 0XF8000B54 0x00000FFF 0x00000674
-    mask_write 0XF8000B58 0x00000FFF 0x00000600
-    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
-    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B6C 0x00007FFF 0x00000209
-    mask_write 0XF8000B70 0x00000001 0x00000001
-    mask_write 0XF8000B70 0x00000021 0x00000020
-    mask_write 0XF8000B70 0x07FEFFFF 0x00000823
-    mask_write 0XF8000700 0x00003FFF 0x00000600
-    mask_write 0XF8000704 0x00003FFF 0x00000702
-    mask_write 0XF8000708 0x00003FFF 0x00000702
-    mask_write 0XF800070C 0x00003FFF 0x00000702
-    mask_write 0XF8000710 0x00003FFF 0x00000702
-    mask_write 0XF8000714 0x00003FFF 0x00000702
-    mask_write 0XF8000718 0x00003FFF 0x00000702
-    mask_write 0XF800071C 0x00003FFF 0x00000600
-    mask_write 0XF8000720 0x00003FFF 0x00000700
-    mask_write 0XF8000724 0x00003FFF 0x00000600
-    mask_write 0XF8000728 0x00003FFF 0x00000600
-    mask_write 0XF800072C 0x00003FFF 0x00000600
-    mask_write 0XF8000730 0x00003FFF 0x00000600
-    mask_write 0XF8000734 0x00003FFF 0x00000600
-    mask_write 0XF8000738 0x00003FFF 0x00000600
-    mask_write 0XF800073C 0x00003FFF 0x00000600
-    mask_write 0XF8000740 0x00003FFF 0x00000302
-    mask_write 0XF8000744 0x00003FFF 0x00000302
-    mask_write 0XF8000748 0x00003FFF 0x00000302
-    mask_write 0XF800074C 0x00003FFF 0x00000302
-    mask_write 0XF8000750 0x00003FFF 0x00000302
-    mask_write 0XF8000754 0x00003FFF 0x00000302
-    mask_write 0XF8000758 0x00003FFF 0x00000303
-    mask_write 0XF800075C 0x00003FFF 0x00000303
-    mask_write 0XF8000760 0x00003FFF 0x00000303
-    mask_write 0XF8000764 0x00003FFF 0x00000303
-    mask_write 0XF8000768 0x00003FFF 0x00000303
-    mask_write 0XF800076C 0x00003FFF 0x00000303
-    mask_write 0XF8000770 0x00003FFF 0x00000304
-    mask_write 0XF8000774 0x00003FFF 0x00000305
-    mask_write 0XF8000778 0x00003FFF 0x00000304
-    mask_write 0XF800077C 0x00003FFF 0x00000305
-    mask_write 0XF8000780 0x00003FFF 0x00000304
-    mask_write 0XF8000784 0x00003FFF 0x00000304
-    mask_write 0XF8000788 0x00003FFF 0x00000304
-    mask_write 0XF800078C 0x00003FFF 0x00000304
-    mask_write 0XF8000790 0x00003FFF 0x00000305
-    mask_write 0XF8000794 0x00003FFF 0x00000304
-    mask_write 0XF8000798 0x00003FFF 0x00000304
-    mask_write 0XF800079C 0x00003FFF 0x00000304
-    mask_write 0XF80007A0 0x00003FFF 0x00000380
-    mask_write 0XF80007A4 0x00003FFF 0x00000380
-    mask_write 0XF80007A8 0x00003FFF 0x00000380
-    mask_write 0XF80007AC 0x00003FFF 0x00000380
-    mask_write 0XF80007B0 0x00003FFF 0x00000380
-    mask_write 0XF80007B4 0x00003FFF 0x00000380
-    mask_write 0XF80007B8 0x00003F01 0x00000201
-    mask_write 0XF80007BC 0x00003F01 0x00000201
-    mask_write 0XF80007C0 0x00003FFF 0x000002E0
-    mask_write 0XF80007C4 0x00003FFF 0x000002E1
-    mask_write 0XF80007C8 0x00003FFF 0x00000200
-    mask_write 0XF80007CC 0x00003FFF 0x00000200
-    mask_write 0XF80007D0 0x00003FFF 0x00000280
-    mask_write 0XF80007D4 0x00003FFF 0x00000280
-    mask_write 0XF8000830 0x003F003F 0x002F002E
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_3_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000B48 0x00000180 0x00000180
-    mask_write 0XF8000B4C 0x00000180 0x00000180
-    mask_write 0XF8000B50 0x00000180 0x00000180
-    mask_write 0XF8000B54 0x00000180 0x00000180
-    mwr -force 0XF8000004 0x0000767B
-    mask_write 0XE0001034 0x000000FF 0x00000006
-    mask_write 0XE0001018 0x0000FFFF 0x0000003E
-    mask_write 0XE0001000 0x000001FF 0x00000017
-    mask_write 0XE0001004 0x000003FF 0x00000020
-    mask_write 0XE000D000 0x00080000 0x00080000
-    mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_3_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000900 0x0000000F 0x0000000F
-    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_3_0 {} {
-    mwr -force 0XF8898FB0 0xC5ACCE55
-    mwr -force 0XF8899FB0 0xC5ACCE55
-    mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_2_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000110 0x003FFFF0 0x000FA220
-    mask_write 0XF8000100 0x0007F000 0x00028000
-    mask_write 0XF8000100 0x00000010 0x00000010
-    mask_write 0XF8000100 0x00000001 0x00000001
-    mask_write 0XF8000100 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000001
-    mask_write 0XF8000100 0x00000010 0x00000000
-    mask_write 0XF8000120 0x1F003F30 0x1F000200
-    mask_write 0XF8000114 0x003FFFF0 0x0012C220
-    mask_write 0XF8000104 0x0007F000 0x00020000
-    mask_write 0XF8000104 0x00000010 0x00000010
-    mask_write 0XF8000104 0x00000001 0x00000001
-    mask_write 0XF8000104 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000002
-    mask_write 0XF8000104 0x00000010 0x00000000
-    mask_write 0XF8000124 0xFFF00003 0x0C200003
-    mask_write 0XF8000118 0x003FFFF0 0x001452C0
-    mask_write 0XF8000108 0x0007F000 0x0001E000
-    mask_write 0XF8000108 0x00000010 0x00000010
-    mask_write 0XF8000108 0x00000001 0x00000001
-    mask_write 0XF8000108 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000004
-    mask_write 0XF8000108 0x00000010 0x00000000
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_2_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000128 0x03F03F01 0x00700F01
-    mask_write 0XF8000138 0x00000011 0x00000001
-    mask_write 0XF8000140 0x03F03F71 0x00100801
-    mask_write 0XF800014C 0x00003F31 0x00000501
-    mask_write 0XF8000150 0x00003F33 0x00001401
-    mask_write 0XF8000154 0x00003F33 0x00001402
-    mask_write 0XF8000168 0x00003F31 0x00000501
-    mask_write 0XF8000170 0x03F03F30 0x00200500
-    mask_write 0XF80001C4 0x00000001 0x00000001
-    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_2_0 {} {
-    mask_write 0XF8006000 0x0001FFFF 0x00000080
-    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
-    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
-    mask_write 0XF800600C 0x03FFFFFF 0x02001001
-    mask_write 0XF8006010 0x03FFFFFF 0x00014001
-    mask_write 0XF8006014 0x001FFFFF 0x0004159B
-    mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
-    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
-    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
-    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
-    mask_write 0XF8006028 0x00003FFF 0x00002007
-    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
-    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
-    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
-    mask_write 0XF8006038 0x00001FC3 0x00000000
-    mask_write 0XF800603C 0x000FFFFF 0x00000777
-    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
-    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
-    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
-    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
-    mask_write 0XF8006058 0x0001FFFF 0x00000101
-    mask_write 0XF800605C 0x0000FFFF 0x00005003
-    mask_write 0XF8006060 0x000017FF 0x0000003E
-    mask_write 0XF8006064 0x00021FE0 0x00020000
-    mask_write 0XF8006068 0x03FFFFFF 0x00284141
-    mask_write 0XF800606C 0x0000FFFF 0x00001610
-    mask_write 0XF8006078 0x03FFFFFF 0x00466111
-    mask_write 0XF800607C 0x000FFFFF 0x00032222
-    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
-    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
-    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
-    mask_write 0XF80060AC 0x000001FF 0x000001FE
-    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
-    mask_write 0XF80060B4 0x000007FF 0x00000200
-    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
-    mask_write 0XF80060C4 0x00000003 0x00000000
-    mask_write 0XF80060C8 0x000000FF 0x00000000
-    mask_write 0XF80060DC 0x00000001 0x00000000
-    mask_write 0XF80060F0 0x0000FFFF 0x00000000
-    mask_write 0XF80060F4 0x0000000F 0x00000008
-    mask_write 0XF8006114 0x000000FF 0x00000000
-    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
-    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
-    mask_write 0XF800612C 0x000FFFFF 0x00033C03
-    mask_write 0XF8006130 0x000FFFFF 0x00034003
-    mask_write 0XF8006134 0x000FFFFF 0x0002F400
-    mask_write 0XF8006138 0x000FFFFF 0x00030400
-    mask_write 0XF8006140 0x000FFFFF 0x00000035
-    mask_write 0XF8006144 0x000FFFFF 0x00000035
-    mask_write 0XF8006148 0x000FFFFF 0x00000035
-    mask_write 0XF800614C 0x000FFFFF 0x00000035
-    mask_write 0XF8006154 0x000FFFFF 0x00000083
-    mask_write 0XF8006158 0x000FFFFF 0x00000083
-    mask_write 0XF800615C 0x000FFFFF 0x00000080
-    mask_write 0XF8006160 0x000FFFFF 0x00000080
-    mask_write 0XF8006168 0x001FFFFF 0x00000124
-    mask_write 0XF800616C 0x001FFFFF 0x00000125
-    mask_write 0XF8006170 0x001FFFFF 0x00000112
-    mask_write 0XF8006174 0x001FFFFF 0x00000116
-    mask_write 0XF800617C 0x000FFFFF 0x000000C3
-    mask_write 0XF8006180 0x000FFFFF 0x000000C3
-    mask_write 0XF8006184 0x000FFFFF 0x000000C0
-    mask_write 0XF8006188 0x000FFFFF 0x000000C0
-    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
-    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
-    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
-    mask_write 0XF8006208 0x000F03FF 0x000803FF
-    mask_write 0XF800620C 0x000F03FF 0x000803FF
-    mask_write 0XF8006210 0x000F03FF 0x000803FF
-    mask_write 0XF8006214 0x000F03FF 0x000803FF
-    mask_write 0XF8006218 0x000F03FF 0x000003FF
-    mask_write 0XF800621C 0x000F03FF 0x000003FF
-    mask_write 0XF8006220 0x000F03FF 0x000003FF
-    mask_write 0XF8006224 0x000F03FF 0x000003FF
-    mask_write 0XF80062A8 0x00000FF7 0x00000000
-    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
-    mask_write 0XF80062B0 0x003FFFFF 0x00005125
-    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
-    mask_poll 0XF8000B74 0x00002000
-    mask_write 0XF8006000 0x0001FFFF 0x00000081
-    mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_2_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000B40 0x00000FFF 0x00000600
-    mask_write 0XF8000B44 0x00000FFF 0x00000600
-    mask_write 0XF8000B48 0x00000FFF 0x00000672
-    mask_write 0XF8000B4C 0x00000FFF 0x00000672
-    mask_write 0XF8000B50 0x00000FFF 0x00000674
-    mask_write 0XF8000B54 0x00000FFF 0x00000674
-    mask_write 0XF8000B58 0x00000FFF 0x00000600
-    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
-    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B6C 0x00007FFF 0x00000209
-    mask_write 0XF8000B70 0x00000021 0x00000021
-    mask_write 0XF8000B70 0x00000021 0x00000020
-    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
-    mask_write 0XF8000700 0x00003FFF 0x00000600
-    mask_write 0XF8000704 0x00003FFF 0x00000702
-    mask_write 0XF8000708 0x00003FFF 0x00000702
-    mask_write 0XF800070C 0x00003FFF 0x00000702
-    mask_write 0XF8000710 0x00003FFF 0x00000702
-    mask_write 0XF8000714 0x00003FFF 0x00000702
-    mask_write 0XF8000718 0x00003FFF 0x00000702
-    mask_write 0XF800071C 0x00003FFF 0x00000600
-    mask_write 0XF8000720 0x00003FFF 0x00000700
-    mask_write 0XF8000724 0x00003FFF 0x00000600
-    mask_write 0XF8000728 0x00003FFF 0x00000600
-    mask_write 0XF800072C 0x00003FFF 0x00000600
-    mask_write 0XF8000730 0x00003FFF 0x00000600
-    mask_write 0XF8000734 0x00003FFF 0x00000600
-    mask_write 0XF8000738 0x00003FFF 0x00000600
-    mask_write 0XF800073C 0x00003FFF 0x00000600
-    mask_write 0XF8000740 0x00003FFF 0x00000302
-    mask_write 0XF8000744 0x00003FFF 0x00000302
-    mask_write 0XF8000748 0x00003FFF 0x00000302
-    mask_write 0XF800074C 0x00003FFF 0x00000302
-    mask_write 0XF8000750 0x00003FFF 0x00000302
-    mask_write 0XF8000754 0x00003FFF 0x00000302
-    mask_write 0XF8000758 0x00003FFF 0x00000303
-    mask_write 0XF800075C 0x00003FFF 0x00000303
-    mask_write 0XF8000760 0x00003FFF 0x00000303
-    mask_write 0XF8000764 0x00003FFF 0x00000303
-    mask_write 0XF8000768 0x00003FFF 0x00000303
-    mask_write 0XF800076C 0x00003FFF 0x00000303
-    mask_write 0XF8000770 0x00003FFF 0x00000304
-    mask_write 0XF8000774 0x00003FFF 0x00000305
-    mask_write 0XF8000778 0x00003FFF 0x00000304
-    mask_write 0XF800077C 0x00003FFF 0x00000305
-    mask_write 0XF8000780 0x00003FFF 0x00000304
-    mask_write 0XF8000784 0x00003FFF 0x00000304
-    mask_write 0XF8000788 0x00003FFF 0x00000304
-    mask_write 0XF800078C 0x00003FFF 0x00000304
-    mask_write 0XF8000790 0x00003FFF 0x00000305
-    mask_write 0XF8000794 0x00003FFF 0x00000304
-    mask_write 0XF8000798 0x00003FFF 0x00000304
-    mask_write 0XF800079C 0x00003FFF 0x00000304
-    mask_write 0XF80007A0 0x00003FFF 0x00000380
-    mask_write 0XF80007A4 0x00003FFF 0x00000380
-    mask_write 0XF80007A8 0x00003FFF 0x00000380
-    mask_write 0XF80007AC 0x00003FFF 0x00000380
-    mask_write 0XF80007B0 0x00003FFF 0x00000380
-    mask_write 0XF80007B4 0x00003FFF 0x00000380
-    mask_write 0XF80007B8 0x00003F01 0x00000201
-    mask_write 0XF80007BC 0x00003F01 0x00000201
-    mask_write 0XF80007C0 0x00003FFF 0x000002E0
-    mask_write 0XF80007C4 0x00003FFF 0x000002E1
-    mask_write 0XF80007C8 0x00003FFF 0x00000200
-    mask_write 0XF80007CC 0x00003FFF 0x00000200
-    mask_write 0XF80007D0 0x00003FFF 0x00000280
-    mask_write 0XF80007D4 0x00003FFF 0x00000280
-    mask_write 0XF8000830 0x003F003F 0x002F002E
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_2_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000B48 0x00000180 0x00000180
-    mask_write 0XF8000B4C 0x00000180 0x00000180
-    mask_write 0XF8000B50 0x00000180 0x00000180
-    mask_write 0XF8000B54 0x00000180 0x00000180
-    mwr -force 0XF8000004 0x0000767B
-    mask_write 0XE0001034 0x000000FF 0x00000006
-    mask_write 0XE0001018 0x0000FFFF 0x0000003E
-    mask_write 0XE0001000 0x000001FF 0x00000017
-    mask_write 0XE0001004 0x00000FFF 0x00000020
-    mask_write 0XE000D000 0x00080000 0x00080000
-    mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_2_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000900 0x0000000F 0x0000000F
-    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_2_0 {} {
-    mwr -force 0XF8898FB0 0xC5ACCE55
-    mwr -force 0XF8899FB0 0xC5ACCE55
-    mwr -force 0XF8809FB0 0xC5ACCE55
-}
-proc ps7_pll_init_data_1_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000110 0x003FFFF0 0x000FA220
-    mask_write 0XF8000100 0x0007F000 0x00028000
-    mask_write 0XF8000100 0x00000010 0x00000010
-    mask_write 0XF8000100 0x00000001 0x00000001
-    mask_write 0XF8000100 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000001
-    mask_write 0XF8000100 0x00000010 0x00000000
-    mask_write 0XF8000120 0x1F003F30 0x1F000200
-    mask_write 0XF8000114 0x003FFFF0 0x0012C220
-    mask_write 0XF8000104 0x0007F000 0x00020000
-    mask_write 0XF8000104 0x00000010 0x00000010
-    mask_write 0XF8000104 0x00000001 0x00000001
-    mask_write 0XF8000104 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000002
-    mask_write 0XF8000104 0x00000010 0x00000000
-    mask_write 0XF8000124 0xFFF00003 0x0C200003
-    mask_write 0XF8000118 0x003FFFF0 0x001452C0
-    mask_write 0XF8000108 0x0007F000 0x0001E000
-    mask_write 0XF8000108 0x00000010 0x00000010
-    mask_write 0XF8000108 0x00000001 0x00000001
-    mask_write 0XF8000108 0x00000001 0x00000000
-    mask_poll 0XF800010C 0x00000004
-    mask_write 0XF8000108 0x00000010 0x00000000
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_clock_init_data_1_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000128 0x03F03F01 0x00700F01
-    mask_write 0XF8000138 0x00000011 0x00000001
-    mask_write 0XF8000140 0x03F03F71 0x00100801
-    mask_write 0XF800014C 0x00003F31 0x00000501
-    mask_write 0XF8000150 0x00003F33 0x00001401
-    mask_write 0XF8000154 0x00003F33 0x00001402
-    mask_write 0XF8000168 0x00003F31 0x00000501
-    mask_write 0XF8000170 0x03F03F30 0x00200400
-    mask_write 0XF80001C4 0x00000001 0x00000001
-    mask_write 0XF800012C 0x01FFCCCD 0x01EC044D
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_ddr_init_data_1_0 {} {
-    mask_write 0XF8006000 0x0001FFFF 0x00000080
-    mask_write 0XF8006004 0x1FFFFFFF 0x00081081
-    mask_write 0XF8006008 0x03FFFFFF 0x03C0780F
-    mask_write 0XF800600C 0x03FFFFFF 0x02001001
-    mask_write 0XF8006010 0x03FFFFFF 0x00014001
-    mask_write 0XF8006014 0x001FFFFF 0x0004159B
-    mask_write 0XF8006018 0xF7FFFFFF 0x452460D2
-    mask_write 0XF800601C 0xFFFFFFFF 0x720238E5
-    mask_write 0XF8006020 0xFFFFFFFC 0x272872D0
-    mask_write 0XF8006024 0x0FFFFFFF 0x0000003C
-    mask_write 0XF8006028 0x00003FFF 0x00002007
-    mask_write 0XF800602C 0xFFFFFFFF 0x00000008
-    mask_write 0XF8006030 0xFFFFFFFF 0x00040930
-    mask_write 0XF8006034 0x13FF3FFF 0x000116D4
-    mask_write 0XF8006038 0x00001FC3 0x00000000
-    mask_write 0XF800603C 0x000FFFFF 0x00000777
-    mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000
-    mask_write 0XF8006044 0x0FFFFFFF 0x0FF66666
-    mask_write 0XF8006048 0x3FFFFFFF 0x0003C248
-    mask_write 0XF8006050 0xFF0F8FFF 0x77010800
-    mask_write 0XF8006058 0x0001FFFF 0x00000101
-    mask_write 0XF800605C 0x0000FFFF 0x00005003
-    mask_write 0XF8006060 0x000017FF 0x0000003E
-    mask_write 0XF8006064 0x00021FE0 0x00020000
-    mask_write 0XF8006068 0x03FFFFFF 0x00284141
-    mask_write 0XF800606C 0x0000FFFF 0x00001610
-    mask_write 0XF80060A0 0x00FFFFFF 0x00008000
-    mask_write 0XF80060A4 0xFFFFFFFF 0x10200802
-    mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73
-    mask_write 0XF80060AC 0x000001FF 0x000001FE
-    mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF
-    mask_write 0XF80060B4 0x000007FF 0x00000200
-    mask_write 0XF80060B8 0x01FFFFFF 0x00200066
-    mask_write 0XF80060C4 0x00000003 0x00000000
-    mask_write 0XF80060C8 0x000000FF 0x00000000
-    mask_write 0XF80060DC 0x00000001 0x00000000
-    mask_write 0XF80060F0 0x0000FFFF 0x00000000
-    mask_write 0XF80060F4 0x0000000F 0x00000008
-    mask_write 0XF8006114 0x000000FF 0x00000000
-    mask_write 0XF8006118 0x7FFFFFFF 0x40000001
-    mask_write 0XF800611C 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006120 0x7FFFFFFF 0x40000001
-    mask_write 0XF8006124 0x7FFFFFFF 0x40000001
-    mask_write 0XF800612C 0x000FFFFF 0x00033C03
-    mask_write 0XF8006130 0x000FFFFF 0x00034003
-    mask_write 0XF8006134 0x000FFFFF 0x0002F400
-    mask_write 0XF8006138 0x000FFFFF 0x00030400
-    mask_write 0XF8006140 0x000FFFFF 0x00000035
-    mask_write 0XF8006144 0x000FFFFF 0x00000035
-    mask_write 0XF8006148 0x000FFFFF 0x00000035
-    mask_write 0XF800614C 0x000FFFFF 0x00000035
-    mask_write 0XF8006154 0x000FFFFF 0x00000083
-    mask_write 0XF8006158 0x000FFFFF 0x00000083
-    mask_write 0XF800615C 0x000FFFFF 0x00000080
-    mask_write 0XF8006160 0x000FFFFF 0x00000080
-    mask_write 0XF8006168 0x001FFFFF 0x00000124
-    mask_write 0XF800616C 0x001FFFFF 0x00000125
-    mask_write 0XF8006170 0x001FFFFF 0x00000112
-    mask_write 0XF8006174 0x001FFFFF 0x00000116
-    mask_write 0XF800617C 0x000FFFFF 0x000000C3
-    mask_write 0XF8006180 0x000FFFFF 0x000000C3
-    mask_write 0XF8006184 0x000FFFFF 0x000000C0
-    mask_write 0XF8006188 0x000FFFFF 0x000000C0
-    mask_write 0XF8006190 0xFFFFFFFF 0x10040080
-    mask_write 0XF8006194 0x000FFFFF 0x0001FC82
-    mask_write 0XF8006204 0xFFFFFFFF 0x00000000
-    mask_write 0XF8006208 0x000F03FF 0x000803FF
-    mask_write 0XF800620C 0x000F03FF 0x000803FF
-    mask_write 0XF8006210 0x000F03FF 0x000803FF
-    mask_write 0XF8006214 0x000F03FF 0x000803FF
-    mask_write 0XF8006218 0x000F03FF 0x000003FF
-    mask_write 0XF800621C 0x000F03FF 0x000003FF
-    mask_write 0XF8006220 0x000F03FF 0x000003FF
-    mask_write 0XF8006224 0x000F03FF 0x000003FF
-    mask_write 0XF80062A8 0x00000FF7 0x00000000
-    mask_write 0XF80062AC 0xFFFFFFFF 0x00000000
-    mask_write 0XF80062B0 0x003FFFFF 0x00005125
-    mask_write 0XF80062B4 0x0003FFFF 0x000012A8
-    mask_poll 0XF8000B74 0x00002000
-    mask_write 0XF8006000 0x0001FFFF 0x00000081
-    mask_poll 0XF8006054 0x00000007
-}
-proc ps7_mio_init_data_1_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000B40 0x00000FFF 0x00000600
-    mask_write 0XF8000B44 0x00000FFF 0x00000600
-    mask_write 0XF8000B48 0x00000FFF 0x00000672
-    mask_write 0XF8000B4C 0x00000FFF 0x00000672
-    mask_write 0XF8000B50 0x00000FFF 0x00000674
-    mask_write 0XF8000B54 0x00000FFF 0x00000674
-    mask_write 0XF8000B58 0x00000FFF 0x00000600
-    mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C
-    mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C
-    mask_write 0XF8000B6C 0x000073FF 0x00000209
-    mask_write 0XF8000B70 0x00000021 0x00000021
-    mask_write 0XF8000B70 0x00000021 0x00000020
-    mask_write 0XF8000B70 0x07FFFFFF 0x00000823
-    mask_write 0XF8000700 0x00003FFF 0x00000600
-    mask_write 0XF8000704 0x00003FFF 0x00000702
-    mask_write 0XF8000708 0x00003FFF 0x00000702
-    mask_write 0XF800070C 0x00003FFF 0x00000702
-    mask_write 0XF8000710 0x00003FFF 0x00000702
-    mask_write 0XF8000714 0x00003FFF 0x00000702
-    mask_write 0XF8000718 0x00003FFF 0x00000702
-    mask_write 0XF800071C 0x00003FFF 0x00000600
-    mask_write 0XF8000720 0x00003FFF 0x00000700
-    mask_write 0XF8000724 0x00003FFF 0x00000600
-    mask_write 0XF8000728 0x00003FFF 0x00000600
-    mask_write 0XF800072C 0x00003FFF 0x00000600
-    mask_write 0XF8000730 0x00003FFF 0x00000600
-    mask_write 0XF8000734 0x00003FFF 0x00000600
-    mask_write 0XF8000738 0x00003FFF 0x00000600
-    mask_write 0XF800073C 0x00003FFF 0x00000600
-    mask_write 0XF8000740 0x00003FFF 0x00000302
-    mask_write 0XF8000744 0x00003FFF 0x00000302
-    mask_write 0XF8000748 0x00003FFF 0x00000302
-    mask_write 0XF800074C 0x00003FFF 0x00000302
-    mask_write 0XF8000750 0x00003FFF 0x00000302
-    mask_write 0XF8000754 0x00003FFF 0x00000302
-    mask_write 0XF8000758 0x00003FFF 0x00000303
-    mask_write 0XF800075C 0x00003FFF 0x00000303
-    mask_write 0XF8000760 0x00003FFF 0x00000303
-    mask_write 0XF8000764 0x00003FFF 0x00000303
-    mask_write 0XF8000768 0x00003FFF 0x00000303
-    mask_write 0XF800076C 0x00003FFF 0x00000303
-    mask_write 0XF8000770 0x00003FFF 0x00000304
-    mask_write 0XF8000774 0x00003FFF 0x00000305
-    mask_write 0XF8000778 0x00003FFF 0x00000304
-    mask_write 0XF800077C 0x00003FFF 0x00000305
-    mask_write 0XF8000780 0x00003FFF 0x00000304
-    mask_write 0XF8000784 0x00003FFF 0x00000304
-    mask_write 0XF8000788 0x00003FFF 0x00000304
-    mask_write 0XF800078C 0x00003FFF 0x00000304
-    mask_write 0XF8000790 0x00003FFF 0x00000305
-    mask_write 0XF8000794 0x00003FFF 0x00000304
-    mask_write 0XF8000798 0x00003FFF 0x00000304
-    mask_write 0XF800079C 0x00003FFF 0x00000304
-    mask_write 0XF80007A0 0x00003FFF 0x00000380
-    mask_write 0XF80007A4 0x00003FFF 0x00000380
-    mask_write 0XF80007A8 0x00003FFF 0x00000380
-    mask_write 0XF80007AC 0x00003FFF 0x00000380
-    mask_write 0XF80007B0 0x00003FFF 0x00000380
-    mask_write 0XF80007B4 0x00003FFF 0x00000380
-    mask_write 0XF80007B8 0x00003F01 0x00000201
-    mask_write 0XF80007BC 0x00003F01 0x00000201
-    mask_write 0XF80007C0 0x00003FFF 0x000002E0
-    mask_write 0XF80007C4 0x00003FFF 0x000002E1
-    mask_write 0XF80007C8 0x00003FFF 0x00000200
-    mask_write 0XF80007CC 0x00003FFF 0x00000200
-    mask_write 0XF80007D0 0x00003FFF 0x00000280
-    mask_write 0XF80007D4 0x00003FFF 0x00000280
-    mask_write 0XF8000830 0x003F003F 0x002F002E
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_peripherals_init_data_1_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000B48 0x00000180 0x00000180
-    mask_write 0XF8000B4C 0x00000180 0x00000180
-    mask_write 0XF8000B50 0x00000180 0x00000180
-    mask_write 0XF8000B54 0x00000180 0x00000180
-    mwr -force 0XF8000004 0x0000767B
-    mask_write 0XE0001034 0x000000FF 0x00000006
-    mask_write 0XE0001018 0x0000FFFF 0x0000003E
-    mask_write 0XE0001000 0x000001FF 0x00000017
-    mask_write 0XE0001004 0x00000FFF 0x00000020
-    mask_write 0XE000D000 0x00080000 0x00080000
-    mask_write 0XF8007000 0x20000000 0x00000000
-}
-proc ps7_post_config_1_0 {} {
-    mwr -force 0XF8000008 0x0000DF0D
-    mask_write 0XF8000900 0x0000000F 0x0000000F
-    mask_write 0XF8000240 0xFFFFFFFF 0x00000000
-    mwr -force 0XF8000004 0x0000767B
-}
-proc ps7_debug_1_0 {} {
-    mwr -force 0XF8898FB0 0xC5ACCE55
-    mwr -force 0XF8899FB0 0xC5ACCE55
-    mwr -force 0XF8809FB0 0xC5ACCE55
-}
-set PCW_SILICON_VER_1_0 "0x0"
-set PCW_SILICON_VER_2_0 "0x1"
-set PCW_SILICON_VER_3_0 "0x2"
-set APU_FREQ  666666667
-
-
-
-proc mask_poll { addr mask } {
-    set count 1
-    set curval "0x[string range [mrd $addr] end-8 end]"
-    set maskedval [expr {$curval & $mask}]
-    while { $maskedval == 0 } {
-        set curval "0x[string range [mrd $addr] end-8 end]"
-        set maskedval [expr {$curval & $mask}]
-        set count [ expr { $count + 1 } ]
-        if { $count == 100000000 } {
-          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
-          break
-        }
-    }
-}
-
-
-
-proc mask_delay { addr val } {
-    set delay  [ get_number_of_cycles_for_delay $val ]
-    perf_reset_and_start_timer
-    set curval "0x[string range [mrd $addr] end-8 end]"
-    set maskedval [expr {$curval < $delay}]
-    while { $maskedval == 1 } {
-        set curval "0x[string range [mrd $addr] end-8 end]"
-        set maskedval [expr {$curval < $delay}]
-    }
-    perf_reset_clock 
-}
-
-proc ps_version { } {
-    set si_ver "0x[string range [mrd 0xF8007080] end-8 end]"
-    set mask_sil_ver "0x[expr {$si_ver >> 28}]"
-    return $mask_sil_ver;
-}
-
-proc ps7_post_config {} {
-
-        ps7_post_config_1_0   
-
-}
-
-proc ps7_debug {} {
-        ps7_debug_1_0   
-
-}
-proc ps7_init {} {
-
-            ps7_mio_init_data_1_0
-            ps7_pll_init_data_1_0
-            ps7_clock_init_data_1_0
-            ps7_ddr_init_data_1_0
-            ps7_peripherals_init_data_1_0
-}
-
-
-# For delay calculation using global timer 
-
-# start timer 
- proc perf_start_clock { } {
-
-    #writing SCU_GLOBAL_TIMER_CONTROL register
-
-    mask_write 0xF8F00208 0x00000109 0x00000009
-}
-
-# stop timer and reset timer count regs 
- proc perf_reset_clock { } {
-	perf_disable_clock
-    mask_write 0xF8F00200 0xFFFFFFFF 0x00000000
-    mask_write 0xF8F00204 0xFFFFFFFF 0x00000000
-}
-
-# Compute mask for given delay in miliseconds
-proc get_number_of_cycles_for_delay { delay } {
-
-  # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
-  variable APU_FREQ
-  return [ expr ($delay * $APU_FREQ /(2 * 1000))]
-}
-
-
-# stop timer 
-proc perf_disable_clock {} {
-    mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 
-}
-
-proc perf_reset_and_start_timer {} {
-  	    perf_reset_clock 
-	    perf_start_clock 
-}
-
-

openocd/xilinx-tcl.cfg

@@ -1,61 +0,0 @@
-#
-# TCL to allow the Xilinx PS7 Init TCL code to run in OpenOCD.
-#
-
-proc mrd { args } {
-    if {[llength $args] == 0} {
-        echo "mrd address \[count \[w|h|b\]\]"
-        echo "    Read <count> memory locations starting at <address>.  Defaults to one word."
-        return
-    }
-    set addr [lindex $args 0]
-    set count  1
-    set bits  32
-    if {[llength $args] > 1} {
-        set count [lindex $args 1]
-        if {[llength $args] > 2} {
-            switch [lindex $args 2] {
-                w       { set bits 32 }
-                h       { set bits 16 }
-                b       { set bits  8 }
-                default { set bits 32 }
-            }
-        }
-    }
-    mem2array x $bits $addr $count
-    set nibbles [expr {$bits / 4}]
-    set bytes   [expr {$bits / 8}]
-    set result  {}
-    foreach {idx elmt} $x {
-        append result [format "%08x:   %0*x\n" [expr {$addr + $idx * $bytes}] $nibbles $elmt]
-    }
-    return $result
-}
-
-proc mwr { args } {
-  set addr [lindex $args 1]
-  set data [lindex $args 2]
-  mww $addr $data
-}
-
-proc mask_write { addr mask value } {
-    set curval "0x[string range [mrd $addr] end-8 end]"
-    set maskedval [expr {$curval & ~$mask}]
-    #echo "curval = [format 0x%08x $curval] maskedval = [format 0x%08x $maskedval]"
-    set writeval(0) [expr {$maskedval | $value}]
-    #echo " $addr <= [format 0x%08x $writeval(0)] ([format 0x%08x $curval]: [format 0x%08x $mask]/[format 0x%08x $value])"
-    array2mem writeval 32 $addr 1
-}
-
-proc xilinx_ps7_init { } {
-   poll off
-   reset init
-   reset halt
-   targets zynq.cpu.0
-   sleep 100
-   halt
-   ps7_debug
-   ps7_init
-   ps7_post_config
-   poll on
-}

openocd/zc706.cfg

@@ -1,43 +0,0 @@
-source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
-source [find xilinx-tcl.cfg]
-adapter_khz 1000
-
-set PL_TAPID 0x23731093
-set SMP 1
-
-source ./zynq-7000.cfg
-source ./xilinx-tcl.cfg
-source ./ps7_init.tcl
-
-reset_config srst_only srst_open_drain
-adapter_nsrst_assert_width 250
-adapter_nsrst_delay 400
-
-set XC7_JSHUTDOWN 0x0d
-set XC7_JPROGRAM 0x0b
-set XC7_JSTART 0x0c
-set XC7_BYPASS 0x3f
-
-proc xc7_program {tap} {
-    global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
-    irscan $tap $XC7_JSHUTDOWN
-    irscan $tap $XC7_JPROGRAM
-    runtest 60000
-    #JSTART prevents this from working...
-    #irscan $tap $XC7_JSTART
-    runtest 2000
-    irscan $tap $XC7_BYPASS
-    runtest 2000
-}
-
-pld device virtex2 zynq.tap 1
-init
-xc7_program zynq.tap
-
-xilinx_ps7_init
-
-# Disable MMU
-targets $_TARGETNAME_1
-arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]
-targets $_TARGETNAME_0
-arm mcr 15 0 1 0 0 [expr [arm mrc 15 0 1 0 0] & ~0xd]

openocd/zynq-7000.cfg

@@ -1,211 +0,0 @@
-#
-# Xilinx Zynq 7000 SoC
-#
-#  Chris Johns <chrisj@rtems.org>
-#
-# Setup
-# -----
-#
-# Create a user configuration following the "Configuration Basics" in the user
-# documentation. In the file have:
-#
-#    source [find interface/ftdi/flyswatter2.cfg]
-#    source [find board/zynq-zc706-eval.cfg]
-#    adapter_khz 2000
-#    init
-#
-
-if { [info exists CHIPNAME] } {
-    global _CHIPNAME
-    set _CHIPNAME $CHIPNAME
-} else {
-    global _CHIPNAME
-    set _CHIPNAME zynq
-}
-
-if { [info exists ENDIAN] } {
-    set _ENDIAN $ENDIAN
-} else {
-    # this defaults to a bigendian
-    set _ENDIAN little
-}
-
-if { [info exists SMP] } {
-    global _SMP
-    set _SMP 1
-} else {
-    global _SMP
-    set _SMP 0
-}
-
-#
-# PL Tap.
-#
-# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
-#   0x03731093 - ZC706 Eval board 1.1
-#   0x23731093 - ??
-#   0x23727093 - Zedboard Rev. C and D
-#
-# Set in your configuration file or board specific file.
-#
-if { [info exists PL_TAPID] } {
-    set _PL_TAPID $PL_TAPID
-} else {
-    set _PL_TAPID 0x03731093
-}
-
-jtag newtap $_CHIPNAME tap -irlen 6 -ircapture 0x001 -irmask 0x003 \
-    -expected-id $_PL_TAPID
-
-#
-# CoreSight Debug Access Port
-#
-if { [info exists DAP_TAPID] } {
-    set _DAP_TAPID $DAP_TAPID
-} else {
-    set _DAP_TAPID 0x4ba00477
-}
-
-jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x03 \
-    -expected-id $_DAP_TAPID
-
-#
-# GDB target: Cortex-A9, using DAP, configuring only one core
-# Base addresses of cores:
-# core 0  -  0xF8890000
-# core 1  -  0xF8892000
-#
-# Read from the ROM table with the patch to read the nested table.
-#
-
-set _TARGETNAME_0 $_CHIPNAME.cpu.0
-set _TARGETNAME_1 $_CHIPNAME.cpu.1
-
-target create $_TARGETNAME_0 cortex_a -coreid 0 \
-    -endian $_ENDIAN \
-    -chain-position $_CHIPNAME.dap \
-    -dbgbase 0x80090000
-if { $_SMP } {
-    echo "Zynq CPU1."
-    target create $_TARGETNAME_1 cortex_a -coreid 1 \
-        -endian $_ENDIAN \
-        -chain-position $_CHIPNAME.dap \
-        -dbgbase 0x80092000
-    target smp $_TARGETNAME_0 $_TARGETNAME_1
-}
-
-#
-# Hack to get the registers into a stable state when first booting a zynq in
-# JTAG mode. If r11 is pointing to an invalid address and you use gdb to set a
-# register the write will fail because gdb attempts to scan or unwind the
-# current frame and the bad address seems to lock the bus up. This code puts
-# the registers into the OCM and hopefull safe.
-#
-proc zynq_clear_registers { target } {
-    echo "Zynq-7000 Series setup: $target"
-    set _OCM_END 0x0003FFF0
-    mww phys 0xF8007000 0x4E00E07F
-    reg r0 0
-    reg r1 0
-    reg r2 0
-    reg r3 0
-    reg r4 0
-    reg r5 0
-    reg r6 0
-    reg r7 0
-    reg r8 0
-    reg r9 0
-    reg r10 0
-    reg r11 $_OCM_END
-    reg sp_svc $_OCM_END
-    reg lr_svc $_OCM_END
-    reg sp_abt $_OCM_END
-    reg lr_abt $_OCM_END
-    reg sp_und $_OCM_END
-    reg lr_und $_OCM_END
-}
-
-proc zynq_disable_mmu_and_caches { target } {
-    # arm mcr pX op1 CRn CRm op2 value
-    echo "Disable MMU and caches"
-    # Invalidate caches
-    catch {
-        $target arm mcr 15 0 7 5 0 0
-        $target arm mcr 15 0 7 7 0 0
-        # Invalidate all TLBs
-        $target arm mcr 15 0 8 5 0 0
-        $target arm mcr 15 0 8 6 0 0
-        $target arm mcr 15 0 8 7 0 0
-        $target arm mcr 15 4 8 3 0 0
-        $target arm mcr 15 4 8 7 0 0
-        set cp [$target arm mrc 15 0 1 0 0]
-        echo "SCTRL => [format 0x%x $cp]"
-        set mask [expr 1 << 29 | 1 << 12 | 1 << 11 | 1 << 2 | 1 << 1 | 1 << 0]
-        set cp [expr ($cp & ~$mask)]
-        $target arm mcr 15 0 1 0 0 $cp
-        echo "SCTRL <= [format 0x%x $cp]"
-    }
-}
-
-proc zynq_boot_ocm_setup { } {
-    #
-    # Enable the OCM
-    #
-    echo "Zynq Boot OCM setup"
-    catch {
-      mww phys 0xF8000008 0xDF0D
-      mww phys 0xF8000238 0
-      mww phys 0xF8000910 0xC
-    }
-}
-
-proc zynq_rtems_setup { } {
-    cache_config l2x 0xF8F02000 8
-    cortex_a maskisr on
-}
-
-proc zynq_restart { wait } {
-    global _SMP
-    global _TARGETNAME_0
-    global _TARGETNAME_1
-    set target0 $_TARGETNAME_0
-    set target1 $_TARGETNAME_1
-    echo "Zynq reset, resetting the board ... "
-    poll off
-    #
-    # Issue the reset via the SLCR
-    #
-    catch {
-        mww phys 0xF8000008 0xDF0D
-        mww phys 0xF8000200 1
-    }
-    echo "Zynq reset waiting for $wait msecs ... "
-    sleep $wait
-    #
-    # Reconnect the DAP etc due to the reset.
-    #
-    $target0 cortex_a dbginit
-    $target0 arm core_state arm
-    if { $_SMP } {
-        $target1 arm core_state arm
-        $target1 cortex_a dbginit
-        cortex_a smp_off
-    }
-    poll on
-    #
-    # We can now halt the core.
-    #
-    if { $_SMP } {
-        targets $target1
-        halt
-    }
-    targets $target0
-    halt
-    zynq_rtems_setup
-}
-
-proc zynq_gdb_attach { target } {
-    catch {
-      halt
-    }
-}

remote_run.sh

@@ -1,30 +1,69 @@
 #!/usr/bin/env bash
 
+# Only ZC706 supported for now.
+
 set -e
 
+if [ -z "$OPENOCD_ZYNQ" ]; then
+    echo "OPENOCD_ZYNQ environment variable must be set"
+    exit 1
+fi
+if [ -z "$SZL" ]; then
+    echo "SZL environment variable must be set"
+    exit 1
+fi
+
 target_host="rpi-4.m-labs.hk"
 impure=0
+pure_dir="result"
+impure_dir="build"
+sshopts=""
+load_bitstream=1
+board_host="192.168.1.52"
+fw_type="runtime"
 
-while getopts "h:i" opt; do
+while getopts "h:id:o:lt:" opt; do
     case "$opt" in
-    \?) exit 0
+    \?) exit 1
         ;;
     h)  target_host=$OPTARG
         ;;
     i)  impure=1
         ;;
+    d)  pure_dir=$OPTARG;
+        impure_dir=$OPTARG;
+        ;;
+    o)  sshopts=$OPTARG
+        ;;
+    l)  load_bitstream=0
+        ;;
+    b)  board_host=$OPTARG
+        ;;
+    t)  fw_type=$OPTARG
+        ;;
     esac
 done
 
-target_folder=/tmp/zynq-\$USER
+target_folder="/tmp/zynq-$USER"
+load_bitstream_cmd=""
 
-ssh $target_host "mkdir -p $target_folder"
-rsync openocd/* $target_host:$target_folder
+echo "Creating $target_folder..."
+ssh $sshopts $target_host "mkdir -p $target_folder"
+echo "Copying files..."
+rsync -e "ssh $sshopts" -Lc $OPENOCD_ZYNQ/* $target_host:$target_folder
+rsync -e "ssh $sshopts" -Lc $SZL/szl-zc706.elf $target_host:$target_folder/szl.elf
 if [ $impure -eq 1 ]; then
-    rsync build/firmware/armv7-none-eabihf/release/szl $target_host:$target_folder/szl.elf
-    rsync build/gateware/top.bit $target_host:$target_folder
+    if [ $load_bitstream -eq 1 ]; then
+        load_bitstream_cmd="-g build/gateware/top.bit"
+    fi
+    firmware="build/$fw_type.bin"
 else
-    rsync -L result/szl.elf $target_host:$target_folder
-    rsync -L result/top.bit $target_host:$target_folder
+    if [ $load_bitstream -eq 1 ]; then
+        load_bitstream_cmd="-g $pure_dir/top.bit"
+    fi
+    firmware="$pure_dir/$fw_type.bin"    
 fi
-ssh $target_host "cd $target_folder; openocd -f zc706.cfg -c 'pld load 0 top.bit; load_image szl.elf; resume 0; exit'"
+echo "Programming board..."
+ssh $sshopts $target_host "cd $target_folder; openocd -f zc706.cfg -c'load_image szl.elf; resume 0; exit'"
+sleep 5
+artiq_netboot $load_bitstream_cmd -f $firmware -b $board_host

rustPlatform.nix

@@ -1,24 +0,0 @@
-{ pkgs }:
-
-let
-  rustcSrc = pkgs.fetchgit {
-    url = "https://github.com/rust-lang/rust.git";
-    # master of 2020-04-10
-    rev = "94d346360da50f159e0dc777dc9bc3c5b6b51a00";
-    sha256 = "1hcqdz4w2vqb12rrqqcjbfs5s0w4qwjn7z45d1zh0fzncdcf6f7d";
-    fetchSubmodules = true;
-  };
-  rustManifest = ./channel-rust-nightly.toml;
-
-  targets = [];
-  rustChannelOfTargets = _channel: _date: targets:
-    (pkgs.lib.rustLib.fromManifestFile rustManifest {
-      inherit (pkgs) stdenv fetchurl patchelf;
-    }).rust.override { inherit targets; };
-  rust =
-    rustChannelOfTargets "nightly" null targets;
-in
-  pkgs.recurseIntoAttrs (pkgs.makeRustPlatform {
-    rustc = rust // { src = rustcSrc; };
-    cargo = rust;
-  })

shell.nix

@@ -1,30 +0,0 @@
-let
-  mozillaOverlay = import (builtins.fetchTarball "https://github.com/mozilla/nixpkgs-mozilla/archive/master.tar.gz");
-  pkgs = import <nixpkgs> { overlays = [ mozillaOverlay ]; };
-  artiq-fast = <artiq-fast>;
-  rustPlatform = (import ./rustPlatform.nix { inherit pkgs; });
-  artiqpkgs = import "${artiq-fast}/default.nix" { inherit pkgs; };
-  vivado = import "${artiq-fast}/vivado.nix" { inherit pkgs; };
-in
-  pkgs.stdenv.mkDerivation {
-    name = "artiq-zynq-env";
-    buildInputs = [
-      pkgs.gnumake
-      rustPlatform.rust.rustc
-      rustPlatform.rust.cargo
-      pkgs.llvm_9
-      pkgs.clang_9
-      pkgs.cacert
-      pkgs.cargo-xbuild
-
-      pkgs.openocd
-      pkgs.openssh pkgs.rsync
-
-      (pkgs.python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq ])))
-      vivado
-
-      (import ./mkbootimage.nix { inherit pkgs; })
-    ];
-
-    XARGO_RUST_SRC = "${rustPlatform.rust.rustc.src}/src";
-  }

src/.clang-format

@@ -0,0 +1,32 @@
+BasedOnStyle: LLVM
+
+Language: Cpp
+Standard: Cpp11
+
+AccessModifierOffset: -1
+AlignEscapedNewlines: Left
+AlwaysBreakAfterReturnType: None
+AlwaysBreakTemplateDeclarations: Yes
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortFunctionsOnASingleLine: Inline
+BinPackParameters: false
+BreakBeforeBinaryOperators: NonAssignment
+BreakBeforeTernaryOperators: true
+BreakConstructorInitializers: AfterColon
+BreakInheritanceList: AfterColon
+ColumnLimit: 120
+ConstructorInitializerAllOnOneLineOrOnePerLine: true
+ContinuationIndentWidth: 4
+DerivePointerAlignment: false
+IndentCaseLabels: true
+IndentPPDirectives: None
+IndentWidth: 4
+MaxEmptyLinesToKeep: 1
+PointerAlignment: Left
+ReflowComments: true
+SortIncludes: false
+SortUsingDeclarations: true
+SpaceAfterTemplateKeyword: false
+SpacesBeforeTrailingComments: 2
+TabWidth: 4
+UseTab: Never

src/.clippy.toml

@@ -0,0 +1 @@
+doc-valid-idents = ["CPython", "NumPy", ".."]

src/.pre-commit-config.yaml

@@ -0,0 +1,32 @@
+# See https://pre-commit.com for more information
+# See https://pre-commit.com/hooks.html for more hooks
+
+default_stages: [commit]
+
+repos:
+  - repo: local
+    hooks:
+      - id: cargo-fmt
+        name: artiq-zynq cargo format
+        entry: nix
+        language: system
+        types: [file, rust]
+        pass_filenames: false
+        description: Runs cargo fmt on the codebase.
+        args: [develop, -c, cargo, fmt, --manifest-path, src/Cargo.toml, --all]
+      - id: cargo-clippy
+        name: artiq-zynq cargo clippy
+        entry: nix
+        language: system
+        types: [file, rust]
+        pass_filenames: false
+        description: Runs cargo clippy on the codebase.
+        args: [develop, -c, cargo, clippy, --manifest-path, src/Cargo.toml, --tests]
+  - repo: https://github.com/pre-commit/mirrors-clang-format
+    rev: v19.1.0
+    hooks:
+      - id: clang-format
+        name: artiq-zynq clang-format
+        description: Runs clang-format on the codebase.
+        files: \.(cpp|h|hpp|c)$
+        args: [-style=file, -fallback-style=none, -assume-filename=src/.clang-format]

src/Cargo.lock

@@ -1,10 +1,27 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
+version = 3
+
+[[package]]
+name = "approx"
+version = "0.5.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "cab112f0a86d568ea0e627cc1d6be74a1e9cd55214684db5561995f6dad897c6"
+dependencies = [
+ "num-traits",
+]
+
+[[package]]
+name = "arrayvec"
+version = "0.7.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "96d30a06541fbafbc7f82ed10c06164cfbd2c401138f6addd8404629c4b16711"
+
 [[package]]
 name = "async-recursion"
-version = "0.3.1"
+version = "0.3.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e5444eec77a9ec2bfe4524139e09195862e981400c4358d3b760cae634e4c4ee"
+checksum = "d7d78656ba01f1b93024b7c3a0467f1608e4be67d725749fdcd7d2c7678fd7a2"
 dependencies = [
  "proc-macro2",
  "quote",
@@ -13,27 +30,43 @@ dependencies = [
 
 [[package]]
 name = "autocfg"
-version = "1.0.0"
+version = "1.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f8aac770f1885fd7e387acedd76065302551364496e46b3dd00860b2f8359b9d"
+checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
 
 [[package]]
 name = "bit_field"
-version = "0.10.0"
+version = "0.10.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a165d606cf084741d4ac3a28fb6e9b1eb0bd31f6cd999098cfddb0b2ab381dc0"
+checksum = "dcb6dd1c2376d2e096796e234a70e17e94cc2d5d54ff8ce42b28cef1d0d359a4"
 
 [[package]]
 name = "bitflags"
-version = "1.2.1"
+version = "1.3.2"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cf1de2fe8c75bc145a2f577add951f8134889b4795d47466a54a5c846d691693"
+checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
+
+[[package]]
+name = "build_const"
+version = "0.2.2"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "b4ae4235e6dac0694637c763029ecea1a2ec9e4e06ec2729bd21ba4d9c863eb7"
+
+[[package]]
+name = "build_zynq"
+version = "0.0.0"
 
 [[package]]
 name = "byteorder"
-version = "1.3.4"
+version = "1.4.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "08c48aae112d48ed9f069b33538ea9e3e90aa263cfa3d1c24309612b1f7472de"
+checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
+
+[[package]]
+name = "cc"
+version = "1.0.77"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "e9f73505338f7d905b19d18738976aae232eb46b8efc15554ffc56deb5d9ebe4"
 
 [[package]]
 name = "cfg-if"
@@ -42,16 +75,33 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "4785bdd1c96b2a846b2bd7cc02e86b6b3dbf14e7e53446c4f54c92a361040822"
 
 [[package]]
-name = "compiler_builtins"
-version = "0.1.32"
+name = "cfg-if"
+version = "1.0.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7bc4ac2c824d2bfc612cba57708198547e9a26943af0632aff033e0693074d5c"
+checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
+
+[[package]]
+name = "compiler_builtins"
+version = "0.1.39"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
 
 [[package]]
 name = "core_io"
-version = "0.1.20200410"
+version = "0.1.20210325"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
 dependencies = [
- "memchr",
+ "rustc_version",
+]
+
+[[package]]
+name = "crc"
+version = "1.8.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d663548de7f5cca343f1e0a48d14dcfb0e9eb4e079ec58883b7251539fa10aeb"
+dependencies = [
+ "build_const",
 ]
 
 [[package]]
@@ -61,43 +111,39 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"
 
 [[package]]
-name = "cstr_core"
-version = "0.2.0"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8758514b5f03968703f1db1f1e196e031d5268f5295ff99a5bf345008790ba85"
+name = "dwarf"
+version = "0.0.0"
 dependencies = [
- "cty",
- "memchr",
+ "cfg-if 0.1.10",
+ "compiler_builtins",
+ "cslice",
+ "libc",
+ "unwind",
 ]
 
-[[package]]
-name = "cty"
-version = "0.2.1"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7313c0d620d0cb4dbd9d019e461a4beb501071ff46ec0ab933efb4daa76d73e3"
-
 [[package]]
 name = "dyld"
 version = "0.1.0"
 dependencies = [
+ "libcortex_a9",
  "log",
 ]
 
 [[package]]
 name = "embedded-hal"
-version = "0.2.4"
+version = "0.2.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "fa998ce59ec9765d15216393af37a58961ddcefb14c753b4816ba2191d865fcb"
+checksum = "35949884794ad573cf46071e41c9b60efb0cb311e3ca01f7af807af1debc66ff"
 dependencies = [
- "nb",
+ "nb 0.1.3",
  "void",
 ]
 
 [[package]]
 name = "fatfs"
-version = "0.3.3"
+version = "0.3.5"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f6d1df9e4503954f60504a5ee4fc435cd65cc42e98b2081f7f421be5f2e68e7d"
+checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
 dependencies = [
  "bitflags",
  "byteorder",
@@ -107,9 +153,9 @@ dependencies = [
 
 [[package]]
 name = "futures"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "1e05b85ec287aac0dc34db7d4a569323df697f9c55b99b15d6b4ef8cde49f613"
+checksum = "38390104763dc37a5145a53c29c63c1290b5d316d6086ec32c293f6736051bb0"
 dependencies = [
  "futures-channel",
  "futures-core",
@@ -121,9 +167,9 @@ dependencies = [
 
 [[package]]
 name = "futures-channel"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f366ad74c28cca6ba456d95e6422883cfb4b252a83bed929c83abfdbbf2967d5"
+checksum = "52ba265a92256105f45b719605a571ffe2d1f0fea3807304b522c1d778f79eed"
 dependencies = [
  "futures-core",
  "futures-sink",
@@ -131,23 +177,22 @@ dependencies = [
 
 [[package]]
 name = "futures-core"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "59f5fff90fd5d971f936ad674802482ba441b6f09ba5e15fd8b39145582ca399"
+checksum = "04909a7a7e4633ae6c4a9ab280aeb86da1236243a77b694a49eacd659a4bd3ac"
 
 [[package]]
 name = "futures-io"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "de27142b013a8e869c14957e6d2edeef89e97c289e69d042ee3a49acd8b51789"
+checksum = "00f5fb52a06bdcadeb54e8d3671f8888a39697dcb0b81b23b55174030427f4eb"
 
 [[package]]
 name = "futures-macro"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d0b5a30a4328ab5473878237c447333c093297bded83a4983d10f4deea240d39"
+checksum = "bdfb8ce053d86b91919aad980c220b1fb8401a9394410e1c289ed7e66b61835d"
 dependencies = [
- "proc-macro-hack",
  "proc-macro2",
  "quote",
  "syn",
@@ -155,73 +200,152 @@ dependencies = [
 
 [[package]]
 name = "futures-sink"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3f2032893cb734c7a05d85ce0cc8b8c4075278e93b24b66f9de99d6eb0fa8acc"
+checksum = "39c15cf1a4aa79df40f1bb462fb39676d0ad9e366c2a33b590d7c66f4f81fcf9"
 
 [[package]]
 name = "futures-task"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "bdb66b5f09e22019b1ab0830f7785bcea8e7a42148683f99214f73f8ec21a626"
+checksum = "2ffb393ac5d9a6eaa9d3fdf37ae2776656b706e200c8e16b1bdb227f5198e6ea"
 
 [[package]]
 name = "futures-util"
-version = "0.3.5"
+version = "0.3.25"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "8764574ff08b701a084482c3c7031349104b07ac897393010494beaa18ce32c6"
+checksum = "197676987abd2f9cadff84926f410af1c183608d36641465df73ae8211dc65d6"
 dependencies = [
  "futures-core",
  "futures-macro",
  "futures-sink",
  "futures-task",
- "pin-project",
+ "pin-project-lite",
  "pin-utils",
- "proc-macro-hack",
- "proc-macro-nested",
+]
+
+[[package]]
+name = "io"
+version = "0.0.0"
+dependencies = [
+ "byteorder",
+ "core_io",
+ "libsupport_zynq",
+]
+
+[[package]]
+name = "ksupport"
+version = "0.1.0"
+dependencies = [
+ "build_zynq",
+ "byteorder",
+ "core_io",
+ "cslice",
+ "dwarf",
+ "dyld",
+ "io",
+ "libasync",
+ "libboard_artiq",
+ "libboard_zynq",
+ "libc",
+ "libconfig",
+ "libcortex_a9",
+ "libm",
+ "libregister",
+ "libsupport_zynq",
+ "log",
+ "log_buffer",
+ "nalgebra",
+ "nb 0.1.3",
+ "unwind",
+ "vcell",
+ "void",
 ]
 
 [[package]]
 name = "libasync"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ec252b099cf67a51ba9daa72b3292db8c21ba1b8"
 dependencies = [
  "embedded-hal",
  "libcortex_a9",
- "nb",
+ "nb 1.0.0",
  "pin-utils",
  "smoltcp",
 ]
 
+[[package]]
+name = "libboard_artiq"
+version = "0.0.0"
+dependencies = [
+ "build_zynq",
+ "core_io",
+ "crc",
+ "embedded-hal",
+ "io",
+ "libasync",
+ "libboard_zynq",
+ "libconfig",
+ "libcortex_a9",
+ "libregister",
+ "libsupport_zynq",
+ "log",
+ "log_buffer",
+ "nb 1.0.0",
+ "void",
+]
+
 [[package]]
 name = "libboard_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ec252b099cf67a51ba9daa72b3292db8c21ba1b8"
 dependencies = [
  "bit_field",
  "embedded-hal",
+ "libasync",
  "libcortex_a9",
  "libregister",
  "log",
- "nb",
+ "nb 0.1.3",
  "smoltcp",
  "void",
  "volatile-register",
 ]
 
+[[package]]
+name = "libc"
+version = "0.1.0"
+dependencies = [
+ "cc",
+ "libboard_zynq",
+]
+
+[[package]]
+name = "libconfig"
+version = "0.1.0"
+dependencies = [
+ "core_io",
+ "fatfs",
+ "libboard_zynq",
+ "log",
+]
+
 [[package]]
 name = "libcortex_a9"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ec252b099cf67a51ba9daa72b3292db8c21ba1b8"
 dependencies = [
  "bit_field",
  "libregister",
+ "volatile-register",
 ]
 
+[[package]]
+name = "libm"
+version = "0.2.6"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "348108ab3fba42ec82ff6e9564fc4ca0247bdccdc68dd8af9764bbc79c3c8ffb"
+
 [[package]]
 name = "libregister"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ec252b099cf67a51ba9daa72b3292db8c21ba1b8"
 dependencies = [
  "bit_field",
  "vcell",
@@ -231,8 +355,8 @@ dependencies = [
 [[package]]
 name = "libsupport_zynq"
 version = "0.0.0"
-source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ec252b099cf67a51ba9daa72b3292db8c21ba1b8"
 dependencies = [
+ "cc",
  "compiler_builtins",
  "libboard_zynq",
  "libcortex_a9",
@@ -243,19 +367,25 @@ dependencies = [
 
 [[package]]
 name = "linked_list_allocator"
-version = "0.8.4"
+version = "0.8.11"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e70e46c13c0e8374c26cec5752e3347ca1087d9711de8f45aa513a7700efd73d"
+checksum = "822add9edb1860698b79522510da17bef885171f75aa395cff099d770c609c24"
 
 [[package]]
 name = "log"
-version = "0.4.8"
+version = "0.4.17"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "14b6052be84e6b71ab17edffc2eeabf5c2c3ae1fdb464aae35ac50c67a44e1f7"
+checksum = "abb12e687cfb44aa40f41fc3978ef76448f9b6038cad6aef4259d3c095a2382e"
 dependencies = [
- "cfg-if",
+ "cfg-if 1.0.0",
 ]
 
+[[package]]
+name = "log_buffer"
+version = "1.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f033173c9486b7fe97a79c895c0a3483ae395ab6744c985d10078950e2492419"
+
 [[package]]
 name = "managed"
 version = "0.7.2"
@@ -263,56 +393,94 @@ source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "c75de51135344a4f8ed3cfe2720dc27736f7711989703a0b43aadf3753c55577"
 
 [[package]]
-name = "memchr"
-version = "2.3.3"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3728d817d99e5ac407411fa471ff9800a778d88a24685968b36824eaf4bee400"
+name = "nalgebra"
+version = "0.32.6"
+source = "git+https://git.m-labs.hk/M-Labs/nalgebra.git?rev=dd00f9b#dd00f9b46046e0b931d1b470166db02fd29591be"
+dependencies = [
+ "approx",
+ "num-complex",
+ "num-rational",
+ "num-traits",
+ "simba",
+ "typenum",
+]
 
 [[package]]
 name = "nb"
-version = "0.1.2"
+version = "0.1.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b1411551beb3c11dedfb0a90a0fa256b47d28b9ec2cdff34c25a2fa59e45dbdc"
+checksum = "801d31da0513b6ec5214e9bf433a77966320625a37860f910be265be6e18d06f"
+dependencies = [
+ "nb 1.0.0",
+]
+
+[[package]]
+name = "nb"
+version = "1.0.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "546c37ac5d9e56f55e73b677106873d9d9f5190605e41a856503623648488cae"
+
+[[package]]
+name = "num-complex"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "26873667bbbb7c5182d4a37c1add32cdf09f841af72da53318fdb81543c15085"
+dependencies = [
+ "num-traits",
+]
 
 [[package]]
 name = "num-derive"
-version = "0.3.0"
+version = "0.3.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0c8b15b261814f992e33760b1fca9fe8b693d8a65299f20c9901688636cfb746"
+checksum = "876a53fff98e03a936a674b29568b0e605f06b29372c2489ff4de23f1949743d"
 dependencies = [
  "proc-macro2",
  "quote",
  "syn",
 ]
 
+[[package]]
+name = "num-integer"
+version = "0.1.46"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "7969661fd2958a5cb096e56c8e1ad0444ac2bbcd0061bd28660485a44879858f"
+dependencies = [
+ "num-traits",
+]
+
+[[package]]
+name = "num-rational"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d41702bd167c2df5520b384281bc111a4b5efcf7fbc4c9c222c815b07e0a6a6a"
+dependencies = [
+ "autocfg",
+ "num-integer",
+ "num-traits",
+]
+
 [[package]]
 name = "num-traits"
-version = "0.2.12"
+version = "0.2.15"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ac267bcc07f48ee5f8935ab0d24f316fb722d7a1292e2913f0cc196b29ffd611"
+checksum = "578ede34cf02f8924ab9447f50c28075b4d3e5b269972345e7e0372b38c6cdcd"
 dependencies = [
  "autocfg",
+ "libm",
 ]
 
 [[package]]
-name = "pin-project"
-version = "0.4.22"
+name = "paste"
+version = "1.0.15"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "12e3a6cdbfe94a5e4572812a0201f8c0ed98c1c452c7b8563ce2276988ef9c17"
-dependencies = [
- "pin-project-internal",
-]
+checksum = "57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a"
 
 [[package]]
-name = "pin-project-internal"
-version = "0.4.22"
+name = "pin-project-lite"
+version = "0.2.9"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "6a0ffd45cf79d88737d7cc85bfd5d2894bee1139b356e616fe85dc389c61aaf7"
-dependencies = [
- "proc-macro2",
- "quote",
- "syn",
-]
+checksum = "e0a7ae3ac2f1173085d398531c705756c94a4c56843785df85a60c1a0afac116"
 
 [[package]]
 name = "pin-utils"
@@ -320,32 +488,20 @@ version = "0.1.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "8b870d8c151b6f2fb93e84a13146138f05d02ed11c7e7c54f8826aaaf7c9f184"
 
-[[package]]
-name = "proc-macro-hack"
-version = "0.5.16"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "7e0456befd48169b9f13ef0f0ad46d492cf9d2dbb918bcf38e01eed4ce3ec5e4"
-
-[[package]]
-name = "proc-macro-nested"
-version = "0.1.6"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "eba180dafb9038b050a4c280019bbedf9f2467b61e5d892dcad585bb57aadc5a"
-
 [[package]]
 name = "proc-macro2"
-version = "1.0.18"
+version = "1.0.43"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "beae6331a816b1f65d04c45b078fd8e6c93e8071771f41b8163255bbd8d7c8fa"
+checksum = "0a2ca2c61bc9f3d74d2886294ab7b9853abd9c1ad903a3ac7815c58989bb7bab"
 dependencies = [
- "unicode-xid",
+ "unicode-ident",
 ]
 
 [[package]]
 name = "quote"
-version = "1.0.7"
+version = "1.0.21"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "aa563d17ecb180e500da1cfd2b028310ac758de548efdd203e18f283af693f37"
+checksum = "bbe448f377a7d6961e30f5955f9b8d106c3f5e449d493ee1b125c1d43c2b5179"
 dependencies = [
  "proc-macro2",
 ]
@@ -361,27 +517,90 @@ name = "runtime"
 version = "0.1.0"
 dependencies = [
  "async-recursion",
+ "build_zynq",
  "byteorder",
  "core_io",
  "cslice",
+ "dwarf",
  "dyld",
- "fatfs",
+ "embedded-hal",
  "futures",
+ "io",
+ "ksupport",
  "libasync",
+ "libboard_artiq",
  "libboard_zynq",
+ "libc",
+ "libconfig",
  "libcortex_a9",
+ "libregister",
  "libsupport_zynq",
  "log",
+ "log_buffer",
  "num-derive",
  "num-traits",
+ "tar-no-std",
+ "unwind",
+ "vcell",
  "void",
 ]
 
 [[package]]
-name = "smoltcp"
-version = "0.6.0"
+name = "rustc_version"
+version = "0.1.7"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0fe46639fd2ec79eadf8fe719f237a7a0bd4dac5d957f1ca5bbdbc1c3c39e53a"
+checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
+dependencies = [
+ "semver",
+]
+
+[[package]]
+name = "satman"
+version = "0.0.0"
+dependencies = [
+ "build_zynq",
+ "byteorder",
+ "core_io",
+ "crc",
+ "cslice",
+ "embedded-hal",
+ "io",
+ "ksupport",
+ "libasync",
+ "libboard_artiq",
+ "libboard_zynq",
+ "libc",
+ "libconfig",
+ "libcortex_a9",
+ "libregister",
+ "libsupport_zynq",
+ "log",
+ "unwind",
+]
+
+[[package]]
+name = "semver"
+version = "0.1.20"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
+
+[[package]]
+name = "simba"
+version = "0.8.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "50582927ed6f77e4ac020c057f37a268fc6aebc29225050365aacbb9deeeddc4"
+dependencies = [
+ "approx",
+ "num-complex",
+ "num-traits",
+ "paste",
+]
+
+[[package]]
+name = "smoltcp"
+version = "0.7.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "3e4a069bef843d170df47e7c0a8bf8d037f217d9f5b325865acc3e466ffe40d3"
 dependencies = [
  "bitflags",
  "byteorder",
@@ -390,37 +609,52 @@ dependencies = [
 
 [[package]]
 name = "syn"
-version = "1.0.33"
+version = "1.0.101"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e8d5d96e8cbb005d6959f119f773bfaebb5684296108fb32600c00cde305b2cd"
+checksum = "e90cde112c4b9690b8cbe810cba9ddd8bc1d7472e2cae317b69e9438c1cba7d2"
 dependencies = [
  "proc-macro2",
  "quote",
- "unicode-xid",
+ "unicode-ident",
 ]
 
 [[package]]
-name = "szl"
-version = "0.1.0"
+name = "tar-no-std"
+version = "0.1.8"
+source = "git+https://git.m-labs.hk/M-Labs/tar-no-std?rev=2ab6dc5#2ab6dc58e5249c59c4eb03eaf3a119bcdd678d32"
 dependencies = [
- "cstr_core",
- "libboard_zynq",
- "libcortex_a9",
- "libsupport_zynq",
+ "arrayvec",
+ "bitflags",
  "log",
 ]
 
 [[package]]
-name = "unicode-xid"
-version = "0.2.1"
+name = "typenum"
+version = "1.17.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f7fe0bb3479651439c9112f72b6c505038574c9fbb575ed1bf3b797fa39dd564"
+checksum = "42ff0bf0c66b8238c6f3b578df37d0b7848e55df8577b3f74f92a69acceeb825"
+
+[[package]]
+name = "unicode-ident"
+version = "1.0.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "6ceab39d59e4c9499d4e5a8ee0e2735b891bb7308ac83dfb4e80cad195c9f6f3"
+
+[[package]]
+name = "unwind"
+version = "0.0.0"
+dependencies = [
+ "cc",
+ "cfg-if 0.1.10",
+ "compiler_builtins",
+ "libc",
+]
 
 [[package]]
 name = "vcell"
-version = "0.1.2"
+version = "0.1.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "876e32dcadfe563a4289e994f7cb391197f362b6315dc45e8ba4aa6f564a4b3c"
+checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
 
 [[package]]
 name = "void"
@@ -430,9 +664,9 @@ checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
 
 [[package]]
 name = "volatile-register"
-version = "0.2.0"
+version = "0.2.1"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "0d67cb4616d99b940db1d6bd28844ff97108b498a6ca850e5b6191a532063286"
+checksum = "9ee8f19f9d74293faf70901bc20ad067dc1ad390d2cbf1e3f75f721ffee908b6"
 dependencies = [
  "vcell",
 ]

src/Cargo.toml

@@ -1,22 +1,18 @@
 [workspace]
 members = [
+  "libc",
   "libdyld",
-  "libcoreio",
+  "libdwarf",
+  "libio",
+  "libunwind",
+  "libksupport",
   "runtime",
-  "szl"
+  "satman"
 ]
 
-[profile.dev]
-panic = "abort"
-lto = false
-
 [profile.release]
 panic = "abort"
 debug = true
-# Link-Time Optimization:
-# turn off if you get unusable debug symbols.
+codegen-units = 1
+opt-level = 2
 lto = true
-opt-level = 'z'  # Optimize for size.
-
-[patch.crates-io]
-core_io = { path = "./libcoreio" }

src/Makefile

@@ -1,20 +1,41 @@
-VARIANT := simple
+TARGET := zc706
+GWARGS := -V nist_clock
 
-all: ../build/firmware/armv7-none-eabihf/release/szl
+all: runtime
 
-.PHONY: all
+runtime: ../build/runtime.bin
 
+satman: ../build/satman.bin
 
-../build/pl.rs: zc706.py
+.PHONY: all manifests
+
+manifests = libboard_artiq/Cargo.toml libc/Cargo.toml libdyld/Cargo.toml libio/Cargo.toml libksupport/Cargo.toml runtime/Cargo.toml satman/Cargo.toml
+
+$(manifests): %.toml: %.toml.tpl
+	sed s+@@ZYNQ_RS@@+$(ZYNQ_RS)+g $< > $@
+
+manifests: $(manifests)
+
+../build/pl.rs ../build/rustc-cfg ../build/mem.rs: gateware/* 
 	mkdir -p ../build
-	python zc706.py -r ../build/pl.rs -V $(VARIANT)
+	python gateware/$(TARGET).py -r ../build/pl.rs -c ../build/rustc-cfg -m ../build/mem.rs $(GWARGS)
 
-../build/firmware/armv7-none-eabihf/release/runtime: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml libdyld/* libdyld/src/* libcoreio/* libcoreio/src/* libcoreio/src/io/* runtime/* runtime/src/* ../build/pl.rs
-	XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p runtime --target-dir ../build/firmware
+../build/firmware/armv7-none-eabihf/release/runtime: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(manifests) $(shell find . -type f -not -name Cargo.toml -print)
+	cd runtime && \
+	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
+	cargo xbuild --release \
+		--target-dir ../../build/firmware \
+		--no-default-features --features=target_$(TARGET)
 
-../build/szl-payload.bin.lzma: ../build/firmware/armv7-none-eabihf/release/runtime
-	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/szl-payload.bin
-	lzma --keep -f ../build/szl-payload.bin
+../build/runtime.bin: ../build/firmware/armv7-none-eabihf/release/runtime
+	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/runtime ../build/runtime.bin
 
-../build/firmware/armv7-none-eabihf/release/szl: .cargo/* armv7-none-eabihf.json Cargo.lock Cargo.toml szl/* szl/src/* ../build/szl-payload.bin.lzma
-	XBUILD_SYSROOT_PATH=`pwd`/../build/sysroot cargo xbuild --release -p szl --target-dir ../build/firmware
+../build/firmware/armv7-none-eabihf/release/satman: ../build/pl.rs ../build/rustc-cfg ../build/mem.rs $(manifests) $(shell find . -type f -not -name Cargo.toml -print)
+	cd satman && \
+	XBUILD_SYSROOT_PATH=`pwd`/../../build/sysroot \
+	cargo xbuild --release \
+		--target-dir ../../build/firmware \
+		--no-default-features --features=target_$(TARGET)
+
+../build/satman.bin: ../build/firmware/armv7-none-eabihf/release/satman
+	llvm-objcopy -O binary ../build/firmware/armv7-none-eabihf/release/satman ../build/satman.bin

src/armv7-none-eabihf.json

@@ -20,6 +20,8 @@
   "max-atomic-width": 32,
   "os": "none",
   "panic-strategy": "abort",
+  "requires-uwtable": true,
+  "force-unwind-tables": "yes",
   "relocation-model": "static",
   "target-c-int-width": "32",
   "target-endian": "little",

src/gateware/acpki.py

@@ -0,0 +1,272 @@
+from operator import attrgetter
+
+from migen import *
+from migen.genlib.cdc import MultiReg
+from migen_axi.interconnect import axi
+from misoc.interconnect.csr import *
+
+from artiq.gateware import rtio
+
+OUT_BURST_LEN = 10
+IN_BURST_LEN = 4
+
+
+class Engine(Module, AutoCSR):
+    def __init__(self, bus, user):
+        self.addr_base = CSRStorage(32)
+        self.trig_count = CSRStatus(32)
+        self.write_count = CSRStatus(32)
+
+        self.trigger_stb = Signal()
+
+        # Dout : Data received from CPU, output by DMA module
+        # Din : Data driven into DMA module, written into CPU
+        # When stb assert, index shows word being read/written, dout/din holds
+        # data
+        #
+        # Cycle:
+        # trigger_stb pulsed at start
+        # Then out_burst_len words are strobed out of dout
+        # Then, when din_ready is high, in_burst_len words are strobed in to din
+        self.dout_stb = Signal()
+        self.din_stb = Signal()
+        self.dout_index = Signal(max=16)
+        self.din_index = Signal(max=16)
+        self.din_ready = Signal()
+        self.dout = Signal(64)
+        self.din = Signal(64)
+
+        ###
+
+        self.sync += If(self.trigger_stb, self.trig_count.status.eq(self.trig_count.status+1))
+
+        self.comb += [
+            user.aruser.eq(0x1f),
+            user.awuser.eq(0x1f)
+        ]
+
+        ar, aw, w, r, b = attrgetter("ar", "aw", "w", "r", "b")(bus)
+
+        ### Read
+        self.comb += [
+            ar.addr.eq(self.addr_base.storage),
+            self.dout.eq(r.data),
+            r.ready.eq(1),
+            ar.burst.eq(axi.Burst.incr.value),
+            ar.len.eq(OUT_BURST_LEN-1), # Number of transfers in burst (0->1 transfer, 1->2 transfers...)
+            ar.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
+            ar.cache.eq(0xf),
+        ]
+
+        # read control
+        self.submodules.read_fsm = read_fsm = FSM(reset_state="IDLE")
+        read_fsm.act("IDLE",
+            If(self.trigger_stb,
+                ar.valid.eq(1),
+                If(ar.ready,
+                    NextState("READ")
+                ).Else(
+                    NextState("READ_START")
+                )
+            )
+        )
+        read_fsm.act("READ_START",
+            ar.valid.eq(1),
+            If(ar.ready,
+                NextState("READ"),
+            )
+        )
+        read_fsm.act("READ",
+            ar.valid.eq(0),
+            If(r.last & r.valid,
+                NextState("IDLE")
+            )
+        )
+
+        self.sync += [
+            If(read_fsm.ongoing("IDLE"),
+                self.dout_index.eq(0)
+            ).Else(If(r.valid & read_fsm.ongoing("READ"),
+                    self.dout_index.eq(self.dout_index+1)
+                )
+            )
+        ]
+
+        self.comb += self.dout_stb.eq(r.valid & r.ready)
+
+        ### Write
+        self.comb += [
+            w.data.eq(self.din),
+            aw.addr.eq(self.addr_base.storage+96),
+            w.strb.eq(0xff),
+            aw.burst.eq(axi.Burst.incr.value),
+            aw.len.eq(IN_BURST_LEN-1), # Number of transfers in burst minus 1
+            aw.size.eq(3), # Width of burst: 3 = 8 bytes = 64 bits
+            aw.cache.eq(0xf),
+            b.ready.eq(1),
+        ]
+
+        # write control
+        self.submodules.write_fsm = write_fsm = FSM(reset_state="IDLE")
+        write_fsm.act("IDLE",
+            w.valid.eq(0),
+            aw.valid.eq(0),
+            If(self.trigger_stb,
+                aw.valid.eq(1),
+                If(aw.ready, # assumes aw.ready is not randomly deasserted
+                    NextState("DATA_WAIT")
+                ).Else(
+                    NextState("AW_READY_WAIT")
+                )
+            )
+        )
+        write_fsm.act("AW_READY_WAIT",
+            aw.valid.eq(1),
+            If(aw.ready,
+                NextState("DATA_WAIT"),
+            )
+        )
+        write_fsm.act("DATA_WAIT",
+            aw.valid.eq(0),
+            If(self.din_ready,
+                w.valid.eq(1),
+                NextState("WRITE")
+            )
+        )
+        write_fsm.act("WRITE",
+            w.valid.eq(1),
+            If(w.ready & w.last,
+                NextState("IDLE")
+            )
+        )
+
+        self.sync += If(w.ready & w.valid, self.write_count.status.eq(self.write_count.status+1))
+
+        self.sync += [
+            If(write_fsm.ongoing("IDLE"),
+                self.din_index.eq(0)
+            ),
+            If(w.ready & w.valid, self.din_index.eq(self.din_index+1))
+        ]
+
+        self.comb += [
+            w.last.eq(0),
+            If(self.din_index==aw.len, w.last.eq(1))
+        ]
+
+        self.comb += self.din_stb.eq(w.valid & w.ready)
+
+
+
+class KernelInitiator(Module, AutoCSR):
+    def __init__(self, tsc, bus, user, evento):
+        # Core is disabled upon reset to avoid spurious triggering if evento toggles from e.g. boot code.
+        self.enable = CSRStorage()
+
+        self.counter = CSRStatus(64)
+        self.counter_update = CSR()
+        self.o_status = CSRStatus(3)
+        self.i_status = CSRStatus(4)
+
+        self.submodules.engine = Engine(bus, user)
+        self.cri = rtio.cri.Interface()
+
+        ###
+
+        evento_stb = Signal()
+        evento_latched = Signal()
+        evento_latched_d = Signal()
+        self.specials += MultiReg(evento, evento_latched)
+        self.sync += evento_latched_d.eq(evento_latched)
+        self.comb += self.engine.trigger_stb.eq(self.enable.storage & (evento_latched != evento_latched_d))
+
+        cri = self.cri
+
+        cmd = Signal(8)
+        cmd_write = Signal()
+        cmd_read = Signal()
+        self.comb += [
+            cmd_write.eq(cmd == 0),
+            cmd_read.eq(cmd == 1)
+        ]
+
+        out_len = Signal(8)
+        dout_cases = {}
+        dout_cases[0] = [
+            cmd.eq(self.engine.dout[:8]),
+            out_len.eq(self.engine.dout[8:16]),
+            cri.chan_sel.eq(self.engine.dout[40:]),
+            cri.o_address.eq(self.engine.dout[32:40])
+        ]
+        for i in range(8):
+            target = cri.o_data[i*64:(i+1)*64]
+            dout_cases[0] += [If(i >= self.engine.dout[8:16], target.eq(0))]
+
+        dout_cases[1] = [
+            cri.o_timestamp.eq(self.engine.dout),
+            cri.i_timeout.eq(self.engine.dout)
+        ]
+        for i in range(8):
+            target = cri.o_data[i*64:(i+1)*64]
+            dout_cases[i+2] = [target.eq(self.engine.dout)]
+
+        self.sync += [
+            cri.cmd.eq(rtio.cri.commands["nop"]),
+            If(self.engine.dout_stb,
+                Case(self.engine.dout_index, dout_cases),
+                If(self.engine.dout_index == out_len + 2,
+                    If(cmd_write, cri.cmd.eq(rtio.cri.commands["write"])),
+                    If(cmd_read, cri.cmd.eq(rtio.cri.commands["read"]))
+                )
+            )
+        ]
+
+        # If input event, wait for response before allow input data to be
+        # sampled
+        # TODO: If output, wait for wait flag clear
+        RTIO_I_STATUS_WAIT_STATUS = 4
+        RTIO_O_STATUS_WAIT = 1
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            If(self.engine.trigger_stb, NextState("WAIT_OUT_CYCLE"))
+        )
+        fsm.act("WAIT_OUT_CYCLE",
+            self.engine.din_ready.eq(0),
+            If(self.engine.dout_stb & cmd_write & (self.engine.dout_index == out_len + 2),
+               NextState("WAIT_READY")
+            ),
+            # for some reason read requires some delay until the next state
+            If(self.engine.dout_stb & cmd_read & (self.engine.dout_index == out_len + 3),
+                NextState("WAIT_READY")
+            )
+        )
+        fsm.act("WAIT_READY",
+            If(cmd_read & (cri.i_status & RTIO_I_STATUS_WAIT_STATUS == 0) \
+                | cmd_write & ~(cri.o_status & RTIO_O_STATUS_WAIT),
+                self.engine.din_ready.eq(1),
+                NextState("IDLE")
+            )
+        )
+
+        din_cases_cmdwrite = {
+            0: [self.engine.din.eq((1<<16) | cri.o_status)],
+            1: [self.engine.din.eq(0)],
+        }
+        din_cases_cmdread = {
+            0: [self.engine.din[:32].eq((1<<16) | cri.i_status), self.engine.din[32:].eq(cri.i_data)],
+            1: [self.engine.din.eq(cri.i_timestamp)]
+        }
+
+        self.comb += [
+            If(cmd_read, Case(self.engine.din_index, din_cases_cmdread)),
+            If(cmd_write, Case(self.engine.din_index, din_cases_cmdwrite)),
+        ]
+
+        # CRI CSRs
+        self.sync += If(self.counter_update.re, self.counter.status.eq(tsc.full_ts_cri))
+        self.comb += [
+            self.o_status.status.eq(self.cri.o_status),
+            self.i_status.status.eq(self.cri.i_status),
+        ]

src/gateware/analyzer.py

@@ -0,0 +1,121 @@
+from migen import *
+
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+from migen_axi.interconnect import axi
+
+from artiq.gateware.rtio.analyzer import message_len, MessageEncoder
+
+import endianness
+
+
+class AXIDMAWriter(Module, AutoCSR):
+    def __init__(self, membus, max_outstanding_requests):
+        aw = len(membus.aw.addr)
+        dw = len(membus.w.data)
+        assert message_len % dw == 0
+        burst_length = message_len//dw
+        alignment_bits = log2_int(message_len//8)
+
+        self.reset = CSR()  # only apply when shut down
+        # All numbers in bytes
+        self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
+        self.last_address = CSRStorage(aw, alignment_bits=alignment_bits)
+        self.byte_count = CSRStatus(32)  # only read when shut down
+        self.bus_error = CSRStatus()
+
+        self.make_request = Signal()
+        self.sink = stream.Endpoint([("data", dw)])
+
+        # # #
+
+        outstanding_requests = Signal(max=max_outstanding_requests+1)
+        current_address = Signal(aw - alignment_bits)
+        self.comb += [
+            membus.aw.addr.eq(Cat(C(0, alignment_bits), current_address)),
+            membus.aw.id.eq(0),                   # Same ID for all transactions to forbid reordering.
+            membus.aw.burst.eq(axi.Burst.incr.value),
+            membus.aw.len.eq(burst_length-1),     # Number of transfers in burst (0->1 transfer, 1->2 transfers...).
+            membus.aw.size.eq(log2_int(dw//8)),   # Width of burst: 3 = 8 bytes = 64 bits.
+            membus.aw.cache.eq(0xf),
+            membus.aw.valid.eq(outstanding_requests != 0),
+        ]
+        self.sync += [
+            outstanding_requests.eq(outstanding_requests + self.make_request - (membus.aw.valid & membus.aw.ready)),
+
+            If(self.reset.re,
+                current_address.eq(self.base_address.storage)),
+            If(membus.aw.valid & membus.aw.ready,
+                If(current_address == self.last_address.storage,
+                    current_address.eq(self.base_address.storage)
+                ).Else(
+                    current_address.eq(current_address + 1)
+                )
+            )
+        ]
+
+        self.comb += [
+            membus.w.id.eq(0),
+            membus.w.valid.eq(self.sink.stb),
+            self.sink.ack.eq(membus.w.ready),
+            membus.w.data.eq(endianness.convert_signal(self.sink.data)),
+            membus.w.strb.eq(2**(dw//8)-1),
+        ]
+        beat_count = Signal(max=burst_length)
+        self.sync += [
+            If(membus.w.valid & membus.w.ready,
+                membus.w.last.eq(0),
+                If(membus.w.last,
+                    beat_count.eq(0)
+                ).Else(
+                    If(beat_count == burst_length-2, membus.w.last.eq(1)),
+                    beat_count.eq(beat_count + 1)
+                )
+            )
+        ]
+
+        message_count = Signal(32 - log2_int(message_len//8))
+        self.comb += self.byte_count.status.eq(
+            message_count << log2_int(message_len//8))
+        self.sync += [
+            If(self.reset.re, message_count.eq(0)),
+            If(membus.w.valid & membus.w.ready & membus.w.last, message_count.eq(message_count + 1))
+        ]
+
+        self.comb += membus.b.ready.eq(1)
+        self.sync += [
+            If(self.reset.re, self.bus_error.status.eq(0)),
+            If(membus.b.valid & membus.b.ready & (membus.b.resp != axi.Response.okay),
+                self.bus_error.status.eq(1))
+        ]
+
+
+class Analyzer(Module, AutoCSR):
+    def __init__(self, tsc, cri, membus, fifo_depth=128):
+        # shutdown procedure: set enable to 0, wait until busy=0
+        self.enable = CSRStorage()
+        self.busy = CSRStatus()
+
+        self.submodules.message_encoder = MessageEncoder(
+            tsc, cri, self.enable.storage)
+        self.submodules.fifo = stream.SyncFIFO(
+            [("data", message_len)], fifo_depth, True)
+        self.submodules.converter = stream.Converter(
+            message_len, len(membus.w.data), reverse=True)
+        self.submodules.dma = AXIDMAWriter(membus, max_outstanding_requests=fifo_depth)
+
+        enable_r = Signal()
+        self.sync += [
+            enable_r.eq(self.enable.storage),
+            If(self.enable.storage & ~enable_r,
+                self.busy.status.eq(1)),
+            If(self.dma.sink.stb & self.dma.sink.ack & self.dma.sink.eop,
+                self.busy.status.eq(0))
+        ]
+
+        self.comb += [
+            self.message_encoder.source.connect(self.fifo.sink),
+            self.fifo.source.connect(self.converter.sink),
+            self.converter.source.connect(self.dma.sink),
+            self.dma.make_request.eq(self.fifo.sink.stb & self.fifo.sink.ack)
+        ]

src/gateware/config.py

@@ -0,0 +1,16 @@
+from misoc.integration import cpu_interface
+
+def write_csr_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_csr_rust(
+            soc.get_csr_regions(), soc.get_csr_groups(), soc.get_constants()))
+
+def write_mem_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_mem_rust(
+            soc.get_memory_regions(), soc.get_memory_groups(), None))
+
+def write_rustc_cfg_file(soc, filename):
+    with open(filename, "w") as f:
+        f.write(cpu_interface.get_rust_cfg(
+            soc.get_csr_regions(), soc.get_constants()))

src/gateware/ddmtd.py

@@ -0,0 +1,119 @@
+from migen import *
+from migen.genlib.cdc import PulseSynchronizer, MultiReg
+from misoc.interconnect.csr import *
+
+
+class DDMTDSampler(Module):
+    def __init__(self, cd_ref, main_clk_se):
+        self.ref_beating = Signal()
+        self.main_beating = Signal()
+
+        # # #
+
+        ref_clk = Signal()
+        self.specials +=[
+            # ISERDESE2 can only be driven from fabric via IDELAYE2 (see UG471)
+            Instance("IDELAYE2",
+                    p_DELAY_SRC="DATAIN",
+                    p_HIGH_PERFORMANCE_MODE="TRUE",
+                    p_REFCLK_FREQUENCY=208.3,   # REFCLK frequency from IDELAYCTRL
+                    p_IDELAY_VALUE=0,
+
+                    i_DATAIN=cd_ref.clk,
+
+                    o_DATAOUT=ref_clk
+            ),
+            Instance("ISERDESE2",
+                    p_IOBDELAY="IFD",   # use DDLY as input
+                    p_DATA_RATE="SDR",
+                    p_DATA_WIDTH=2,     # min is 2
+                    p_NUM_CE=1,
+
+                    i_DDLY=ref_clk,
+                    i_CE1=1,
+                    i_CLK=ClockSignal("helper"),
+                    i_CLKDIV=ClockSignal("helper"),
+
+                    o_Q1=self.ref_beating
+            ),
+            Instance("ISERDESE2",
+                    p_DATA_RATE="SDR",
+                    p_DATA_WIDTH=2,     # min is 2
+                    p_NUM_CE=1,
+
+                    i_D=main_clk_se,
+                    i_CE1=1,
+                    i_CLK=ClockSignal("helper"),
+                    i_CLKDIV=ClockSignal("helper"),
+
+                    o_Q1=self.main_beating,
+            ),
+        ]
+
+
+class DDMTDDeglitcherMedianEdge(Module):
+    def __init__(self, counter, input_signal, stable_0_period=100, stable_1_period=100):
+        self.tag = Signal(len(counter))
+        self.detect = Signal()
+
+        stable_0_counter = Signal(reset=stable_0_period - 1, max=stable_0_period)
+        stable_1_counter = Signal(reset=stable_1_period - 1, max=stable_1_period)
+
+        # # #
+
+        # Based on CERN's median edge deglitcher FSM
+        # https://white-rabbit.web.cern.ch/documents/Precise_time_and_frequency_transfer_in_a_White_Rabbit_network.pdf (p.72)
+        fsm = ClockDomainsRenamer("helper")(FSM(reset_state="WAIT_STABLE_0"))
+        self.submodules += fsm
+
+        fsm.act("WAIT_STABLE_0",
+            If(stable_0_counter != 0,
+                NextValue(stable_0_counter, stable_0_counter - 1)
+            ).Else(
+                NextValue(stable_0_counter, stable_0_period - 1),
+                NextState("WAIT_EDGE")
+            ),
+            If(input_signal,
+                NextValue(stable_0_counter, stable_0_period - 1)
+            ),
+        )
+        fsm.act("WAIT_EDGE",
+            If(input_signal,
+                NextValue(self.tag, counter),
+                NextState("GOT_EDGE")
+            )
+        )
+        fsm.act("GOT_EDGE",
+            If(stable_1_counter != 0,
+                NextValue(stable_1_counter, stable_1_counter - 1)
+            ).Else(
+                NextValue(stable_1_counter, stable_1_period - 1),
+                self.detect.eq(1),
+                NextState("WAIT_STABLE_0")
+            ),
+            If(~input_signal,
+                NextValue(self.tag, self.tag + 1),
+                NextValue(stable_1_counter, stable_1_period - 1)
+            ),
+        )
+        
+
+class DDMTD(Module):
+    def __init__(self, counter, input_signal):
+
+        # in helper clock domain
+        self.h_tag = Signal(len(counter))
+        self.h_tag_update = Signal()
+
+        # # #
+
+        deglitcher = DDMTDDeglitcherMedianEdge(counter, input_signal)
+        self.submodules += deglitcher
+
+        self.sync.helper += [
+            self.h_tag_update.eq(0),
+            If(deglitcher.detect,
+                self.h_tag_update.eq(1),
+                self.h_tag.eq(deglitcher.tag)
+               )
+        ]

src/gateware/dma.py

@@ -0,0 +1,157 @@
+from migen import *
+from migen.genlib.fsm import FSM
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+from migen_axi.interconnect import axi
+
+from artiq.gateware.rtio.dma import RawSlicer, RecordConverter, RecordSlicer, TimeOffset, CRIMaster
+
+import endianness
+
+
+AXI_BURST_LEN = 16
+
+
+class AXIReader(Module, AutoCSR):
+    def __init__(self, membus):
+        aw = len(membus.ar.addr)
+        dw = len(membus.r.data)
+        alignment_bits = log2_int(AXI_BURST_LEN*dw//8)
+        self.sink = stream.Endpoint([("address", aw - alignment_bits)])
+        self.source = stream.Endpoint([("data", dw)])
+
+        self.bus_error = CSRStatus()
+
+        # # #
+
+        eop_pending = Signal()
+        self.sync += [
+            If(self.sink.stb & self.sink.ack & self.sink.eop, eop_pending.eq(1)),
+            If(self.source.stb & self.source.ack & self.source.eop, eop_pending.eq(0)),
+        ]
+
+        self.comb += [
+            membus.ar.addr.eq(Cat(C(0, alignment_bits), self.sink.address)),
+            membus.ar.id.eq(0),                   # Same ID for all transactions to forbid reordering.
+            membus.ar.burst.eq(axi.Burst.incr.value),
+            membus.ar.len.eq(AXI_BURST_LEN-1),    # Number of transfers in burst (0->1 transfer, 1->2 transfers...).
+            membus.ar.size.eq(log2_int(dw//8)),   # Width of burst: 3 = 8 bytes = 64 bits.
+            membus.ar.cache.eq(0xf),
+            membus.ar.valid.eq(self.sink.stb & ~eop_pending),
+            self.sink.ack.eq(membus.ar.ready & ~eop_pending)
+        ]
+
+        # UG585: "Large slave interface read acceptance capability in the range of 14 to 70 commands"
+        inflight_cnt = Signal(max=128)
+        request_done = Signal()
+        reply_done = Signal()
+        self.comb += [
+            request_done.eq(membus.ar.valid & membus.ar.ready),
+            reply_done.eq(membus.r.valid & membus.r.ready & membus.r.last)
+        ]
+        self.sync += inflight_cnt.eq(inflight_cnt + request_done - reply_done)
+
+        self.comb += [
+            self.source.stb.eq(membus.r.valid),
+            membus.r.ready.eq(self.source.ack),
+            self.source.data.eq(endianness.convert_signal(membus.r.data)),
+            # Note that when eop_pending=1, no new transactions are made and inflight_cnt is no longer incremented
+            self.source.eop.eq(eop_pending & membus.r.last & (inflight_cnt == 1))
+        ]
+
+        stopped = Signal(reset=1)
+        self.sync += [
+            If(self.source.stb & self.source.ack & self.source.eop, stopped.eq(1)),
+            If(self.sink.stb & self.sink.ack, stopped.eq(0)),
+            If(stopped & (self.sink.stb & self.sink.ack),
+                # reset bus error status on new run
+                self.bus_error.status.eq(0)),
+            If(membus.r.valid & membus.r.valid & (membus.r.resp != axi.Response.okay),
+                self.bus_error.status.eq(1))
+        ]
+
+
+class DMAReader(Module, AutoCSR):
+    def __init__(self, membus, enable):
+        aw = len(membus.ar.addr)
+        alignment_bits = log2_int(AXI_BURST_LEN*len(membus.r.data)//8)
+
+        self.submodules.wb_reader = AXIReader(membus)
+        self.source = self.wb_reader.source
+
+        # All numbers in bytes
+        self.base_address = CSRStorage(aw, alignment_bits=alignment_bits)
+
+        # # #
+
+        enable_r = Signal()
+        address = self.wb_reader.sink
+        assert len(address.address) == len(self.base_address.storage)
+        self.sync += [
+            enable_r.eq(enable),
+            If(enable & ~enable_r,
+                address.address.eq(self.base_address.storage),
+                address.eop.eq(0),
+                address.stb.eq(1),
+            ),
+            If(address.stb & address.ack,
+                If(address.eop,
+                    address.stb.eq(0)
+                ).Else(
+                    address.address.eq(address.address + 1),
+                    If(~enable, address.eop.eq(1))
+                )
+            )
+        ]
+
+
+class DMA(Module):
+    def __init__(self, membus):
+        self.enable = CSR()
+
+        flow_enable = Signal()
+        self.submodules.dma = DMAReader(membus, flow_enable)
+        self.submodules.slicer = RecordSlicer(len(membus.r.data))
+        self.submodules.time_offset = TimeOffset()
+        self.submodules.cri_master = CRIMaster()
+        self.cri = self.cri_master.cri
+
+        self.comb += [
+            self.dma.source.connect(self.slicer.sink),
+            self.slicer.source.connect(self.time_offset.sink),
+            self.time_offset.source.connect(self.cri_master.sink)
+        ]
+
+        fsm = FSM(reset_state="IDLE")
+        self.submodules += fsm
+
+        fsm.act("IDLE",
+            If(self.enable.re, NextState("FLOWING"))
+        )
+        fsm.act("FLOWING",
+            self.enable.w.eq(1),
+            flow_enable.eq(1),
+            If(self.slicer.end_marker_found,
+                NextState("FLUSH")
+            )
+        )
+        fsm.act("FLUSH",
+            self.enable.w.eq(1),
+            self.slicer.flush.eq(1),
+            NextState("WAIT_EOP")
+        )
+        fsm.act("WAIT_EOP",
+            self.enable.w.eq(1),
+            If(self.cri_master.sink.stb & self.cri_master.sink.ack & self.cri_master.sink.eop,
+                NextState("WAIT_CRI_MASTER")
+            )
+        )
+        fsm.act("WAIT_CRI_MASTER",
+            self.enable.w.eq(1),
+            If(~self.cri_master.busy, NextState("IDLE"))
+        )
+
+    def get_csrs(self):
+        return ([self.enable] +
+                self.dma.get_csrs() + self.time_offset.get_csrs() +
+                self.cri_master.get_csrs())

src/gateware/drtio_aux_controller.py

@@ -0,0 +1,85 @@
+"""Auxiliary controller, common to satellite and master"""
+
+from artiq.gateware.drtio.aux_controller import (max_packet, aux_buffer_count,
+    Transmitter, Receiver)
+from migen.fhdl.simplify import FullMemoryWE
+from misoc.interconnect.csr import *
+from migen_axi.interconnect.sram import SRAM
+from migen_axi.interconnect import axi
+
+
+class _DRTIOAuxControllerBase(Module):
+    def __init__(self, link_layer):
+        self.bus = axi.Interface()
+        self.submodules.transmitter = Transmitter(link_layer, len(self.bus.w.data))
+        self.submodules.receiver = Receiver(link_layer, len(self.bus.w.data))
+
+    def get_csrs(self):
+        return self.transmitter.get_csrs() + self.receiver.get_csrs()
+
+
+# TODO: FullMemoryWE should be applied by migen.build
+@FullMemoryWE()
+class DRTIOAuxControllerAxi(_DRTIOAuxControllerBase):
+    def __init__(self, link_layer):
+        _DRTIOAuxControllerBase.__init__(self, link_layer)
+
+        tx_sdram_if = SRAM(self.transmitter.mem, read_only=False)
+        rx_sdram_if = SRAM(self.receiver.mem, read_only=True)
+        aw_decoder = axi.AddressDecoder(self.bus.aw,
+            [(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 0, tx_sdram_if.bus.aw),
+             (lambda a: a[log2_int(max_packet*aux_buffer_count)] == 1, rx_sdram_if.bus.aw)],
+            register=True)
+        ar_decoder = axi.AddressDecoder(self.bus.ar,
+            [(lambda a: a[log2_int(max_packet*aux_buffer_count)] == 0, tx_sdram_if.bus.ar),
+             (lambda a: a[log2_int(max_packet*aux_buffer_count)] == 1, rx_sdram_if.bus.ar)],
+            register=True)
+        # unlike wb, axi address decoder only connects ar/aw lanes,
+        # the rest must also be connected!
+        # not quite unlike an address decoder itself.
+
+        # connect bus.b with tx.b
+        self.comb += [tx_sdram_if.bus.b.ready.eq(self.bus.b.ready),
+                      self.bus.b.id.eq(tx_sdram_if.bus.b.id),
+                      self.bus.b.resp.eq(tx_sdram_if.bus.b.resp),
+                      self.bus.b.valid.eq(tx_sdram_if.bus.b.valid)]
+        # connect bus.w with tx.w
+        # no worries about w.valid and slave sel here, only tx will be written to
+        self.comb += [tx_sdram_if.bus.w.id.eq(self.bus.w.id),
+                      tx_sdram_if.bus.w.data.eq(self.bus.w.data),
+                      tx_sdram_if.bus.w.strb.eq(self.bus.w.strb),
+                      tx_sdram_if.bus.w.last.eq(self.bus.w.last),
+                      tx_sdram_if.bus.w.valid.eq(self.bus.w.valid),
+                      self.bus.w.ready.eq(tx_sdram_if.bus.w.ready)]
+        # connect bus.r with rx.r and tx.r w/o data
+        self.comb += [self.bus.r.id.eq(rx_sdram_if.bus.r.id | tx_sdram_if.bus.r.id),
+                #self.bus.r.data.eq(rx_sdram_if.bus.r.data | tx_sdram_if.bus.r.data),
+                self.bus.r.resp.eq(rx_sdram_if.bus.r.resp | tx_sdram_if.bus.r.resp),
+                self.bus.r.last.eq(rx_sdram_if.bus.r.last | tx_sdram_if.bus.r.last),
+                self.bus.r.valid.eq(rx_sdram_if.bus.r.valid | tx_sdram_if.bus.r.valid),
+                rx_sdram_if.bus.r.ready.eq(self.bus.r.ready),
+                tx_sdram_if.bus.r.ready.eq(self.bus.r.ready)]
+        # connect read data after being masked
+        masked = [Replicate(rx_sdram_if.bus.r.valid,
+                            len(self.bus.r.data)
+                            ) & rx_sdram_if.bus.r.data,
+                 Replicate(tx_sdram_if.bus.r.valid,
+                            len(self.bus.r.data)
+                            ) & tx_sdram_if.bus.r.data]
+        self.comb += self.bus.r.data.eq(reduce(or_, masked))
+
+        self.submodules += tx_sdram_if, rx_sdram_if, aw_decoder, ar_decoder
+
+
+@FullMemoryWE()
+class DRTIOAuxControllerBare(_DRTIOAuxControllerBase):
+    # Barebones version of the AuxController. No SRAM, no decoders.
+    # add memories manually from tx and rx in target code.
+    def get_tx_port(self):
+        return self.transmitter.mem.get_port(write_capable=True)
+
+    def get_rx_port(self):
+        return self.receiver.mem.get_port(write_capable=False)
+
+    def get_mem_size(self):
+        return max_packet*aux_buffer_count

src/gateware/ebaz4205.py

@@ -0,0 +1,307 @@
+#!/usr/bin/env python
+
+import argparse
+
+import analyzer
+import dma
+from artiq.gateware import rtio
+from artiq.gateware.rtio.phy import spi2, ttl_simple
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
+from migen import *
+from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
+from migen.build.platforms import ebaz4205
+from migen_axi.integration.soc_core import SoCCore
+from misoc.interconnect.csr import *
+
+_ps = [
+    (
+        "ps",
+        0,
+        Subsignal("clk", Pins("E7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
+        Subsignal("por_b", Pins("C7"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
+        Subsignal("srst_b", Pins("B10"), IOStandard("LVCMOS18"), Misc("SLEW=FAST")),
+    )
+]
+
+_ddr = [
+    (
+        "ddr",
+        0,
+        Subsignal(
+            "a",
+            Pins("N2 K2 M3 K3 M4 L1 L4 K4 K1 J4 F5 G4 E4 D4 F4"),
+            IOStandard("SSTL15"),
+        ),
+        Subsignal("ba", Pins("L5 R4 J5"), IOStandard("SSTL15")),
+        Subsignal("cas_n", Pins("P5"), IOStandard("SSTL15")),
+        Subsignal("cke", Pins("N3"), IOStandard("SSTL15")),
+        Subsignal("cs_n", Pins("N1"), IOStandard("SSTL15")),
+        Subsignal("ck_n", Pins("M2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
+        Subsignal("ck_p", Pins("L2"), IOStandard("DIFF_SSTL15"), Misc("SLEW=FAST")),
+        # Pins "T1 Y1" not connected
+        Subsignal("dm", Pins("A1 F1"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal(
+            "dq",
+            Pins("C3 B3 A2 A4 D3 D1 C1 E1 E2 E3 G3 H3 J3 H2 H1 J1"),
+            # Pins "P1 P3 R3 R1 T4 U4 U2 U3 V1 Y3 W1 Y4 Y2 W3 V2 V3" not connected
+            IOStandard("SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal(
+            "dqs_n",
+            Pins("B2 F2"),  # Pins "T2 W4" not connected
+            IOStandard("DIFF_SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal(
+            "dqs_p",
+            Pins("C2 G2"),  # Pins "R2 W5" not connected
+            IOStandard("DIFF_SSTL15_T_DCI"),
+            Misc("SLEW=FAST"),
+        ),
+        Subsignal("vrn", Pins("G5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal("vrp", Pins("H5"), IOStandard("SSTL15_T_DCI"), Misc("SLEW=FAST")),
+        Subsignal("drst_n", Pins("B4"), IOStandard("SSTL15"), Misc("SLEW=FAST")),
+        Subsignal("odt", Pins("N5"), IOStandard("SSTL15")),
+        Subsignal("ras_n", Pins("P4"), IOStandard("SSTL15")),
+        Subsignal("we_n", Pins("M5"), IOStandard("SSTL15")),
+    )
+]
+
+# Connector J3
+_i2c = [
+    (
+        "i2c",
+        0,
+        Subsignal("scl", Pins("U12"), IOStandard("LVCMOS33")),
+        Subsignal("sda", Pins("V13"), IOStandard("LVCMOS33")),
+    )
+]
+
+_spi = [
+    (
+        "spi",
+        0,
+        Subsignal("clk", Pins("V20")),
+        Subsignal("mosi", Pins("U20")),
+        Subsignal("cs_n", Pins("P19")),
+        IOStandard("LVCMOS33"),
+    )
+]
+
+
+# Connector DATA1
+def _create_ttl():
+    _ttl = []
+
+    for idx, elem in enumerate([x for x in range(5, 21) if x not in (10, 12)]):
+        _ttl.append(
+            ("ttl", idx, Pins("DATA1:DATA1-{}".format(elem)), IOStandard("LVCMOS33")),
+        )
+    return _ttl
+
+
+class EBAZ4205(SoCCore):
+    def __init__(self, rtio_clk=125e6, acpki=False):
+        self.acpki = acpki
+
+        platform = ebaz4205.Platform()
+        platform.toolchain.bitstream_commands.extend(
+            [
+                "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+            ]
+        )
+        platform.add_extension(_ps)
+        platform.add_extension(_ddr)
+        platform.add_extension(_i2c)
+        platform.add_extension(_spi)
+        platform.add_extension(_create_ttl())
+
+        gmii = platform.request("gmii")
+        platform.add_period_constraint(gmii.rx_clk, 10)
+        platform.add_period_constraint(gmii.tx_clk, 10)
+        platform.add_platform_command(
+            "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
+        )
+
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)
+        fix_serdes_timing_path(platform)
+        self.config["RTIO_FREQUENCY"] = str(rtio_clk / 1e6)
+        platform.add_period_constraint(self.ps7.cd_sys.clk, 10)
+
+        self.comb += [
+            self.ps7.enet0.enet.gmii.tx_clk.eq(gmii.tx_clk),
+            self.ps7.enet0.enet.gmii.rx_clk.eq(gmii.rx_clk),
+        ]
+        self.clock_domains.cd_eth_rx = ClockDomain(reset_less=False)
+        self.clock_domains.cd_eth_tx = ClockDomain(reset_less=False)
+        self.comb += [
+            ClockSignal("eth_rx").eq(gmii.rx_clk),
+            ClockSignal("eth_tx").eq(gmii.tx_clk),
+        ]
+        self.sync.eth_tx += [
+            gmii.txd.eq(self.ps7.enet0.enet.gmii.txd),
+            gmii.tx_en.eq(self.ps7.enet0.enet.gmii.tx_en),
+        ]
+        self.sync.eth_rx += [
+            self.ps7.enet0.enet.gmii.rxd.eq(gmii.rxd),
+            self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
+        ]
+
+        # MDIO
+        mdio = platform.request("mdio")
+        self.comb += mdio.mdc.eq(self.ps7.enet0.enet.mdio.mdc)
+        self.specials += Instance(
+            "IOBUF",
+            i_I=self.ps7.enet0.enet.mdio.o,
+            io_IO=mdio.mdio,
+            o_O=self.ps7.enet0.enet.mdio.i,
+            i_T=~self.ps7.enet0.enet.mdio.t_n,
+        )
+
+        # I2C
+        i2c = self.platform.request("i2c")
+        self.specials += [
+            # SCL
+            Instance(
+                "IOBUF",
+                i_I=self.ps7.i2c0.scl.o,
+                io_IO=i2c.scl,
+                o_O=self.ps7.i2c0.scl.i,
+                i_T=~self.ps7.i2c0.scl.t_n,
+            ),
+            # SDA
+            Instance(
+                "IOBUF",
+                i_I=self.ps7.i2c0.sda.o,
+                io_IO=i2c.sda,
+                o_O=self.ps7.i2c0.sda.i,
+                i_T=~self.ps7.i2c0.sda.t_n,
+            ),
+        ]
+
+        self.rtio_channels = []
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        for i in range(14):
+            print("TTL at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            ttl = self.platform.request("ttl", i)
+            phy = ttl_simple.InOut(ttl)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        print("SPI at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+        spi_phy = spi2.SPIMaster(platform.request("spi"))
+        self.submodules += spi_phy
+        self.rtio_channels.append(rtio.Channel.from_phy(spi_phy, ififo_depth=4))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, self.rtio_channels)
+        self.csr_devices.append("rtio_core")
+        if self.acpki:
+            import acpki
+
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(
+                self.rtio_tsc,
+                bus=self.ps7.s_axi_acp,
+                user=self.ps7.s_axi_acp_user,
+                evento=self.ps7.event.o,
+            )
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri],
+            enable_routing=True,
+        )
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(
+            self.rtio_tsc, self.rtio_core.cri, self.ps7.s_axi_hp1
+        )
+        self.csr_devices.append("rtio_analyzer")
+
+
+class BASE(EBAZ4205):
+    def __init__(self, rtio_clk, acpki):
+        EBAZ4205.__init__(self, rtio_clk, acpki)
+
+
+VARIANTS = {cls.__name__.lower(): cls for cls in [BASE]}
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="ARTIQ port to the EBAZ4205 control card of Ebit E9+ BTC miner"
+    )
+    parser.add_argument(
+        "-r", default=None, help="build Rust interface into the specified file"
+    )
+    parser.add_argument(
+        "-m", default=None, help="build Rust memory interface into the specified file"
+    )
+    parser.add_argument(
+        "-c",
+        default=None,
+        help="build Rust compiler configuration into the specified file",
+    )
+    parser.add_argument(
+        "-g", default=None, help="build gateware into the specified directory"
+    )
+    parser.add_argument("--rtio-clk", default=125e6, help="RTIO Clock Frequency (Hz)")
+    parser.add_argument(
+        "-V",
+        "--variant",
+        default="base",
+        help="variant: " "[acpki_]base" "(default: %(default)s)",
+    )
+    args = parser.parse_args()
+
+    rtio_clk = int(args.rtio_clk)
+    variant = args.variant.lower()
+    acpki = variant.startswith("acpki_")
+    if acpki:
+        variant = variant[6:]
+
+    try:
+        cls = VARIANTS[variant]
+    except KeyError:
+        raise SystemExit("Invalid variant (-V/--variant)")
+
+    soc = cls(rtio_clk=rtio_clk, acpki=acpki)
+    soc.finalize()
+
+    if args.r is not None:
+        write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
+    if args.c is not None:
+        write_rustc_cfg_file(soc, args.c)
+    if args.g is not None:
+        soc.build(build_dir=args.g)
+
+
+if __name__ == "__main__":
+    main()

src/gateware/endianness.py

@@ -0,0 +1,21 @@
+from migen import *
+
+
+def convert_signal(signal):
+    assert len(signal) % 8 == 0
+    nbytes = len(signal)//8
+    signal_bytes = []
+    for i in range(nbytes):
+        signal_bytes.append(signal[8*i:8*(i+1)])
+    return Cat(*reversed(signal_bytes))
+
+
+def convert_value(value, size):
+    assert size % 8 == 0
+    nbytes = size//8
+    result = 0
+    for i in range(nbytes):
+        result <<= 8
+        result |= value & 0xff
+        value >>= 8
+    return result

src/gateware/kasli_soc.py

@@ -0,0 +1,672 @@
+#!/usr/bin/env python
+
+import argparse
+from operator import itemgetter
+
+from migen import *
+from migen.build.generic_platform import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import MultiReg
+from migen_axi.integration.soc_core import SoCCore
+from migen_axi.platforms import kasli_soc
+from misoc.interconnect.csr import *
+from misoc.cores import virtual_leds
+
+from artiq.coredevice import jsondesc
+from artiq.gateware import rtio, eem_7series
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
+from artiq.gateware.rtio.phy import ttl_simple
+from artiq.gateware.drtio.transceiver import gtx_7series, eem_serdes
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio import *
+from artiq.gateware.wrpll import wrpll
+
+import dma
+import analyzer
+import acpki
+import drtio_aux_controller
+import zynq_clocking
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
+
+eem_iostandard_dict = {
+     0: "LVDS_25",
+     1: "LVDS_25",
+     2: "LVDS",
+     3: "LVDS",
+     4: "LVDS",
+     5: "LVDS",
+     6: "LVDS",
+     7: "LVDS",
+     8: "LVDS_25",
+     9: "LVDS_25",
+    10: "LVDS",
+    11: "LVDS",
+}
+
+
+def eem_iostandard(eem):
+    return IOStandard(eem_iostandard_dict[eem])
+
+
+class SMAClkinForward(Module):
+    def __init__(self, platform):
+        sma_clkin = platform.request("sma_clkin")
+        sma_clkin_se = Signal()
+        cdr_clk_se = Signal()
+        cdr_clk = platform.request("cdr_clk")
+        self.specials += [
+            Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
+            Instance("ODDR", i_C=sma_clkin_se, i_CE=1, i_D1=1, i_D2=0, o_Q=cdr_clk_se),
+            Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
+        ]
+
+
+class GTPBootstrapClock(Module):
+    def __init__(self, platform, freq=125e6):
+        self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
+        self.cd_bootstrap.clk.attr.add("keep")
+
+        bootstrap_125 = platform.request("clk125_gtp")
+        bootstrap_se = Signal()
+        clk_out = Signal()
+        platform.add_period_constraint(bootstrap_125.p, 8.0)
+        self.specials += [
+            Instance("IBUFDS_GTE2",
+                i_CEB=0,
+                i_I=bootstrap_125.p, i_IB=bootstrap_125.n, 
+                o_O=bootstrap_se,
+                p_CLKCM_CFG="TRUE",
+                p_CLKRCV_TRST="TRUE",
+                p_CLKSWING_CFG=3),
+            Instance("BUFG", i_I=bootstrap_se, o_O=clk_out)
+        ]
+        if freq == 125e6:
+            self.comb += self.cd_bootstrap.clk.eq(clk_out)
+        elif freq == 100e6:
+            pll_fb = Signal()
+            pll_out = Signal()
+            self.specials += [
+                Instance("PLLE2_BASE",
+                    p_CLKIN1_PERIOD=8.0,
+                    i_CLKIN1=clk_out,
+                    i_CLKFBIN=pll_fb,
+                    o_CLKFBOUT=pll_fb,
+
+                    # VCO @ 1GHz
+                    p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
+
+                    # 100MHz for bootstrap
+                    p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_out,
+                ),
+                Instance("BUFG", i_I=pll_out, o_O=self.cd_bootstrap.clk)
+            ]
+        else:
+            raise ValueError("Bootstrap frequency must be 100 or 125MHz")
+
+
+class GenericStandalone(SoCCore):
+    def __init__(self, description, acpki=False):
+        self.acpki = acpki
+        clk_freq = description["rtio_frequency"]
+        with_wrpll = description["enable_wrpll"]
+
+        platform = kasli_soc.Platform()
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
+        ident = description["variant"]
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        self.config["HW_REV"] = description["hw_rev"]
+        clk_synth = platform.request("cdr_clk_clean_fabric")
+        clk_synth_se = Signal()
+        clk_synth_se_buf = Signal()
+        platform.add_period_constraint(clk_synth.p, 8.0)
+
+        self.specials += [ 
+            Instance("IBUFGDS",
+                p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE",
+                i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se
+            ),
+            Instance("BUFG", i_I=clk_synth_se, o_O=clk_synth_se_buf),
+        ]
+        fix_serdes_timing_path(platform)
+        self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
+        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
+        self.config["CLOCK_FREQUENCY"] = int(clk_freq)
+
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se_buf)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        self.csr_devices.append("sys_crg")
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+        self.crg.cd_sys = self.sys_crg.cd_sys
+
+        if with_wrpll:
+            self.submodules.wrpll_refclk = wrpll.FrequencyMultiplier(platform.request("sma_clkin"))
+            self.submodules.wrpll = wrpll.WRPLL(
+                platform=self.platform,
+                cd_ref=self.wrpll_refclk.cd_ref,
+                main_clk_se=clk_synth_se)
+            self.csr_devices.append("wrpll_refclk")
+            self.csr_devices.append("wrpll")
+            self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
+            self.config["HAS_SI549"] = None
+            self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
+        else:
+            self.submodules += SMAClkinForward(self.platform)
+            self.config["HAS_SI5324"] = None
+            self.config["SI5324_SOFT_RESET"] = None
+
+
+        self.rtio_channels = []
+        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
+        if has_grabber:
+            self.grabber_csr_group = []
+        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(
+            self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
+        )
+        self.csr_devices.append("rtio_core")
+
+        if self.acpki:
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri])
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        if has_grabber:
+            self.config["HAS_GRABBER"] = None
+            self.add_csr_group("grabber", self.grabber_csr_group)
+            for grabber in self.grabber_csr_group:
+                self.platform.add_false_path_constraints(
+                    self.sys_crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
+
+
+class GenericMaster(SoCCore):
+    def __init__(self, description, acpki=False):
+        clk_freq = description["rtio_frequency"]
+        with_wrpll = description["enable_wrpll"]
+
+        has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
+        self.acpki = acpki
+
+        platform = kasli_soc.Platform()
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
+        ident = description["variant"]
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        self.config["HW_REV"] = description["hw_rev"]
+
+        data_pads = [platform.request("sfp", i) for i in range(4)]
+
+        self.submodules.gt_drtio = gtx_7series.GTX(
+            clock_pads=platform.request("clk_gtp"),
+            pads=data_pads,
+            clk_freq=clk_freq)
+        self.csr_devices.append("gt_drtio")
+        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
+        self.config["CLOCK_FREQUENCY"] = int(clk_freq)
+
+        txout_buf = Signal()
+        gtx0 = self.gt_drtio.gtxs[0]
+        self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
+
+        ext_async_rst = Signal()
+
+        self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(
+            self.platform,
+            self.ps7,
+            txout_buf,
+            clk_sw=self.gt_drtio.stable_clkin.storage,
+            clk_sw_status=gtx0.tx_init.done,
+            ext_async_rst=ext_async_rst)
+        self.csr_devices.append("sys_crg")
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+        self.crg.cd_sys = self.sys_crg.cd_sys
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        fix_serdes_timing_path(platform)
+
+        self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
+        self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
+
+        if with_wrpll:
+            clk_synth = platform.request("cdr_clk_clean_fabric")
+            clk_synth_se = Signal()
+            platform.add_period_constraint(clk_synth.p, 8.0)
+            self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
+            self.submodules.wrpll_refclk = wrpll.FrequencyMultiplier(platform.request("sma_clkin"))
+            self.submodules.wrpll = wrpll.WRPLL(
+                platform=self.platform,
+                cd_ref=self.wrpll_refclk.cd_ref,
+                main_clk_se=clk_synth_se)
+            self.csr_devices.append("wrpll_refclk")
+            self.csr_devices.append("wrpll")
+            self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
+            self.config["HAS_SI549"] = None
+            self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
+        else:
+            self.submodules += SMAClkinForward(self.platform)
+            self.config["HAS_SI5324"] = None
+            self.config["SI5324_SOFT_RESET"] = None
+
+        self.rtio_channels = []
+        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
+        if has_drtio_over_eem:
+            self.eem_drtio_channels = []
+        if has_grabber:
+            self.grabber_csr_group = []
+        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+
+        self.drtio_csr_group = []
+        self.drtioaux_csr_group = []
+        self.drtioaux_memory_group = []
+        self.drtio_cri = []
+        for i in range(len(self.gt_drtio.channels)):
+            core_name = "drtio" + str(i)
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            self.drtio_csr_group.append(core_name)
+            self.drtioaux_csr_group.append(coreaux_name)
+            self.drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            core = cdr(DRTIOMaster(self.rtio_tsc, self.gt_drtio.channels[i]))
+            setattr(self.submodules, core_name, core)
+            self.drtio_cri.append(core.cri)
+            self.csr_devices.append(core_name)
+
+            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            size = coreaux.get_mem_size()
+            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
+            self.axi2csr.register_port(coreaux.get_rx_port(), size)
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
+
+        if has_drtio_over_eem:
+            self.add_eem_drtio(self.eem_drtio_channels)
+        self.add_drtio_cpuif_groups()
+
+        self.submodules.rtio_core = rtio.Core(
+            self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
+        )
+        self.csr_devices.append("rtio_core")
+
+        if self.acpki:
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri] + self.drtio_cri,
+            enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        if has_grabber:
+            self.config["HAS_GRABBER"] = None
+            self.add_csr_group("grabber", self.grabber_csr_group)
+        
+
+        self.submodules.virtual_leds = virtual_leds.VirtualLeds()
+        self.csr_devices.append("virtual_leds")
+
+        self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
+                for i, channel in enumerate(self.gt_drtio.channels)]
+
+    def add_eem_drtio(self, eem_drtio_channels):
+        # Must be called before invoking add_rtio() to construct the CRI
+        # interconnect properly
+        self.submodules.eem_transceiver = eem_serdes.EEMSerdes(self.platform, eem_drtio_channels)
+        self.csr_devices.append("eem_transceiver")
+        self.config["HAS_DRTIO_EEM"] = None
+        self.config["EEM_DRTIO_COUNT"] = len(eem_drtio_channels)
+
+        cdr = ClockDomainsRenamer({"rtio_rx": "sys"})
+        for i in range(len(self.eem_transceiver.channels)):
+            channel = i + len(self.gt_drtio.channels)
+            core_name = "drtio" + str(channel)
+            coreaux_name = "drtioaux" + str(channel)
+            memory_name = "drtioaux" + str(channel) + "_mem"
+            self.drtio_csr_group.append(core_name)
+            self.drtioaux_csr_group.append(coreaux_name)
+            self.drtioaux_memory_group.append(memory_name)
+
+            core = cdr(DRTIOMaster(self.rtio_tsc, self.eem_transceiver.channels[i]))
+            setattr(self.submodules, core_name, core)
+            self.drtio_cri.append(core.cri)
+            self.csr_devices.append(core_name)
+
+            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            size = coreaux.get_mem_size()
+            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
+            self.axi2csr.register_port(coreaux.get_rx_port(), size)
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
+
+    def add_drtio_cpuif_groups(self):
+        self.add_csr_group("drtio", self.drtio_csr_group)
+        self.add_csr_group("drtioaux", self.drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", self.drtioaux_memory_group)
+
+
+class GenericSatellite(SoCCore):
+    def __init__(self, description, acpki=False):
+        clk_freq = description["rtio_frequency"]
+        with_wrpll = description["enable_wrpll"]
+
+        self.acpki = acpki
+
+        platform = kasli_soc.Platform()
+        platform.toolchain.bitstream_commands.extend([
+            "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+        ])
+        ident = description["variant"]
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        self.config["HW_REV"] = description["hw_rev"]
+
+        data_pads = [platform.request("sfp", i) for i in range(4)]
+        
+        self.submodules.gt_drtio = gtx_7series.GTX(
+            clock_pads=platform.request("clk_gtp"),  
+            pads=data_pads,
+            clk_freq=clk_freq)
+        self.csr_devices.append("gt_drtio")
+
+        txout_buf = Signal()
+        gtx0 = self.gt_drtio.gtxs[0]
+        self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
+
+        ext_async_rst = Signal()
+
+        self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(
+            self.platform, 
+            self.ps7,
+            txout_buf,
+            clk_sw=self.gt_drtio.stable_clkin.storage,
+            clk_sw_status=gtx0.tx_init.done,
+            ext_async_rst=ext_async_rst)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        self.csr_devices.append("sys_crg")
+        self.crg = self.ps7 # HACK for eem_7series to find the clock
+        self.crg.cd_sys = self.sys_crg.cd_sys
+
+        fix_serdes_timing_path(platform)
+
+        self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
+        self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
+
+        self.rtio_channels = []
+        has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
+        if has_grabber:
+            self.grabber_csr_group = []
+        eem_7series.add_peripherals(self, description["peripherals"], iostandard=eem_iostandard)
+        for i in (0, 1):
+            print("USER LED at RTIO channel 0x{:06x}".format(len(self.rtio_channels)))
+            user_led = self.platform.request("user_led", i)
+            phy = ttl_simple.Output(user_led)
+            self.submodules += phy
+            self.rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["RTIO_LOG_CHANNEL"] = len(self.rtio_channels)
+        self.rtio_channels.append(rtio.LogChannel())
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        drtiorep_csr_group = []
+        self.drtio_cri = []
+        for i in range(len(self.gt_drtio.channels)):
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            if i == 0:
+                self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
+                core = cdr(DRTIOSatellite(
+                    self.rtio_tsc, self.gt_drtio.channels[i],
+                    self.rx_synchronizer))
+                self.submodules.drtiosat = core
+                self.csr_devices.append("drtiosat")
+            else:
+                corerep_name = "drtiorep" + str(i-1)
+                drtiorep_csr_group.append(corerep_name)
+
+                core = cdr(DRTIORepeater(
+                    self.rtio_tsc, self.gt_drtio.channels[i]))
+                setattr(self.submodules, corerep_name, core)
+                self.drtio_cri.append(core.cri)
+                self.csr_devices.append(corerep_name)
+
+            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            mem_size = coreaux.get_mem_size()
+            tx_port = coreaux.get_tx_port()
+            rx_port = coreaux.get_rx_port()
+            memory_address = self.axi2csr.register_port(tx_port, mem_size)
+            # rcv in upper half of the memory, thus added second
+            self.axi2csr.register_port(rx_port, mem_size)
+            # and registered in PS interface
+            # manually, because software refers to rx/tx by halves of entire memory block, not names
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+        self.add_csr_group("drtiorep", drtiorep_csr_group)
+
+        if self.acpki:
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.local_io = SyncRTIO(
+            self.rtio_tsc, self.rtio_channels, lane_count=description["sed_lanes"]
+        )
+        self.comb += [
+            self.drtiosat.async_errors.eq(self.local_io.async_errors),
+            self.local_io.sed_spread_enable.eq(self.drtiosat.sed_spread_enable.storage)
+        ]
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
+            [self.local_io.cri] + self.drtio_cri,
+            enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")     
+
+        self.submodules.rtio_moninj = rtio.MonInj(self.rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.local_io.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        rtio_clk_period = 1e9/clk_freq
+        self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
+        self.config["CLOCK_FREQUENCY"] = int(clk_freq)
+
+        if with_wrpll:
+            clk_synth = platform.request("cdr_clk_clean_fabric")
+            clk_synth_se = Signal()
+            platform.add_period_constraint(clk_synth.p, 8.0)
+            self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
+            self.submodules.wrpll = wrpll.WRPLL(
+                platform=self.platform,
+                cd_ref=self.gt_drtio.cd_rtio_rx0,
+                main_clk_se=clk_synth_se)
+            self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
+            self.csr_devices.append("wrpll_skewtester")
+            self.csr_devices.append("wrpll")
+            self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
+            self.config["HAS_SI549"] = None
+            self.config["WRPLL_REF_CLK"] = "GT_CDR"
+        else:
+            self.submodules.siphaser = SiPhaser7Series(
+                si5324_clkin=platform.request("cdr_clk"),
+                rx_synchronizer=self.rx_synchronizer,
+                ultrascale=False,
+                rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
+            self.csr_devices.append("siphaser")
+            self.config["HAS_SI5324"] = None
+            self.config["SI5324_SOFT_RESET"] = None
+
+        gtx0 = self.gt_drtio.gtxs[0]
+        platform.add_false_path_constraints(
+            gtx0.txoutclk, gtx0.rxoutclk)
+
+        if has_grabber:
+            self.config["HAS_GRABBER"] = None
+            self.add_csr_group("grabber", self.grabber_csr_group)
+            # no RTIO CRG here
+        
+        self.submodules.virtual_leds = virtual_leds.VirtualLeds()
+        self.csr_devices.append("virtual_leds")
+
+        self.comb += [self.virtual_leds.get(i).eq(channel.rx_ready)
+                for i, channel in enumerate(self.gt_drtio.channels)]
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="ARTIQ device binary builder for generic Kasli-SoC systems")
+    parser.add_argument("-r", default=None,
+        help="build Rust interface into the specified file")
+    parser.add_argument("-c", default=None,
+        help="build Rust compiler configuration into the specified file")
+    parser.add_argument("-m", default=None,
+        help="build Rust memory interface into the specified file")
+    parser.add_argument("-g", default=None,
+        help="build gateware into the specified directory")
+    parser.add_argument("--acpki", default=False, action="store_true",
+        help="enable ACPKI")
+    parser.add_argument("description", metavar="DESCRIPTION",
+                        help="JSON system description file")
+    args = parser.parse_args()
+    description = jsondesc.load(args.description)
+
+    if description["target"] != "kasli_soc":
+        raise ValueError("Description is for a different target")
+
+    if description["drtio_role"] == "standalone":
+        cls = GenericStandalone
+    elif description["drtio_role"] == "master":
+        cls = GenericMaster
+    elif description["drtio_role"] == "satellite":
+        cls = GenericSatellite
+    else:
+        raise ValueError("Invalid DRTIO role")
+
+    soc = cls(description, acpki=args.acpki)
+    soc.finalize()
+
+    if args.r is not None:
+        write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
+    if args.c is not None:
+        write_rustc_cfg_file(soc, args.c)
+    if args.g is not None:
+        soc.build(build_dir=args.g)
+
+
+if __name__ == "__main__":
+    main()

src/gateware/test_dma.py

@@ -0,0 +1,236 @@
+import unittest
+import random
+import itertools
+
+from migen import *
+from migen_axi.interconnect import axi
+
+from artiq.coredevice.exceptions import RTIOUnderflow, RTIODestinationUnreachable
+from artiq.gateware import rtio
+from artiq.gateware.rtio import cri
+from artiq.gateware.rtio.phy import ttl_simple
+
+import endianness
+import dma
+
+
+class AXIMemorySim:
+    def __init__(self, bus, data, max_queue=12):
+        self.bus = bus
+        self.data = data
+        self.max_queue = max_queue
+        self.align = len(bus.r.data)//8
+        self.queue = []
+
+    @passive
+    def ar(self):
+        while True:
+            if len(self.queue) < self.max_queue:
+                request = yield from self.bus.read_ar()
+                self.queue.append(request)
+            else:
+                yield
+
+    @passive
+    def r(self):
+        while True:
+            if self.queue:
+                request = self.queue.pop()
+                if request.burst:
+                    request_len = request.len + 1
+                else:
+                    request_len = 1
+                for i in range(request_len):
+                    if request.addr % self.align:
+                        raise ValueError
+                    addr = request.addr//self.align + i
+                    if addr < len(self.data):
+                        data = self.data[addr]
+                    else:
+                        data = 0
+                    data = endianness.convert_value(data, len(self.bus.r.data))
+                    yield from self.bus.write_r(request.id, data, last=i == request_len-1)
+            else:
+                yield
+
+
+def encode_n(n, min_length, max_length):
+    r = []
+    while n:
+        r.append(n & 0xff)
+        n >>= 8
+    r += [0]*(min_length - len(r))
+    if len(r) > max_length:
+        raise ValueError
+    return r
+
+
+def encode_record(channel, timestamp, address, data):
+    r = []
+    r += encode_n(channel, 3, 3)
+    r += encode_n(timestamp, 8, 8)
+    r += encode_n(address, 1, 1)
+    r += encode_n(data, 1, 64)
+    return encode_n(len(r)+1, 1, 1) + r
+
+
+def pack(x, size):
+    r = []
+    for i in range((len(x)+size-1)//size):
+        n = 0
+        for j in range(i*size, (i+1)*size):
+            n <<= 8
+            try:
+                n |= x[j]
+            except IndexError:
+                pass
+        r.append(n)
+    return r
+
+
+def encode_sequence(writes, ws):
+    sequence = [b for write in writes for b in encode_record(*write)]
+    sequence.append(0)
+    return pack(sequence, ws)
+
+
+def do_dma(dut, address):
+    yield from dut.dma.base_address.write(address)
+    yield from dut.enable.write(1)
+    yield
+    while ((yield from dut.enable.read())):
+        yield
+    error = yield from dut.cri_master.error.read()
+    if error & 1:
+        raise RTIOUnderflow
+    if error & 2:
+        raise RTIODestinationUnreachable
+
+
+test_writes1 = [
+    (0x01, 0x23, 0x12, 0x33),
+    (0x901, 0x902, 0x11, 0xeeeeeeeeeeeeeefffffffffffffffffffffffffffffff28888177772736646717738388488),
+    (0x81, 0x288, 0x88, 0x8888)
+]
+
+
+test_writes2 = [
+    (0x10, 0x10000, 0x20, 0x77),
+    (0x11, 0x10001, 0x22, 0x7777),
+    (0x12, 0x10002, 0x30, 0x777777),
+    (0x13, 0x10003, 0x40, 0x77777788),
+    (0x14, 0x10004, 0x50, 0x7777778899),
+]
+
+
+prng = random.Random(0)
+
+
+class TB(Module):
+    def __init__(self, ws):
+        sequence1 = encode_sequence(test_writes1, ws)
+        sequence2 = encode_sequence(test_writes2, ws)
+        offset = 512//ws
+        assert len(sequence1) < offset
+        sequence = (
+            sequence1 +
+            [prng.randrange(2**(ws*8)) for _ in range(offset-len(sequence1))] +
+            sequence2)
+
+        bus = axi.Interface(ws*8)
+        self.memory = AXIMemorySim(bus, sequence)
+        self.submodules.dut = dma.DMA(bus)
+
+
+test_writes_full_stack = [
+    (0, 32, 0, 1),
+    (1, 40, 0, 1),
+    (0, 48, 0, 0),
+    (1, 50, 0, 0),
+]
+
+
+class FullStackTB(Module):
+    def __init__(self, ws):
+        self.ttl0 = Signal()
+        self.ttl1 = Signal()
+
+        self.submodules.phy0 = ttl_simple.Output(self.ttl0)
+        self.submodules.phy1 = ttl_simple.Output(self.ttl1)
+
+        rtio_channels = [
+            rtio.Channel.from_phy(self.phy0),
+            rtio.Channel.from_phy(self.phy1)
+        ]
+
+        sequence = encode_sequence(test_writes_full_stack, ws)
+
+        bus = axi.Interface(ws*8)
+        self.memory = AXIMemorySim(bus, sequence)
+        self.submodules.dut = dma.DMA(bus)
+        self.submodules.tsc = rtio.TSC()
+        self.submodules.rtio = rtio.Core(self.tsc, rtio_channels)
+        self.comb += self.dut.cri.connect(self.rtio.cri)
+
+
+class TestDMA(unittest.TestCase):
+    def test_dma_noerror(self):
+        tb = TB(8)
+
+        def do_writes():
+            yield from do_dma(tb.dut, 0)
+            yield from do_dma(tb.dut, 512)
+
+        received = []
+        @passive
+        def rtio_sim():
+            dut_cri = tb.dut.cri
+            while True:
+                cmd = yield dut_cri.cmd
+                if cmd == cri.commands["nop"]:
+                    pass
+                elif cmd == cri.commands["write"]:
+                    channel = yield dut_cri.chan_sel
+                    timestamp = yield dut_cri.o_timestamp
+                    address = yield dut_cri.o_address
+                    data = yield dut_cri.o_data
+                    received.append((channel, timestamp, address, data))
+
+                    yield dut_cri.o_status.eq(1)
+                    for i in range(prng.randrange(10)):
+                        yield
+                    yield dut_cri.o_status.eq(0)
+                else:
+                    self.fail("unexpected RTIO command")
+                yield
+
+        run_simulation(tb, [do_writes(), rtio_sim(), tb.memory.ar(), tb.memory.r()])
+        self.assertEqual(received, test_writes1 + test_writes2)
+
+    def test_full_stack(self):
+        tb = FullStackTB(8)
+
+        ttl_changes = []
+        @passive
+        def monitor():
+            old_ttl_states = [0, 0]
+            for time in itertools.count():
+                ttl_states = [
+                    (yield tb.ttl0),
+                    (yield tb.ttl1)
+                ]
+                for i, (old, new) in enumerate(zip(old_ttl_states, ttl_states)):
+                    if new != old:
+                        ttl_changes.append((time, i))
+                old_ttl_states = ttl_states
+                yield
+
+        run_simulation(tb, {"sys": [
+            do_dma(tb.dut, 0), monitor(),
+            (None for _ in range(70)),
+            tb.memory.ar(), tb.memory.r()
+        ]}, {"sys": 8, "rsys": 8, "rio": 8, "rio_phy": 8})
+
+        correct_changes = [(timestamp + 11, channel)
+                           for channel, timestamp, _, _ in test_writes_full_stack]
+        self.assertEqual(ttl_changes, correct_changes)

src/gateware/zc706.py

@@ -0,0 +1,732 @@
+#!/usr/bin/env python
+
+import argparse
+from operator import itemgetter
+
+from migen import *
+from migen.build.generic_platform import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.cdc import MultiReg
+from migen_axi.integration.soc_core import SoCCore
+from migen_axi.platforms import zc706
+from misoc.interconnect.csr import *
+from misoc.cores import gpio
+
+from artiq.gateware import rtio, nist_clock, nist_qc2
+from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2, edge_counter
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
+from artiq.gateware.drtio.transceiver import gtx_7series
+from artiq.gateware.drtio.siphaser import SiPhaser7Series
+from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
+from artiq.gateware.drtio import *
+
+import dma
+import analyzer
+import acpki
+import drtio_aux_controller
+import zynq_clocking
+from config import write_csr_file, write_mem_file, write_rustc_cfg_file
+
+class SMAClkinForward(Module):
+    def __init__(self, platform):
+        sma_clkin = platform.request("user_sma_clock")
+        sma_clkin_se = Signal()
+        si5324_clkin_se = Signal()
+        si5324_clkin = platform.request("si5324_clkin")
+        self.specials += [
+            Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
+            Instance("ODDR", i_C=sma_clkin_se, i_CE=1, i_D1=1, i_D2=0, o_Q=si5324_clkin_se),
+            Instance("OBUFDS", i_I=si5324_clkin_se, o_O=si5324_clkin.p, o_OB=si5324_clkin.n)
+        ]
+
+
+class CLK200BootstrapClock(Module):
+    def __init__(self, platform, freq=125e6):
+        self.clock_domains.cd_bootstrap = ClockDomain(reset_less=True)
+        self.cd_bootstrap.clk.attr.add("keep")
+
+        clk200 = platform.request("clk200")
+        clk200_se = Signal()
+
+        pll_fb = Signal()
+        pll_clkout = Signal()
+        assert freq in [125e6, 100e6]
+        divide = int(1e9/freq)
+        self.specials += [
+            Instance("IBUFDS",
+                i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se),
+            Instance("PLLE2_BASE",
+                p_CLKIN1_PERIOD=5.0,
+                i_CLKIN1=clk200_se,
+                i_CLKFBIN=pll_fb,
+                o_CLKFBOUT=pll_fb,
+
+                # VCO @ 1GHz
+                p_CLKFBOUT_MULT=5, p_DIVCLK_DIVIDE=1,
+
+                # 125MHz/100MHz for bootstrap
+                p_CLKOUT1_DIVIDE=divide, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_clkout,
+            ),
+            Instance("BUFG", i_I=pll_clkout, o_O=self.cd_bootstrap.clk)
+        ]
+
+
+# The NIST backplanes require setting VADJ to 3.3V by reprogramming the power supply.
+# This also changes the I/O standard for some on-board LEDs.
+leds_fmc33 = [
+    ("user_led_33", 0, Pins("Y21"), IOStandard("LVCMOS33")),
+    ("user_led_33", 1, Pins("G2"), IOStandard("LVCMOS15")),
+    ("user_led_33", 2, Pins("W21"), IOStandard("LVCMOS33")),
+    ("user_led_33", 3, Pins("A17"), IOStandard("LVCMOS15")),
+]
+
+# same deal as with LEDs - changed I/O standard.
+si5324_fmc33 = [
+    ("si5324_33", 0,
+        Subsignal("rst_n", Pins("W23"), IOStandard("LVCMOS33")),
+        Subsignal("int", Pins("AJ25"), IOStandard("LVCMOS33"))
+    ),
+]
+
+pmod1_33 = [
+    ("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")),
+    ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
+    ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
+    ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
+    # rest removed for use with dummy spi
+]
+
+_ams101_dac = [
+    ("ams101_dac", 0,
+        Subsignal("ldac", Pins("XADC:GPIO0")),
+        Subsignal("clk", Pins("XADC:GPIO1")),
+        Subsignal("mosi", Pins("XADC:GPIO2")),
+        Subsignal("cs_n", Pins("XADC:GPIO3")),
+        IOStandard("LVCMOS15")
+     )
+]
+
+_pmod_spi = [ 
+    ("pmod_spi", 0,
+        # PMOD_1 4-7 pins, same bank as sfp_tx_disable or user_sma_clock
+        Subsignal("miso", Pins("Y20"), IOStandard("LVCMOS25")),
+        Subsignal("clk", Pins("AA20"), IOStandard("LVCMOS25")),
+        Subsignal("mosi", Pins("AC18"), IOStandard("LVCMOS25")),
+        Subsignal("cs_n", Pins("AC19"), IOStandard("LVCMOS25")),
+        IOStandard("LVCMOS25")
+    )
+]
+
+
+def prepare_zc706_platform(platform):
+    platform.toolchain.bitstream_commands.extend([
+        "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
+    ])
+
+class ZC706(SoCCore):
+    def __init__(self, acpki=False):
+        self.acpki = acpki
+
+        platform = zc706.Platform()
+        prepare_zc706_platform(platform)
+
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        platform.add_extension(si5324_fmc33)
+        self.comb += platform.request("si5324_33").rst_n.eq(1)
+
+        cdr_clk = Signal()
+        cdr_clk_buf = Signal()
+        si5324_out = platform.request("si5324_clkout")
+        platform.add_period_constraint(si5324_out.p, 8.0)
+        self.specials += [
+            Instance("IBUFDS_GTE2",
+                i_CEB=0,
+                i_I=si5324_out.p, i_IB=si5324_out.n,
+                o_O=cdr_clk,
+                p_CLKCM_CFG="TRUE",
+                p_CLKRCV_TRST="TRUE",
+                p_CLKSWING_CFG=3),
+            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
+        ]
+        self.config["HAS_SI5324"] = None
+        self.config["SI5324_AS_SYNTHESIZER"] = None
+        self.config["SI5324_SOFT_RESET"] = None
+        
+        self.submodules.bootstrap = CLK200BootstrapClock(platform)
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, cdr_clk_buf)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        self.csr_devices.append("sys_crg")
+
+    def add_rtio(self, rtio_channels):
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
+        self.csr_devices.append("rtio_core")
+
+        if self.acpki:
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri])
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+
+class _MasterBase(SoCCore):
+    def __init__(self, acpki=False, drtio100mhz=False):
+        self.acpki = acpki
+
+        clk_freq = 100e6 if drtio100mhz else 125e6
+
+        platform = zc706.Platform()
+        prepare_zc706_platform(platform)
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        platform.add_extension(si5324_fmc33)
+
+        self.comb += platform.request("sfp_tx_disable_n").eq(1)
+        data_pads = [
+            platform.request("sfp"),
+            platform.request("user_sma_mgt")
+        ]
+
+        self.submodules += SMAClkinForward(self.platform)
+
+        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
+        self.submodules.gt_drtio = gtx_7series.GTX(
+            clock_pads=platform.request("si5324_clkout"),
+            pads=data_pads,
+            clk_freq=clk_freq)
+        self.csr_devices.append("gt_drtio")
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        ext_async_rst = Signal()
+        txout_buf = Signal()
+        gtx0 = self.gt_drtio.gtxs[0]
+        self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
+        self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq)
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(
+            self.platform, 
+            self.ps7, 
+            txout_buf,
+            clk_sw=self.gt_drtio.stable_clkin.storage,
+            clk_sw_status=gtx0.tx_init.done,
+            ext_async_rst=ext_async_rst,
+            freq=clk_freq)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        self.csr_devices.append("sys_crg")
+
+        self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
+        self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
+
+        drtio_csr_group = []
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        self.drtio_cri = []
+        for i in range(len(self.gt_drtio.channels)):
+            core_name = "drtio" + str(i)
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtio_csr_group.append(core_name)
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            core = cdr(DRTIOMaster(
+                self.rtio_tsc, self.gt_drtio.channels[i]))
+            setattr(self.submodules, core_name, core)
+            self.drtio_cri.append(core.cri)
+            self.csr_devices.append(core_name)
+
+            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            mem_size = coreaux.get_mem_size()
+            memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), mem_size)
+            self.axi2csr.register_port(coreaux.get_rx_port(), mem_size)
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
+        self.add_csr_group("drtio", drtio_csr_group)
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+
+        self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6)
+
+        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
+        self.csr_devices.append("si5324_rst_n")
+        self.config["HAS_SI5324"] = None
+        self.config["SI5324_AS_SYNTHESIZER"] = None
+
+        # Constrain TX & RX timing for the first transceiver channel
+        # (First channel acts as master for phase alignment for all channels' TX)
+        platform.add_false_path_constraints(
+            gtx0.txoutclk, gtx0.rxoutclk)
+        # Constrain RX timing for the each transceiver channel
+        # (Each channel performs single-lane phase alignment for RX)
+        for gtx in self.gt_drtio.gtxs[1:]:
+            platform.add_false_path_constraints(
+                gtx0.txoutclk, gtx.rxoutclk)
+
+        fix_serdes_timing_path(platform)
+
+    def add_rtio(self, rtio_channels):
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+        self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
+        self.csr_devices.append("rtio_core")
+
+        if self.acpki:
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.rtio.cri, self.rtio_dma.cri],
+            [self.rtio_core.cri] + self.drtio_cri,
+            enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.rtio_core.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
+
+
+class _SatelliteBase(SoCCore):
+    def __init__(self, acpki=False, drtio100mhz=False):
+        self.acpki = acpki
+
+        clk_freq = 100e6 if drtio100mhz else 125e6
+
+        platform = zc706.Platform()
+        prepare_zc706_platform(platform)
+        ident = self.__class__.__name__
+        if self.acpki:
+            ident = "acpki_" + ident
+        SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
+
+        platform.add_extension(si5324_fmc33)
+
+        # SFP
+        self.comb += platform.request("sfp_tx_disable_n").eq(0)
+        data_pads = [
+            platform.request("sfp"),
+            platform.request("user_sma_mgt")
+        ]
+
+        self.submodules.rtio_tsc = rtio.TSC(glbl_fine_ts_width=3)
+
+        # 1000BASE_BX10 Ethernet compatible, 125MHz RTIO clock
+        self.submodules.gt_drtio = gtx_7series.GTX(
+            clock_pads=platform.request("si5324_clkout"),
+            pads=data_pads,
+            clk_freq=clk_freq)
+        self.csr_devices.append("gt_drtio")
+
+        ext_async_rst = Signal()
+        txout_buf = Signal()
+        txout_buf.attr.add("keep")
+        gtx0 = self.gt_drtio.gtxs[0]
+        self.specials += Instance(
+            "BUFG", 
+            i_I=gtx0.txoutclk, 
+            o_O=txout_buf)
+        self.submodules.bootstrap = CLK200BootstrapClock(platform, clk_freq)
+        self.submodules.sys_crg = zynq_clocking.SYSCRG(
+            self.platform, 
+            self.ps7, 
+            txout_buf,
+            clk_sw=self.gt_drtio.stable_clkin.storage,
+            clk_sw_status=gtx0.tx_init.done,
+            ext_async_rst=ext_async_rst,
+            freq=clk_freq)
+        platform.add_false_path_constraints(
+            self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
+        self.csr_devices.append("sys_crg")
+
+        self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
+        self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
+
+        drtioaux_csr_group = []
+        drtioaux_memory_group = []
+        drtiorep_csr_group = []
+        self.drtio_cri = []
+        for i in range(len(self.gt_drtio.channels)):
+            coreaux_name = "drtioaux" + str(i)
+            memory_name = "drtioaux" + str(i) + "_mem"
+            drtioaux_csr_group.append(coreaux_name)
+            drtioaux_memory_group.append(memory_name)
+
+            cdr = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})
+
+            # Satellite
+            if i == 0:
+                self.submodules.rx_synchronizer = cdr(XilinxRXSynchronizer())
+                core = cdr(DRTIOSatellite(
+                    self.rtio_tsc, self.gt_drtio.channels[0], self.rx_synchronizer))
+                self.submodules.drtiosat = core
+                self.csr_devices.append("drtiosat")
+            # Repeaters
+            else:
+                corerep_name = "drtiorep" + str(i-1)
+                drtiorep_csr_group.append(corerep_name)
+                core = cdr(DRTIORepeater(
+                    self.rtio_tsc, self.gt_drtio.channels[i]))
+                setattr(self.submodules, corerep_name, core)
+                self.drtio_cri.append(core.cri)
+                self.csr_devices.append(corerep_name)
+
+            coreaux = cdr(drtio_aux_controller.DRTIOAuxControllerBare(core.link_layer))
+            setattr(self.submodules, coreaux_name, coreaux)
+            self.csr_devices.append(coreaux_name)
+
+            mem_size = coreaux.get_mem_size()
+            tx_port = coreaux.get_tx_port()
+            rx_port = coreaux.get_rx_port()
+            memory_address = self.axi2csr.register_port(tx_port, mem_size)
+            # rcv in upper half of the memory, thus added second
+            self.axi2csr.register_port(rx_port, mem_size)
+            # and registered in PS interface
+            # manually, because software refers to rx/tx by halves of entire memory block, not names
+            self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
+        self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
+        self.add_csr_group("drtioaux", drtioaux_csr_group)
+        self.add_csr_group("drtiorep", drtiorep_csr_group)
+        self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
+
+        self.config["RTIO_FREQUENCY"] = str(self.gt_drtio.rtio_clk_freq/1e6)
+
+        # Si5324 Phaser
+        self.submodules.siphaser = SiPhaser7Series(
+            si5324_clkin=platform.request("si5324_clkin"),
+            rx_synchronizer=self.rx_synchronizer,
+            ultrascale=False,
+            rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
+        platform.add_false_path_constraints(
+            self.sys_crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
+        self.csr_devices.append("siphaser")
+        self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
+        self.csr_devices.append("si5324_rst_n")
+        self.config["HAS_SI5324"] = None
+
+        rtio_clk_period = 1e9/self.gt_drtio.rtio_clk_freq
+        # Constrain TX & RX timing for the first transceiver channel
+        # (First channel acts as master for phase alignment for all channels' TX)
+        platform.add_false_path_constraints(
+            gtx0.txoutclk, gtx0.rxoutclk)
+        # Constrain RX timing for the each transceiver channel
+        # (Each channel performs single-lane phase alignment for RX)
+        for gtx in self.gt_drtio.gtxs[1:]:
+            platform.add_false_path_constraints(
+                self.sys_crg.cd_sys.clk, gtx.rxoutclk)
+
+        fix_serdes_timing_path(platform)
+
+    def add_rtio(self, rtio_channels):
+        self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
+        self.csr_devices.append("rtio_moninj")
+
+        if self.acpki:
+            self.config["KI_IMPL"] = "acp"
+            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
+                                                         bus=self.ps7.s_axi_acp,
+                                                         user=self.ps7.s_axi_acp_user,
+                                                         evento=self.ps7.event.o)
+            self.csr_devices.append("rtio")
+        else:
+            self.config["KI_IMPL"] = "csr"
+            self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
+            self.csr_devices.append("rtio")
+
+        self.submodules.rtio_dma = dma.DMA(self.ps7.s_axi_hp0)
+        self.csr_devices.append("rtio_dma")
+
+        self.submodules.local_io = SyncRTIO(self.rtio_tsc, rtio_channels)
+        self.comb += [
+            self.drtiosat.async_errors.eq(self.local_io.async_errors),
+            self.local_io.sed_spread_enable.eq(self.drtiosat.sed_spread_enable.storage)
+        ]
+        self.submodules.cri_con = rtio.CRIInterconnectShared(
+            [self.drtiosat.cri, self.rtio_dma.cri, self.rtio.cri],
+            [self.local_io.cri] + self.drtio_cri,
+            enable_routing=True)
+        self.csr_devices.append("cri_con")
+
+        self.submodules.rtio_analyzer = analyzer.Analyzer(self.rtio_tsc, self.local_io.cri,
+                                                          self.ps7.s_axi_hp1)
+        self.csr_devices.append("rtio_analyzer")
+
+        self.submodules.routing_table = rtio.RoutingTableAccess(self.cri_con)
+        self.csr_devices.append("routing_table")
+
+
+
+class _NIST_CLOCK_RTIO:
+    """
+    NIST clock hardware, with old backplane and 11 DDS channels
+    """
+    def __init__(self):
+        platform = self.platform
+        platform.add_extension(nist_clock.fmc_adapter_io)
+        platform.add_extension(leds_fmc33)
+        platform.add_extension(pmod1_33)
+        platform.add_extension(_ams101_dac)
+        platform.add_extension(_pmod_spi)
+
+        rtio_channels = []
+
+        for i in range(16):
+            if i % 4 == 3:
+                phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
+                self.submodules += phy
+                rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+            else:
+                phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
+                self.submodules += phy
+                rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        for i in range(2):
+            phy = ttl_serdes_7series.InOut_8X(platform.request("pmt", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+
+        # no SMA GPIO, replaced with PMOD1_0
+        phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+
+        phy = ttl_simple.Output(platform.request("user_led_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        ams101_dac = self.platform.request("ams101_dac", 0)
+        phy = ttl_simple.Output(ams101_dac.ldac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        phy = ttl_simple.ClockGen(platform.request("la32_p"))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        phy = spi2.SPIMaster(ams101_dac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(
+            phy, ififo_depth=4))
+
+        for i in range(3):
+            phy = spi2.SPIMaster(self.platform.request("spi", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(
+                phy, ififo_depth=128))
+
+        # no SDIO on PL side, dummy SPI placeholder instead
+        phy = spi2.SPIMaster(platform.request("pmod_spi"))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
+
+        phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        rtio_channels.append(rtio.LogChannel())
+
+        self.add_rtio(rtio_channels)
+
+
+class _NIST_QC2_RTIO:
+    """
+    NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
+    and 24 DDS channels.  Two backplanes are used.
+    """
+    def __init__(self):
+        platform = self.platform
+        platform.add_extension(nist_qc2.fmc_adapter_io)
+        platform.add_extension(leds_fmc33)
+        platform.add_extension(_ams101_dac)
+        platform.add_extension(pmod1_33)
+
+        rtio_channels = []
+        edge_counter_phy = []
+
+        # All TTL channels are In+Out capable
+        for i in range(40):
+            phy = ttl_serdes_7series.InOut_8X(platform.request("ttl", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+            # first four TTLs will also have edge counters
+            if i < 4:
+                edge_counter_phy.append(phy)
+
+        # no SMA GPIO, replaced with PMOD1_0
+        phy = ttl_serdes_7series.InOut_8X(platform.request("pmod1_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
+
+        phy = ttl_simple.Output(platform.request("user_led_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        ams101_dac = self.platform.request("ams101_dac", 0)
+        phy = ttl_simple.Output(ams101_dac.ldac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
+        # CLK0, CLK1 are for clock generators, on backplane SMP connectors
+        for i in range(2):
+            phy = ttl_simple.ClockGen(
+                platform.request("clkout", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy))
+        
+        phy = spi2.SPIMaster(ams101_dac)
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(
+            phy, ififo_depth=4))
+
+        for i in range(4):
+            phy = spi2.SPIMaster(self.platform.request("spi", i))
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(
+                phy, ififo_depth=128))
+
+        for backplane_offset in range(2):
+            phy = dds.AD9914(
+                platform.request("dds", backplane_offset), 12, onehot=True)
+            self.submodules += phy
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
+        
+        for phy in edge_counter_phy:
+            counter = edge_counter.SimpleEdgeCounter(phy.input_state)
+            self.submodules += counter
+            rtio_channels.append(rtio.Channel.from_phy(counter))
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        rtio_channels.append(rtio.LogChannel())
+
+        self.add_rtio(rtio_channels)
+
+
+class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki)
+        self.submodules += SMAClkinForward(self.platform)
+        _NIST_CLOCK_RTIO.__init__(self)
+
+class NIST_CLOCK_Master(_MasterBase, _NIST_CLOCK_RTIO):
+    def __init__(self, acpki, drtio100mhz):
+        _MasterBase.__init__(self, acpki, drtio100mhz)
+        _NIST_CLOCK_RTIO.__init__(self)
+
+class NIST_CLOCK_Satellite(_SatelliteBase, _NIST_CLOCK_RTIO):
+    def __init__(self, acpki, drtio100mhz):
+        _SatelliteBase.__init__(self, acpki, drtio100mhz)
+        _NIST_CLOCK_RTIO.__init__(self)
+
+class NIST_QC2(ZC706, _NIST_QC2_RTIO):
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki)
+        self.submodules += SMAClkinForward(self.platform)
+        _NIST_QC2_RTIO.__init__(self)
+
+class NIST_QC2_Master(_MasterBase, _NIST_QC2_RTIO):
+    def __init__(self, acpki, drtio100mhz):
+        _MasterBase.__init__(self, acpki, drtio100mhz)
+        _NIST_QC2_RTIO.__init__(self)
+
+class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
+    def __init__(self, acpki, drtio100mhz):
+        _SatelliteBase.__init__(self, acpki, drtio100mhz)
+        _NIST_QC2_RTIO.__init__(self)
+
+VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
+                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="ARTIQ port to the ZC706 Zynq development kit")
+    parser.add_argument("-r", default=None,
+        help="build Rust interface into the specified file")
+    parser.add_argument("-m", default=None,
+        help="build Rust memory interface into the specified file")
+    parser.add_argument("-c", default=None,
+        help="build Rust compiler configuration into the specified file")
+    parser.add_argument("-g", default=None,
+        help="build gateware into the specified directory")
+    parser.add_argument("-V", "--variant", default="nist_clock",
+                        help="variant: "
+                             "[acpki_]nist_clock/nist_qc2[_master/_satellite][_100mhz]"
+                             "(default: %(default)s)")
+    args = parser.parse_args()
+
+    variant = args.variant.lower()
+    acpki = variant.startswith("acpki_")
+    if acpki:
+        variant = variant[6:]
+    drtio100mhz = variant.endswith("_100mhz")
+    if drtio100mhz:
+        variant = variant[:-7]
+    try:
+        cls = VARIANTS[variant]
+    except KeyError:
+        raise SystemExit("Invalid variant (-V/--variant)")
+
+    soc = cls(acpki=acpki, drtio100mhz=drtio100mhz)
+    soc.finalize()
+
+    if args.r is not None:
+        write_csr_file(soc, args.r)
+    if args.m is not None:
+        write_mem_file(soc, args.m)
+    if args.c is not None:
+        write_rustc_cfg_file(soc, args.c)
+    if args.g is not None:
+        soc.build(build_dir=args.g)
+
+if __name__ == "__main__":
+    main()

src/gateware/zynq_clocking.py

@@ -0,0 +1,154 @@
+from migen import *
+from migen.genlib.cdc import MultiReg
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from misoc.interconnect.csr import *
+
+
+class ClockSwitchFSM(Module):
+    def __init__(self):
+        self.i_clk_sw = Signal()
+
+        self.o_clk_sw = Signal()
+        self.o_reset = Signal()
+
+        ###
+
+        i_switch = Signal()
+        o_switch = Signal()
+        reset = Signal()
+
+        # at 125MHz bootstrap cd, will get around 0.5ms
+        delay_counter = Signal(16, reset=0xFFFF)
+
+        # register to prevent glitches
+        self.sync.bootstrap += [
+            self.o_clk_sw.eq(o_switch),
+            self.o_reset.eq(reset),
+        ]
+
+        self.o_clk_sw.attr.add("no_retiming")
+        self.o_reset.attr.add("no_retiming")
+        self.i_clk_sw.attr.add("no_retiming")
+        i_switch.attr.add("no_retiming")
+
+        self.specials += MultiReg(self.i_clk_sw, i_switch, "bootstrap")
+
+        fsm = ClockDomainsRenamer("bootstrap")(FSM(reset_state="START"))
+
+        self.submodules += fsm
+
+        fsm.act("START",
+            If(i_switch & ~o_switch,
+                NextState("RESET_START"))
+        )
+        
+        fsm.act("RESET_START",
+            reset.eq(1),
+            If(delay_counter == 0,
+                NextValue(delay_counter, 0xFFFF),
+                NextState("CLOCK_SWITCH")
+            ).Else(
+                NextValue(delay_counter, delay_counter-1),
+            )
+        )
+
+        fsm.act("CLOCK_SWITCH",
+            reset.eq(1),
+            NextValue(o_switch, 1),
+            NextValue(delay_counter, delay_counter-1),
+            If(delay_counter == 0,
+                NextState("END"))
+        )
+        fsm.act("END",
+            NextValue(o_switch, 1),
+            reset.eq(0))
+
+
+class SYSCRG(Module, AutoCSR):
+    def __init__(self, platform, ps7, main_clk, clk_sw=None, clk_sw_status=None, freq=125e6, ext_async_rst=None, ):
+        # assumes bootstrap clock is same freq as main and sys output
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys5x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_clk200 = ClockDomain()
+
+        self.current_clock = CSRStatus()
+
+        self.cd_sys.clk.attr.add("keep")
+
+        bootstrap_clk = ClockSignal("bootstrap")
+
+        period = 1e9/freq
+
+        self.submodules.clk_sw_fsm = ClockSwitchFSM()
+
+        if clk_sw is None:
+            self.clock_switch = CSRStorage()
+            self.comb += self.clk_sw_fsm.i_clk_sw.eq(self.clock_switch.storage)
+        else:
+            self.comb += self.clk_sw_fsm.i_clk_sw.eq(clk_sw)
+
+        self.mmcm_locked = Signal()
+        mmcm_sys = Signal()
+        mmcm_sys4x = Signal()
+        mmcm_sys5x = Signal()
+        mmcm_clk208 = Signal()
+        mmcm_fb_clk = Signal()
+        self.specials += [
+            Instance("MMCME2_ADV",
+                p_STARTUP_WAIT="FALSE", o_LOCKED=self.mmcm_locked,
+                p_BANDWIDTH="HIGH",
+                p_REF_JITTER1=0.001,
+                p_CLKIN1_PERIOD=period, i_CLKIN1=main_clk,
+                p_CLKIN2_PERIOD=period, i_CLKIN2=bootstrap_clk,
+                i_CLKINSEL=self.clk_sw_fsm.o_clk_sw,
+
+                # VCO @ 1.25GHz
+                p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
+                i_CLKFBIN=mmcm_fb_clk,
+                i_RST=self.clk_sw_fsm.o_reset,
+
+                o_CLKFBOUT=mmcm_fb_clk,
+
+                p_CLKOUT0_DIVIDE_F=2.5, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=mmcm_sys4x,
+
+                # 125MHz
+                p_CLKOUT1_DIVIDE=10, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=mmcm_sys,
+
+                # 625MHz
+                p_CLKOUT2_DIVIDE=2, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=mmcm_sys5x,
+
+                # 208MHz
+                p_CLKOUT3_DIVIDE=6, p_CLKOUT3_PHASE=0.0, o_CLKOUT3=mmcm_clk208,
+            ),
+            Instance("BUFG", i_I=mmcm_sys5x, o_O=self.cd_sys5x.clk),
+            Instance("BUFG", i_I=mmcm_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=mmcm_sys4x, o_O=self.cd_sys4x.clk),
+            Instance("BUFG", i_I=mmcm_clk208, o_O=self.cd_clk200.clk),
+        ]
+
+        if ext_async_rst is not None:
+            self.specials += [
+                AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked | ext_async_rst),
+                AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked | ext_async_rst),
+            ]
+        else:
+            self.specials += [
+                AsyncResetSynchronizer(self.cd_sys, ~self.mmcm_locked),
+                AsyncResetSynchronizer(self.cd_clk200, ~self.mmcm_locked),
+            ]
+
+        reset_counter = Signal(4, reset=15)
+        ic_reset = Signal(reset=1)
+        self.sync.clk200 += \
+            If(reset_counter != 0,
+                reset_counter.eq(reset_counter - 1)
+            ).Else(
+                ic_reset.eq(0)
+            )
+        self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
+
+        if clk_sw_status is None:
+            self.comb += self.current_clock.status.eq(self.clk_sw_fsm.o_clk_sw)
+        else:
+            self.comb += self.current_clock.status.eq(clk_sw_status)

src/include/_ansi.h

@@ -0,0 +1,82 @@
+/* Provide support for both ANSI and non-ANSI environments.  */
+
+/* To get a strict ANSI C environment, define macro __STRICT_ANSI__.  This will
+   "comment out" the non-ANSI parts of the ANSI header files (non-ANSI header
+   files aren't affected).  */
+
+#ifndef	_ANSIDECL_H_
+#define	_ANSIDECL_H_
+
+#include <newlib.h>
+#include <sys/config.h>
+
+/*  ISO C++.  */
+
+#ifdef __cplusplus
+#if !(defined(_BEGIN_STD_C) && defined(_END_STD_C))
+#ifdef _HAVE_STD_CXX
+#define _BEGIN_STD_C namespace std { extern "C" {
+#define _END_STD_C  } }
+#else
+#define _BEGIN_STD_C extern "C" {
+#define _END_STD_C  }
+#endif
+#if __GNUC_PREREQ (3, 3)
+#define _NOTHROW __attribute__ ((__nothrow__))
+#else
+#define _NOTHROW throw()
+#endif
+#endif
+#else
+#define _BEGIN_STD_C
+#define _END_STD_C
+#define _NOTHROW
+#endif
+
+#ifndef _LONG_DOUBLE
+#define _LONG_DOUBLE long double
+#endif
+
+/* Support gcc's __attribute__ facility.  */
+
+#ifdef __GNUC__
+#define _ATTRIBUTE(attrs) __attribute__ (attrs)
+#else
+#define _ATTRIBUTE(attrs)
+#endif
+
+/*  The traditional meaning of 'extern inline' for GCC is not
+  to emit the function body unless the address is explicitly
+  taken.  However this behaviour is changing to match the C99
+  standard, which uses 'extern inline' to indicate that the
+  function body *must* be emitted.  Likewise, a function declared
+  without either 'extern' or 'static' defaults to extern linkage
+  (C99 6.2.2p5), and the compiler may choose whether to use the
+  inline version or call the extern linkage version (6.7.4p6).
+  If we are using GCC, but do not have the new behaviour, we need
+  to use extern inline; if we are using a new GCC with the
+  C99-compatible behaviour, or a non-GCC compiler (which we will
+  have to hope is C99, since there is no other way to achieve the
+  effect of omitting the function if it isn't referenced) we use
+  'static inline', which c99 defines to mean more-or-less the same
+  as the Gnu C 'extern inline'.  */
+#if defined(__GNUC__) && !defined(__GNUC_STDC_INLINE__)
+/* We're using GCC, but without the new C99-compatible behaviour.  */
+#define _ELIDABLE_INLINE extern __inline__ _ATTRIBUTE ((__always_inline__))
+#else
+/* We're using GCC in C99 mode, or an unknown compiler which
+  we just have to hope obeys the C99 semantics of inline.  */
+#define _ELIDABLE_INLINE static __inline__
+#endif
+
+#if __GNUC_PREREQ (3, 1)
+#define _NOINLINE		__attribute__ ((__noinline__))
+#define _NOINLINE_STATIC	_NOINLINE static
+#else
+/* On non-GNU compilers and GCC prior to version 3.1 the compiler can't be
+   trusted not to inline if it is static. */
+#define _NOINLINE
+#define _NOINLINE_STATIC
+#endif
+
+#endif /* _ANSIDECL_H_ */

src/include/_newlib_version.h

@@ -0,0 +1,12 @@
+/* _newlib_version.h.  Generated from _newlib_version.hin by configure.  */
+/* Version macros for internal and downstream use. */
+#ifndef _NEWLIB_VERSION_H__
+#define _NEWLIB_VERSION_H__ 1
+
+#define _NEWLIB_VERSION "3.1.0"
+#define __NEWLIB__ 3
+#define __NEWLIB_MINOR__ 1
+#define __NEWLIB_PATCHLEVEL__ 0
+
+#endif /* !_NEWLIB_VERSION_H__ */
+

src/include/alloca.h

@@ -0,0 +1,21 @@
+/* libc/include/alloca.h - Allocate memory on stack */
+
+/* Written 2000 by Werner Almesberger */
+/* Rearranged for general inclusion by stdlib.h.
+   2001, Corinna Vinschen <vinschen@redhat.com> */
+
+#ifndef _NEWLIB_ALLOCA_H
+#define _NEWLIB_ALLOCA_H
+
+#include "_ansi.h"
+#include <sys/reent.h>
+
+#undef alloca
+
+#ifdef __GNUC__
+#define alloca(size) __builtin_alloca(size)
+#else
+void * alloca (size_t);
+#endif
+
+#endif

src/include/assert.h

@@ -0,0 +1,50 @@
+/*
+	assert.h
+*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "_ansi.h"
+
+#undef assert
+
+#ifdef NDEBUG           /* required by ANSI standard */
+# define assert(__e) ((void)0)
+#else
+# define assert(__e) ((__e) ? (void)0 : __assert_func (__FILE__, __LINE__, \
+						       __ASSERT_FUNC, #__e))
+
+# ifndef __ASSERT_FUNC
+  /* Use g++'s demangled names in C++.  */
+#  if defined __cplusplus && defined __GNUC__
+#   define __ASSERT_FUNC __PRETTY_FUNCTION__
+
+  /* C99 requires the use of __func__.  */
+#  elif __STDC_VERSION__ >= 199901L
+#   define __ASSERT_FUNC __func__
+
+  /* Older versions of gcc don't have __func__ but can use __FUNCTION__.  */
+#  elif __GNUC__ >= 2
+#   define __ASSERT_FUNC __FUNCTION__
+
+  /* failed to detect __func__ support.  */
+#  else
+#   define __ASSERT_FUNC ((char *) 0)
+#  endif
+# endif /* !__ASSERT_FUNC */
+#endif /* !NDEBUG */
+
+void __assert (const char *, int, const char *)
+	    _ATTRIBUTE ((__noreturn__));
+void __assert_func (const char *, int, const char *, const char *)
+	    _ATTRIBUTE ((__noreturn__));
+
+#if __STDC_VERSION__ >= 201112L && !defined __cplusplus
+# define static_assert _Static_assert
+#endif
+
+#ifdef __cplusplus
+}
+#endif

src/include/inttypes.h

@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2004, 2005 by
+ * Ralf Corsepius, Ulm/Germany. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+/**
+ *  @file  inttypes.h
+ */
+
+#ifndef _INTTYPES_H
+#define _INTTYPES_H
+
+#include <newlib.h>
+#include <sys/config.h>
+#include <sys/_intsup.h>
+#include "_ansi.h"
+#include <stdint.h>
+#define __need_wchar_t
+#include <stddef.h>
+
+#if __BSD_VISIBLE
+#include <xlocale.h>
+#endif
+
+#define __STRINGIFY(a) #a
+
+/* 8-bit types */
+#define __PRI8(x) __INT8 __STRINGIFY(x)
+#define __PRI8LEAST(x) __LEAST8 __STRINGIFY(x)
+#define __PRI8FAST(x) __FAST8 __STRINGIFY(x)
+
+/* NOTICE: scanning 8-bit types requires use of the hh specifier
+ * which is only supported on newlib platforms that
+ * are built with C99 I/O format support enabled.  If the flag in
+ * newlib.h hasn't been set during configuration to indicate this, the 8-bit
+ * scanning format macros are disabled here as they result in undefined
+ * behaviour which can include memory overwrite.  Overriding the flag after the
+ * library has been built is not recommended as it will expose the underlying
+ * undefined behaviour.
+ */
+
+#if defined(_WANT_IO_C99_FORMATS)
+  #define __SCN8(x) __INT8 __STRINGIFY(x)
+	#define __SCN8LEAST(x) __LEAST8 __STRINGIFY(x)
+	#define __SCN8FAST(x) __FAST8 __STRINGIFY(x)
+#endif /* _WANT_IO_C99_FORMATS */
+
+
+#define PRId8		__PRI8(d)
+#define PRIi8		__PRI8(i)
+#define PRIo8		__PRI8(o)
+#define PRIu8		__PRI8(u)
+#define PRIx8		__PRI8(x)
+#define PRIX8		__PRI8(X)
+
+/* Macros below are only enabled for a newlib built with C99 I/O format support. */
+#if defined(_WANT_IO_C99_FORMATS)
+
+#define SCNd8		__SCN8(d)
+#define SCNi8		__SCN8(i)
+#define SCNo8		__SCN8(o)
+#define SCNu8		__SCN8(u)
+#define SCNx8		__SCN8(x)
+
+#endif /* _WANT_IO_C99_FORMATS */
+
+
+#define PRIdLEAST8	__PRI8LEAST(d)
+#define PRIiLEAST8	__PRI8LEAST(i)
+#define PRIoLEAST8	__PRI8LEAST(o)
+#define PRIuLEAST8	__PRI8LEAST(u)
+#define PRIxLEAST8	__PRI8LEAST(x)
+#define PRIXLEAST8	__PRI8LEAST(X)
+
+/* Macros below are only enabled for a newlib built with C99 I/O format support. */
+#if defined(_WANT_IO_C99_FORMATS)
+
+  #define SCNdLEAST8	__SCN8LEAST(d)
+  #define SCNiLEAST8	__SCN8LEAST(i)
+  #define SCNoLEAST8	__SCN8LEAST(o)
+  #define SCNuLEAST8	__SCN8LEAST(u)
+  #define SCNxLEAST8	__SCN8LEAST(x)
+
+#endif /* _WANT_IO_C99_FORMATS */
+
+#define PRIdFAST8	__PRI8FAST(d)
+#define PRIiFAST8	__PRI8FAST(i)
+#define PRIoFAST8	__PRI8FAST(o)
+#define PRIuFAST8	__PRI8FAST(u)
+#define PRIxFAST8	__PRI8FAST(x)
+#define PRIXFAST8	__PRI8FAST(X)
+
+/* Macros below are only enabled for a newlib built with C99 I/O format support. */
+#if defined(_WANT_IO_C99_FORMATS)
+
+  #define SCNdFAST8	__SCN8FAST(d)
+  #define SCNiFAST8	__SCN8FAST(i)
+  #define SCNoFAST8	__SCN8FAST(o)
+  #define SCNuFAST8	__SCN8FAST(u)
+  #define SCNxFAST8	__SCN8FAST(x)
+
+#endif /* _WANT_IO_C99_FORMATS */
+
+/* 16-bit types */
+#define __PRI16(x) __INT16 __STRINGIFY(x)
+#define __PRI16LEAST(x) __LEAST16 __STRINGIFY(x)
+#define __PRI16FAST(x) __FAST16 __STRINGIFY(x)
+#define __SCN16(x) __INT16 __STRINGIFY(x)
+#define __SCN16LEAST(x) __LEAST16 __STRINGIFY(x)
+#define __SCN16FAST(x) __FAST16 __STRINGIFY(x)
+
+
+#define PRId16		__PRI16(d)
+#define PRIi16		__PRI16(i)
+#define PRIo16		__PRI16(o)
+#define PRIu16		__PRI16(u)
+#define PRIx16		__PRI16(x)
+#define PRIX16		__PRI16(X)
+
+#define SCNd16		__SCN16(d)
+#define SCNi16		__SCN16(i)
+#define SCNo16		__SCN16(o)
+#define SCNu16		__SCN16(u)
+#define SCNx16		__SCN16(x)
+
+
+#define PRIdLEAST16	__PRI16LEAST(d)
+#define PRIiLEAST16	__PRI16LEAST(i)
+#define PRIoLEAST16	__PRI16LEAST(o)
+#define PRIuLEAST16	__PRI16LEAST(u)
+#define PRIxLEAST16	__PRI16LEAST(x)
+#define PRIXLEAST16	__PRI16LEAST(X)
+
+#define SCNdLEAST16	__SCN16LEAST(d)
+#define SCNiLEAST16	__SCN16LEAST(i)
+#define SCNoLEAST16	__SCN16LEAST(o)
+#define SCNuLEAST16	__SCN16LEAST(u)
+#define SCNxLEAST16	__SCN16LEAST(x)
+
+
+#define PRIdFAST16	__PRI16FAST(d)
+#define PRIiFAST16	__PRI16FAST(i)
+#define PRIoFAST16	__PRI16FAST(o)
+#define PRIuFAST16	__PRI16FAST(u)
+#define PRIxFAST16	__PRI16FAST(x)
+#define PRIXFAST16	__PRI16FAST(X)
+
+#define SCNdFAST16	__SCN16FAST(d)
+#define SCNiFAST16	__SCN16FAST(i)
+#define SCNoFAST16	__SCN16FAST(o)
+#define SCNuFAST16	__SCN16FAST(u)
+#define SCNxFAST16	__SCN16FAST(x)
+
+/* 32-bit types */
+#define __PRI32(x) __INT32 __STRINGIFY(x)
+#define __SCN32(x) __INT32 __STRINGIFY(x)
+#define __PRI32LEAST(x) __LEAST32 __STRINGIFY(x)
+#define __SCN32LEAST(x) __LEAST32 __STRINGIFY(x)
+#define __PRI32FAST(x) __FAST32 __STRINGIFY(x)
+#define __SCN32FAST(x) __FAST32 __STRINGIFY(x)
+
+#define PRId32		__PRI32(d)
+#define PRIi32		__PRI32(i)
+#define PRIo32		__PRI32(o)
+#define PRIu32		__PRI32(u)
+#define PRIx32		__PRI32(x)
+#define PRIX32		__PRI32(X)
+
+#define SCNd32		__SCN32(d)
+#define SCNi32		__SCN32(i)
+#define SCNo32		__SCN32(o)
+#define SCNu32		__SCN32(u)
+#define SCNx32		__SCN32(x)
+
+
+#define PRIdLEAST32	__PRI32LEAST(d)
+#define PRIiLEAST32	__PRI32LEAST(i)
+#define PRIoLEAST32	__PRI32LEAST(o)
+#define PRIuLEAST32	__PRI32LEAST(u)
+#define PRIxLEAST32	__PRI32LEAST(x)
+#define PRIXLEAST32	__PRI32LEAST(X)
+
+#define SCNdLEAST32	__SCN32LEAST(d)
+#define SCNiLEAST32	__SCN32LEAST(i)
+#define SCNoLEAST32	__SCN32LEAST(o)
+#define SCNuLEAST32	__SCN32LEAST(u)
+#define SCNxLEAST32	__SCN32LEAST(x)
+
+
+#define PRIdFAST32	__PRI32FAST(d)
+#define PRIiFAST32	__PRI32FAST(i)
+#define PRIoFAST32	__PRI32FAST(o)
+#define PRIuFAST32	__PRI32FAST(u)
+#define PRIxFAST32	__PRI32FAST(x)
+#define PRIXFAST32	__PRI32FAST(X)
+
+#define SCNdFAST32	__SCN32FAST(d)
+#define SCNiFAST32	__SCN32FAST(i)
+#define SCNoFAST32	__SCN32FAST(o)
+#define SCNuFAST32	__SCN32FAST(u)
+#define SCNxFAST32	__SCN32FAST(x)
+
+
+/* 64-bit types */
+#define __PRI64(x) __INT64 __STRINGIFY(x)
+#define __SCN64(x) __INT64 __STRINGIFY(x)
+
+#define __PRI64LEAST(x) __LEAST64 __STRINGIFY(x)
+#define __SCN64LEAST(x) __LEAST64 __STRINGIFY(x)
+#define __PRI64FAST(x) __FAST64 __STRINGIFY(x)
+#define __SCN64FAST(x) __FAST64 __STRINGIFY(x)
+
+#if __int64_t_defined
+#define PRId64		__PRI64(d)
+#define PRIi64		__PRI64(i)
+#define PRIo64		__PRI64(o)
+#define PRIu64		__PRI64(u)
+#define PRIx64		__PRI64(x)
+#define PRIX64		__PRI64(X)
+
+#define SCNd64		__SCN64(d)
+#define SCNi64		__SCN64(i)
+#define SCNo64		__SCN64(o)
+#define SCNu64		__SCN64(u)
+#define SCNx64		__SCN64(x)
+#endif
+
+#if __int_least64_t_defined
+#define PRIdLEAST64	__PRI64LEAST(d)
+#define PRIiLEAST64	__PRI64LEAST(i)
+#define PRIoLEAST64	__PRI64LEAST(o)
+#define PRIuLEAST64	__PRI64LEAST(u)
+#define PRIxLEAST64	__PRI64LEAST(x)
+#define PRIXLEAST64	__PRI64LEAST(X)
+
+#define SCNdLEAST64	__SCN64LEAST(d)
+#define SCNiLEAST64	__SCN64LEAST(i)
+#define SCNoLEAST64	__SCN64LEAST(o)
+#define SCNuLEAST64	__SCN64LEAST(u)
+#define SCNxLEAST64	__SCN64LEAST(x)
+#endif
+
+#if __int_fast64_t_defined
+#define PRIdFAST64	__PRI64FAST(d)
+#define PRIiFAST64	__PRI64FAST(i)
+#define PRIoFAST64	__PRI64FAST(o)
+#define PRIuFAST64	__PRI64FAST(u)
+#define PRIxFAST64	__PRI64FAST(x)
+#define PRIXFAST64	__PRI64FAST(X)
+
+#define SCNdFAST64	__SCN64FAST(d)
+#define SCNiFAST64	__SCN64FAST(i)
+#define SCNoFAST64	__SCN64FAST(o)
+#define SCNuFAST64	__SCN64FAST(u)
+#define SCNxFAST64	__SCN64FAST(x)
+#endif
+
+/* max-bit types */
+#if __have_long64
+#define __PRIMAX(x) __STRINGIFY(l##x)
+#define __SCNMAX(x) __STRINGIFY(l##x)
+#elif __have_longlong64
+#define __PRIMAX(x) __STRINGIFY(ll##x)
+#define __SCNMAX(x) __STRINGIFY(ll##x)
+#else
+#define __PRIMAX(x) __STRINGIFY(x)
+#define __SCNMAX(x) __STRINGIFY(x)
+#endif
+
+#define PRIdMAX		__PRIMAX(d)
+#define PRIiMAX		__PRIMAX(i)
+#define PRIoMAX		__PRIMAX(o)
+#define PRIuMAX		__PRIMAX(u)
+#define PRIxMAX		__PRIMAX(x)
+#define PRIXMAX		__PRIMAX(X)
+
+#define SCNdMAX		__SCNMAX(d)
+#define SCNiMAX		__SCNMAX(i)
+#define SCNoMAX		__SCNMAX(o)
+#define SCNuMAX		__SCNMAX(u)
+#define SCNxMAX		__SCNMAX(x)
+
+/* ptr types */
+#if defined (_INTPTR_EQ_LONGLONG)
+# define __PRIPTR(x) __STRINGIFY(ll##x)
+# define __SCNPTR(x) __STRINGIFY(ll##x)
+#elif defined (_INTPTR_EQ_LONG)
+# define __PRIPTR(x) __STRINGIFY(l##x)
+# define __SCNPTR(x) __STRINGIFY(l##x)
+#else
+# define __PRIPTR(x) __STRINGIFY(x)
+# define __SCNPTR(x) __STRINGIFY(x)
+#endif
+
+#define PRIdPTR		__PRIPTR(d)
+#define PRIiPTR		__PRIPTR(i)
+#define PRIoPTR		__PRIPTR(o)
+#define PRIuPTR		__PRIPTR(u)
+#define PRIxPTR		__PRIPTR(x)
+#define PRIXPTR		__PRIPTR(X)
+
+#define SCNdPTR		__SCNPTR(d)
+#define SCNiPTR		__SCNPTR(i)
+#define SCNoPTR		__SCNPTR(o)
+#define SCNuPTR		__SCNPTR(u)
+#define SCNxPTR		__SCNPTR(x)
+
+
+typedef struct {
+  intmax_t	quot;
+  intmax_t	rem;
+} imaxdiv_t;
+
+struct _reent;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern intmax_t  imaxabs(intmax_t j);
+extern imaxdiv_t imaxdiv(intmax_t numer, intmax_t denomer);
+extern intmax_t  strtoimax(const char *__restrict, char **__restrict, int);
+extern intmax_t  _strtoimax_r(struct _reent *, const char *__restrict, char **__restrict, int);
+extern uintmax_t strtoumax(const char *__restrict, char **__restrict, int);
+extern uintmax_t _strtoumax_r(struct _reent *, const char *__restrict, char **__restrict, int);
+extern intmax_t  wcstoimax(const wchar_t *__restrict, wchar_t **__restrict, int);
+extern intmax_t  _wcstoimax_r(struct _reent *, const wchar_t *__restrict, wchar_t **__restrict, int);
+extern uintmax_t wcstoumax(const wchar_t *__restrict, wchar_t **__restrict, int);
+extern uintmax_t _wcstoumax_r(struct _reent *, const wchar_t *__restrict, wchar_t **__restrict, int);
+
+#if __BSD_VISIBLE
+extern intmax_t  strtoimax_l(const char *__restrict, char **_restrict, int, locale_t);
+extern uintmax_t strtoumax_l(const char *__restrict, char **_restrict, int, locale_t);
+extern intmax_t  wcstoimax_l(const wchar_t *__restrict, wchar_t **_restrict, int, locale_t);
+extern uintmax_t wcstoumax_l(const wchar_t *__restrict, wchar_t **_restrict, int, locale_t);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

src/include/machine/_default_types.h

@@ -0,0 +1,250 @@
+/*
+ *  $Id$
+ */
+
+#ifndef _MACHINE__DEFAULT_TYPES_H
+#define _MACHINE__DEFAULT_TYPES_H
+
+#include <sys/features.h>
+
+/*
+ * Guess on types by examining *_MIN / *_MAX defines.
+ */
+#if __GNUC_PREREQ (3, 3)
+/* GCC >= 3.3.0 has __<val>__ implicitly defined. */
+#define __EXP(x) __##x##__
+#else
+/* Fall back to POSIX versions from <limits.h> */
+#define __EXP(x) x
+#include <limits.h>
+#endif
+
+/* Check if "long long" is 64bit wide */
+/* Modern GCCs provide __LONG_LONG_MAX__, SUSv3 wants LLONG_MAX */
+#if ( defined(__LONG_LONG_MAX__) && (__LONG_LONG_MAX__ > 0x7fffffff) ) \
+  || ( defined(LLONG_MAX) && (LLONG_MAX > 0x7fffffff) )
+#define __have_longlong64 1
+#endif
+
+/* Check if "long" is 64bit or 32bit wide */
+#if __EXP(LONG_MAX) > 0x7fffffff
+#define __have_long64 1
+#elif __EXP(LONG_MAX) == 0x7fffffff && !defined(__SPU__)
+#define __have_long32 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __INT8_TYPE__
+typedef __INT8_TYPE__ __int8_t;
+#ifdef __UINT8_TYPE__
+typedef __UINT8_TYPE__ __uint8_t;
+#else
+typedef unsigned __INT8_TYPE__ __uint8_t;
+#endif
+#define ___int8_t_defined 1
+#elif __EXP(SCHAR_MAX) == 0x7f
+typedef signed char __int8_t ;
+typedef unsigned char __uint8_t ;
+#define ___int8_t_defined 1
+#endif
+
+#ifdef __INT16_TYPE__
+typedef __INT16_TYPE__ __int16_t;
+#ifdef __UINT16_TYPE__
+typedef __UINT16_TYPE__ __uint16_t;
+#else
+typedef unsigned __INT16_TYPE__ __uint16_t;
+#endif
+#define ___int16_t_defined 1
+#elif __EXP(INT_MAX) == 0x7fff
+typedef signed int __int16_t;
+typedef unsigned int __uint16_t;
+#define ___int16_t_defined 1
+#elif __EXP(SHRT_MAX) == 0x7fff
+typedef signed short __int16_t;
+typedef unsigned short __uint16_t;
+#define ___int16_t_defined 1
+#elif __EXP(SCHAR_MAX) == 0x7fff
+typedef signed char __int16_t;
+typedef unsigned char __uint16_t;
+#define ___int16_t_defined 1
+#endif
+
+#ifdef __INT32_TYPE__
+typedef __INT32_TYPE__ __int32_t;
+#ifdef __UINT32_TYPE__
+typedef __UINT32_TYPE__ __uint32_t;
+#else
+typedef unsigned __INT32_TYPE__ __uint32_t;
+#endif
+#define ___int32_t_defined 1
+#elif __EXP(INT_MAX) == 0x7fffffffL
+typedef signed int __int32_t;
+typedef unsigned int __uint32_t;
+#define ___int32_t_defined 1
+#elif __EXP(LONG_MAX) == 0x7fffffffL
+typedef signed long __int32_t;
+typedef unsigned long __uint32_t;
+#define ___int32_t_defined 1
+#elif __EXP(SHRT_MAX) == 0x7fffffffL
+typedef signed short __int32_t;
+typedef unsigned short __uint32_t;
+#define ___int32_t_defined 1
+#elif __EXP(SCHAR_MAX) == 0x7fffffffL
+typedef signed char __int32_t;
+typedef unsigned char __uint32_t;
+#define ___int32_t_defined 1
+#endif
+
+#ifdef __INT64_TYPE__
+typedef __INT64_TYPE__ __int64_t;
+#ifdef __UINT64_TYPE__
+typedef __UINT64_TYPE__ __uint64_t;
+#else
+typedef unsigned __INT64_TYPE__ __uint64_t;
+#endif
+#define ___int64_t_defined 1
+#elif __EXP(LONG_MAX) > 0x7fffffff
+typedef signed long __int64_t;
+typedef unsigned long __uint64_t;
+#define ___int64_t_defined 1
+
+/* GCC has __LONG_LONG_MAX__ */
+#elif  defined(__LONG_LONG_MAX__) && (__LONG_LONG_MAX__ > 0x7fffffff)
+typedef signed long long __int64_t;
+typedef unsigned long long __uint64_t;
+#define ___int64_t_defined 1
+
+/* POSIX mandates LLONG_MAX in <limits.h> */
+#elif  defined(LLONG_MAX) && (LLONG_MAX > 0x7fffffff)
+typedef signed long long __int64_t;
+typedef unsigned long long __uint64_t;
+#define ___int64_t_defined 1
+
+#elif  __EXP(INT_MAX) > 0x7fffffff
+typedef signed int __int64_t;
+typedef unsigned int __uint64_t;
+#define ___int64_t_defined 1
+#endif
+
+#ifdef __INT_LEAST8_TYPE__
+typedef __INT_LEAST8_TYPE__ __int_least8_t;
+#ifdef __UINT_LEAST8_TYPE__
+typedef __UINT_LEAST8_TYPE__ __uint_least8_t;
+#else
+typedef unsigned __INT_LEAST8_TYPE__ __uint_least8_t;
+#endif
+#define ___int_least8_t_defined 1
+#elif defined(___int8_t_defined)
+typedef __int8_t __int_least8_t;
+typedef __uint8_t __uint_least8_t;
+#define ___int_least8_t_defined 1
+#elif defined(___int16_t_defined)
+typedef __int16_t __int_least8_t;
+typedef __uint16_t __uint_least8_t;
+#define ___int_least8_t_defined 1
+#elif defined(___int32_t_defined)
+typedef __int32_t __int_least8_t;
+typedef __uint32_t __uint_least8_t;
+#define ___int_least8_t_defined 1
+#elif defined(___int64_t_defined)
+typedef __int64_t __int_least8_t;
+typedef __uint64_t __uint_least8_t;
+#define ___int_least8_t_defined 1
+#endif
+
+#ifdef __INT_LEAST16_TYPE__
+typedef __INT_LEAST16_TYPE__ __int_least16_t;
+#ifdef __UINT_LEAST16_TYPE__
+typedef __UINT_LEAST16_TYPE__ __uint_least16_t;
+#else
+typedef unsigned __INT_LEAST16_TYPE__ __uint_least16_t;
+#endif
+#define ___int_least16_t_defined 1
+#elif defined(___int16_t_defined)
+typedef __int16_t __int_least16_t;
+typedef __uint16_t __uint_least16_t;
+#define ___int_least16_t_defined 1
+#elif defined(___int32_t_defined)
+typedef __int32_t __int_least16_t;
+typedef __uint32_t __uint_least16_t;
+#define ___int_least16_t_defined 1
+#elif defined(___int64_t_defined)
+typedef __int64_t __int_least16_t;
+typedef __uint64_t __uint_least16_t;
+#define ___int_least16_t_defined 1
+#endif
+
+#ifdef __INT_LEAST32_TYPE__
+typedef __INT_LEAST32_TYPE__ __int_least32_t;
+#ifdef __UINT_LEAST32_TYPE__
+typedef __UINT_LEAST32_TYPE__ __uint_least32_t;
+#else
+typedef unsigned __INT_LEAST32_TYPE__ __uint_least32_t;
+#endif
+#define ___int_least32_t_defined 1
+#elif defined(___int32_t_defined)
+typedef __int32_t __int_least32_t;
+typedef __uint32_t __uint_least32_t;
+#define ___int_least32_t_defined 1
+#elif defined(___int64_t_defined)
+typedef __int64_t __int_least32_t;
+typedef __uint64_t __uint_least32_t;
+#define ___int_least32_t_defined 1
+#endif
+
+#ifdef __INT_LEAST64_TYPE__
+typedef __INT_LEAST64_TYPE__ __int_least64_t;
+#ifdef __UINT_LEAST64_TYPE__
+typedef __UINT_LEAST64_TYPE__ __uint_least64_t;
+#else
+typedef unsigned __INT_LEAST64_TYPE__ __uint_least64_t;
+#endif
+#define ___int_least64_t_defined 1
+#elif defined(___int64_t_defined)
+typedef __int64_t __int_least64_t;
+typedef __uint64_t __uint_least64_t;
+#define ___int_least64_t_defined 1
+#endif
+
+#if defined(__INTMAX_TYPE__)
+typedef __INTMAX_TYPE__ __intmax_t;
+#elif __have_longlong64
+typedef signed long long __intmax_t;
+#else
+typedef signed long __intmax_t;
+#endif
+
+#if defined(__UINTMAX_TYPE__)
+typedef __UINTMAX_TYPE__ __uintmax_t;
+#elif __have_longlong64
+typedef unsigned long long __uintmax_t;
+#else
+typedef unsigned long __uintmax_t;
+#endif
+
+#ifdef __INTPTR_TYPE__
+typedef __INTPTR_TYPE__ __intptr_t;
+#ifdef __UINTPTR_TYPE__
+typedef __UINTPTR_TYPE__ __uintptr_t;
+#else
+typedef unsigned __INTPTR_TYPE__ __uintptr_t;
+#endif
+#elif defined(__PTRDIFF_TYPE__)
+typedef __PTRDIFF_TYPE__ __intptr_t;
+typedef unsigned __PTRDIFF_TYPE__ __uintptr_t;
+#else
+typedef long __intptr_t;
+typedef unsigned long __uintptr_t;
+#endif
+
+#undef __EXP
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MACHINE__DEFAULT_TYPES_H */

src/include/machine/_endian.h

@@ -0,0 +1,39 @@
+/* ARM configuration file.
+   Copyright (c) 2015 ARM Ltd.  All rights reserved.
+
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions
+   are met:
+   1. Redistributions of source code must retain the above copyright
+      notice, this list of conditions and the following disclaimer.
+   2. Redistributions in binary form must reproduce the above copyright
+      notice, this list of conditions and the following disclaimer in the
+      documentation and/or other materials provided with the distribution.
+   3. The name of the company may not be used to endorse or promote
+      products derived from this software without specific prior written
+      permission.
+
+   THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
+   WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+   MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+   IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+   TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+   PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+   LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+   NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+   SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+#ifndef __MACHINE_ENDIAN_H__
+#error "must be included via <machine/endian.h>"
+#endif /* !__MACHINE_ENDIAN_H__ */
+
+#define	_LITTLE_ENDIAN	1234
+#define	_BIG_ENDIAN	4321
+#define	_PDP_ENDIAN	3412
+
+#ifdef __ARMEB__
+#define	_BYTE_ORDER	_BIG_ENDIAN
+#else
+#define	_BYTE_ORDER	_LITTLE_ENDIAN
+#endif

src/include/machine/_types.h

@@ -0,0 +1,8 @@
+/*
+ *  $Id$
+ */
+
+#ifndef _MACHINE__TYPES_H
+#define _MACHINE__TYPES_H
+#include <machine/_default_types.h>
+#endif

src/include/machine/endian.h

@@ -0,0 +1,69 @@
+#ifndef __MACHINE_ENDIAN_H__
+#define	__MACHINE_ENDIAN_H__
+
+#include <sys/cdefs.h>
+#include <sys/_types.h>
+#include <machine/_endian.h>
+
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+#define	_QUAD_HIGHWORD	1
+#define	_QUAD_LOWWORD	0
+#else
+#define	_QUAD_HIGHWORD	0
+#define	_QUAD_LOWWORD	1
+#endif
+
+#if __BSD_VISIBLE
+#define	LITTLE_ENDIAN	_LITTLE_ENDIAN
+#define	BIG_ENDIAN	_BIG_ENDIAN
+#define	PDP_ENDIAN	_PDP_ENDIAN
+#define	BYTE_ORDER	_BYTE_ORDER
+#endif
+
+#ifdef __GNUC__
+#define	__bswap16(_x)	__builtin_bswap16(_x)
+#define	__bswap32(_x)	__builtin_bswap32(_x)
+#define	__bswap64(_x)	__builtin_bswap64(_x)
+#else /* __GNUC__ */
+static __inline __uint16_t
+__bswap16(__uint16_t _x)
+{
+
+	return ((__uint16_t)((_x >> 8) | ((_x << 8) & 0xff00)));
+}
+
+static __inline __uint32_t
+__bswap32(__uint32_t _x)
+{
+
+	return ((__uint32_t)((_x >> 24) | ((_x >> 8) & 0xff00) |
+	    ((_x << 8) & 0xff0000) | ((_x << 24) & 0xff000000)));
+}
+
+static __inline __uint64_t
+__bswap64(__uint64_t _x)
+{
+
+	return ((__uint64_t)((_x >> 56) | ((_x >> 40) & 0xff00) |
+	    ((_x >> 24) & 0xff0000) | ((_x >> 8) & 0xff000000) |
+	    ((_x << 8) & ((__uint64_t)0xff << 32)) |
+	    ((_x << 24) & ((__uint64_t)0xff << 40)) |
+	    ((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56))));
+}
+#endif /* !__GNUC__ */
+
+#ifndef __machine_host_to_from_network_defined
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+#define	__htonl(_x)	__bswap32(_x)
+#define	__htons(_x)	__bswap16(_x)
+#define	__ntohl(_x)	__bswap32(_x)
+#define	__ntohs(_x)	__bswap16(_x)
+#else
+#define	__htonl(_x)	((__uint32_t)(_x))
+#define	__htons(_x)	((__uint16_t)(_x))
+#define	__ntohl(_x)	((__uint32_t)(_x))
+#define	__ntohs(_x)	((__uint16_t)(_x))
+#endif
+#endif /* __machine_host_to_from_network_defined */
+
+#endif /* __MACHINE_ENDIAN_H__ */

src/include/machine/ieeefp.h

@@ -0,0 +1,475 @@
+#ifndef __IEEE_BIG_ENDIAN
+#ifndef __IEEE_LITTLE_ENDIAN
+
+/* This file can define macros to choose variations of the IEEE float
+   format:
+
+   _FLT_LARGEST_EXPONENT_IS_NORMAL
+
+	Defined if the float format uses the largest exponent for finite
+	numbers rather than NaN and infinity representations.  Such a
+	format cannot represent NaNs or infinities at all, but it's FLT_MAX
+	is twice the IEEE value.
+
+   _FLT_NO_DENORMALS
+
+	Defined if the float format does not support IEEE denormals.  Every
+	float with a zero exponent is taken to be a zero representation.
+ 
+   ??? At the moment, there are no equivalent macros above for doubles and
+   the macros are not fully supported by --enable-newlib-hw-fp.
+
+   __IEEE_BIG_ENDIAN
+
+        Defined if the float format is big endian.  This is mutually exclusive
+        with __IEEE_LITTLE_ENDIAN.
+
+   __IEEE_LITTLE_ENDIAN
+ 
+        Defined if the float format is little endian.  This is mutually exclusive
+        with __IEEE_BIG_ENDIAN.
+
+   Note that one of __IEEE_BIG_ENDIAN or __IEEE_LITTLE_ENDIAN must be specified for a
+   platform or error will occur.
+
+   __IEEE_BYTES_LITTLE_ENDIAN
+
+        This flag is used in conjunction with __IEEE_BIG_ENDIAN to describe a situation 
+	whereby multiple words of an IEEE floating point are in big endian order, but the
+	words themselves are little endian with respect to the bytes.
+
+   _DOUBLE_IS_32BITS 
+
+        This is used on platforms that support double by using the 32-bit IEEE
+        float type.
+
+   _FLOAT_ARG
+
+        This represents what type a float arg is passed as.  It is used when the type is
+        not promoted to double.
+	
+
+   __OBSOLETE_MATH_DEFAULT
+
+	Default value for __OBSOLETE_MATH if that's not set by the user.
+	It should be set here based on predefined feature macros.
+
+   __OBSOLETE_MATH
+
+	If set to 1 then some new math code will be disabled and older libm
+	code will be used instead.  This is necessary because the new math
+	code does not support all targets, it assumes that the toolchain has
+	ISO C99 support (hexfloat literals, standard fenv semantics), the
+	target has IEEE-754 conforming binary32 float and binary64 double
+	(not mixed endian) representation, standard SNaN representation,
+	double and single precision arithmetics has similar latency and it
+	has no legacy SVID matherr support, only POSIX errno and fenv
+	exception based error handling.
+*/
+
+#if (defined(__arm__) || defined(__thumb__)) && !defined(__MAVERICK__)
+/* ARM traditionally used big-endian words; and within those words the
+   byte ordering was big or little endian depending upon the target.
+   Modern floating-point formats are naturally ordered; in this case
+   __VFP_FP__ will be defined, even if soft-float.  */
+#ifdef __VFP_FP__
+# ifdef __ARMEL__
+#  define __IEEE_LITTLE_ENDIAN
+# else
+#  define __IEEE_BIG_ENDIAN
+# endif
+# if __ARM_FP & 0x8
+#  define __OBSOLETE_MATH_DEFAULT 0
+# endif
+#else
+# define __IEEE_BIG_ENDIAN
+# ifdef __ARMEL__
+#  define __IEEE_BYTES_LITTLE_ENDIAN
+# endif
+#endif
+#endif
+
+#if defined (__aarch64__)
+#if defined (__AARCH64EL__)
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#define __OBSOLETE_MATH_DEFAULT 0
+#endif
+
+#ifdef __epiphany__
+#define __IEEE_LITTLE_ENDIAN
+#define Sudden_Underflow 1
+#endif
+
+#ifdef __hppa__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __nds32__
+#ifdef __big_endian__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __SPU__
+#define __IEEE_BIG_ENDIAN
+
+#define isfinite(__y) \
+	(__extension__ ({int __cy; \
+		(sizeof (__y) == sizeof (float))  ? (1) : \
+		(__cy = fpclassify(__y)) != FP_INFINITE && __cy != FP_NAN;}))
+
+#define isinf(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isinfd(__x))
+#define isnan(__x) ((sizeof (__x) == sizeof (float))  ?  (0) : __isnand(__x))
+
+/*
+ * Macros for use in ieeefp.h. We can't just define the real ones here
+ * (like those above) as we have name space issues when this is *not*
+ * included via generic the ieeefp.h.
+ */
+#define __ieeefp_isnanf(x)	0
+#define __ieeefp_isinff(x)	0
+#define __ieeefp_finitef(x)	1
+#endif
+
+#ifdef __sparc__
+#ifdef __LITTLE_ENDIAN_DATA__
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#endif
+
+#if defined(__m68k__) || defined(__mc68000__)
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
+#define __IEEE_BIG_ENDIAN
+#ifdef __HAVE_SHORT_DOUBLE__
+# define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#if defined (__H8300__) || defined (__H8300H__) || defined (__H8300S__) || defined (__H8500__) || defined (__H8300SX__)
+#define __IEEE_BIG_ENDIAN
+#define _FLOAT_ARG float
+#define _DOUBLE_IS_32BITS
+#endif
+
+#if defined (__xc16x__) || defined (__xc16xL__) || defined (__xc16xS__)
+#define __IEEE_LITTLE_ENDIAN
+#define _FLOAT_ARG float
+#define _DOUBLE_IS_32BITS
+#endif
+
+
+#ifdef __sh__
+#ifdef __LITTLE_ENDIAN__
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#if defined(__SH2E__) || defined(__SH3E__) || defined(__SH4_SINGLE_ONLY__) || defined(__SH2A_SINGLE_ONLY__)
+#define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#ifdef _AM29K
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef _WIN32
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __i386__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __riscv
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __i960__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __lm32__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __M32R__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __nvptx__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#if defined(_C4x) || defined(_C3x)
+#define __IEEE_BIG_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __TMS320C6X__
+#ifdef _BIG_ENDIAN
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __TIC80__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __MIPSEL__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#ifdef __MIPSEB__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __MMIX__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __D30V__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+/* necv70 was __IEEE_LITTLE_ENDIAN. */
+
+#ifdef __W65__
+#define __IEEE_LITTLE_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#if defined(__Z8001__) || defined(__Z8002__)
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __m88k__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __mn10300__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __mn10200__
+#define __IEEE_LITTLE_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __v800
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __v850
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __D10V__
+#define __IEEE_BIG_ENDIAN
+#if __DOUBLE__ == 32
+#define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#ifdef __PPC__
+#if (defined(_BIG_ENDIAN) && _BIG_ENDIAN) || (defined(_AIX) && _AIX)
+#define __IEEE_BIG_ENDIAN
+#else
+#if (defined(_LITTLE_ENDIAN) && _LITTLE_ENDIAN) || (defined(__sun__) && __sun__) || (defined(_WIN32) && _WIN32)
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+#endif
+
+#ifdef __xstormy16__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __arc__
+#ifdef __big_endian__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __CRX__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __fr30__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __FT32__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __mcore__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __mt__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __frv__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __moxie__
+#ifdef __MOXIE_BIG_ENDIAN__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __ia64__
+#ifdef __BIG_ENDIAN__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __AVR__
+#define __IEEE_LITTLE_ENDIAN
+#define _DOUBLE_IS_32BITS
+#endif
+
+#if defined(__or1k__) || defined(__OR1K__) || defined(__OR1KND__)
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __IP2K__
+#define __IEEE_BIG_ENDIAN
+#define __SMALL_BITFIELDS
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __iq2000__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __MAVERICK__
+#ifdef __ARMEL__
+#  define __IEEE_LITTLE_ENDIAN
+#else  /* must be __ARMEB__ */
+#  define __IEEE_BIG_ENDIAN
+#endif /* __ARMEL__ */
+#endif /* __MAVERICK__ */
+
+#ifdef __m32c__
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS
+#endif
+
+#ifdef __CRIS__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __BFIN__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __x86_64__
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifdef __mep__
+#ifdef __LITTLE_ENDIAN__
+#define __IEEE_LITTLE_ENDIAN
+#else
+#define __IEEE_BIG_ENDIAN
+#endif
+#endif
+
+#ifdef __MICROBLAZE__
+#ifndef __MICROBLAZEEL__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+#endif
+
+#ifdef __MSP430__
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS	/* 16 Bit INT */
+#endif
+
+#ifdef __RL78__
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS	/* 16 Bit INT */
+#ifndef __RL78_64BIT_DOUBLES__
+#define _DOUBLE_IS_32BITS
+#endif
+#endif
+
+#ifdef __RX__
+
+#ifdef __RX_BIG_ENDIAN__
+#define __IEEE_BIG_ENDIAN
+#else
+#define __IEEE_LITTLE_ENDIAN
+#endif
+
+#ifndef __RX_64BIT_DOUBLES__
+#define _DOUBLE_IS_32BITS
+#endif
+
+#ifdef __RX_16BIT_INTS__
+#define __SMALL_BITFIELDS
+#endif
+
+#endif
+
+#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
+#define __IEEE_LITTLE_ENDIAN
+#define __SMALL_BITFIELDS	/* 16 Bit INT */
+#endif
+
+#ifdef __NIOS2__
+# ifdef __nios2_big_endian__
+#  define __IEEE_BIG_ENDIAN
+# else
+#  define __IEEE_LITTLE_ENDIAN
+# endif
+#endif
+
+#ifdef __VISIUM__
+#define __IEEE_BIG_ENDIAN
+#endif
+
+#ifdef __CYGWIN__
+#define __OBSOLETE_MATH_DEFAULT 0
+#endif
+
+#ifndef __OBSOLETE_MATH_DEFAULT
+/* Use old math code by default.  */
+#define __OBSOLETE_MATH_DEFAULT 1
+#endif
+#ifndef __OBSOLETE_MATH
+#define __OBSOLETE_MATH __OBSOLETE_MATH_DEFAULT
+#endif
+
+#ifndef __IEEE_BIG_ENDIAN
+#ifndef __IEEE_LITTLE_ENDIAN
+#error Endianess not declared!!
+#endif /* not __IEEE_LITTLE_ENDIAN */
+#endif /* not __IEEE_BIG_ENDIAN */
+
+#endif /* not __IEEE_LITTLE_ENDIAN */
+#endif /* not __IEEE_BIG_ENDIAN */
+

src/include/machine/stdlib.h

@@ -0,0 +1,8 @@
+#ifndef	_MACHSTDLIB_H_
+#define	_MACHSTDLIB_H_
+
+/* place holder so platforms may add stdlib.h extensions */
+
+#endif	/* _MACHSTDLIB_H_ */
+
+

src/include/machine/types.h

@@ -0,0 +1,7 @@
+/*
+ * Newlib targets may provide an own version of this file in their machine
+ * directory to add custom user types for <sys/types.h>.
+ */
+#ifndef _SYS_TYPES_H
+#error "must be included via <sys/types.h>"
+#endif /* !_SYS_TYPES_H */

src/include/newlib.h

@@ -0,0 +1,206 @@
+/* newlib.h.  Generated from newlib.hin by configure.  */
+/* newlib.hin.  Manually edited from the output of autoheader to
+   remove all PACKAGE_ macros which will collide with any user
+   package using newlib header files and having its own package name,
+   version, etc...  */
+#ifndef __NEWLIB_H__
+
+#define __NEWLIB_H__ 1
+
+/* EL/IX level */
+/* #undef _ELIX_LEVEL */
+
+/* Newlib version */
+#include <_newlib_version.h>
+
+/* C99 formats support (such as %a, %zu, ...) in IO functions like
+ * printf/scanf enabled */
+#define _WANT_IO_C99_FORMATS 1
+
+/* long long type support in IO functions like printf/scanf enabled */
+#define _WANT_IO_LONG_LONG 1
+
+/* Register application finalization function using atexit. */
+#define _WANT_REGISTER_FINI 1
+
+/* long double type support in IO functions like printf/scanf enabled */
+/* #undef _WANT_IO_LONG_DOUBLE */
+
+/* Positional argument support in printf functions enabled.  */
+/* #undef _WANT_IO_POS_ARGS */
+
+/* Optional reentrant struct support.  Used mostly on platforms with
+   very restricted storage.  */
+/* #undef _WANT_REENT_SMALL */
+
+/* Multibyte supported */
+/* #undef _MB_CAPABLE */
+
+/* MB_LEN_MAX */
+#define _MB_LEN_MAX 1
+
+/* ICONV enabled */
+/* #undef _ICONV_ENABLED */
+
+/* Enable ICONV external CCS files loading capabilities */
+/* #undef _ICONV_ENABLE_EXTERNAL_CCS */
+
+/* Define if the linker supports .preinit_array/.init_array/.fini_array
+ * sections.  */
+#define HAVE_INITFINI_ARRAY 1
+
+/* True if atexit() may dynamically allocate space for cleanup
+   functions.  */
+#define _ATEXIT_DYNAMIC_ALLOC 1
+
+/* True if long double supported.  */
+#define _HAVE_LONG_DOUBLE 1
+
+/* Define if compiler supports -fno-tree-loop-distribute-patterns. */
+#define _HAVE_CC_INHIBIT_LOOP_TO_LIBCALL 1
+
+/* True if long double supported and it is equal to double.  */
+#define _LDBL_EQ_DBL 1
+ 
+/* Define if ivo supported in streamio.  */
+#define _FVWRITE_IN_STREAMIO 1
+
+/* Define if fseek functions support seek optimization.  */
+#define _FSEEK_OPTIMIZATION 1
+
+/* Define if wide char orientation is supported.  */
+#define _WIDE_ORIENT 1
+
+/* Define if unbuffered stream file optimization is supported.  */
+#define _UNBUF_STREAM_OPT 1
+
+/* Define if lite version of exit supported.  */
+/* #undef _LITE_EXIT */
+
+/* Define if declare atexit data as global.  */
+/* #undef _REENT_GLOBAL_ATEXIT */
+
+/* Define to move the stdio stream FILE objects out of struct _reent and make
+   them global.  The stdio stream pointers of struct _reent are initialized to
+   point to the global stdio FILE stream objects. */
+/* #undef _WANT_REENT_GLOBAL_STDIO_STREAMS */
+
+/* Define if small footprint nano-formatted-IO implementation used.  */
+/* #undef _NANO_FORMATTED_IO */
+
+/* Define if using retargetable functions for default lock routines.  */
+#define _RETARGETABLE_LOCKING 1
+
+/* Define to use type long for time_t.  */
+/* #undef _WANT_USE_LONG_TIME_T */
+
+/*
+ * Iconv encodings enabled ("to" direction)
+ */
+/* #undef _ICONV_TO_ENCODING_BIG5 */
+/* #undef _ICONV_TO_ENCODING_CP775 */
+/* #undef _ICONV_TO_ENCODING_CP850 */
+/* #undef _ICONV_TO_ENCODING_CP852 */
+/* #undef _ICONV_TO_ENCODING_CP855 */
+/* #undef _ICONV_TO_ENCODING_CP866 */
+/* #undef _ICONV_TO_ENCODING_EUC_JP */
+/* #undef _ICONV_TO_ENCODING_EUC_TW */
+/* #undef _ICONV_TO_ENCODING_EUC_KR */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_1 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_10 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_11 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_13 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_14 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_15 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_2 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_3 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_4 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_5 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_6 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_7 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_8 */
+/* #undef _ICONV_TO_ENCODING_ISO_8859_9 */
+/* #undef _ICONV_TO_ENCODING_ISO_IR_111 */
+/* #undef _ICONV_TO_ENCODING_KOI8_R */
+/* #undef _ICONV_TO_ENCODING_KOI8_RU */
+/* #undef _ICONV_TO_ENCODING_KOI8_U */
+/* #undef _ICONV_TO_ENCODING_KOI8_UNI */
+/* #undef _ICONV_TO_ENCODING_UCS_2 */
+/* #undef _ICONV_TO_ENCODING_UCS_2_INTERNAL */
+/* #undef _ICONV_TO_ENCODING_UCS_2BE */
+/* #undef _ICONV_TO_ENCODING_UCS_2LE */
+/* #undef _ICONV_TO_ENCODING_UCS_4 */
+/* #undef _ICONV_TO_ENCODING_UCS_4_INTERNAL */
+/* #undef _ICONV_TO_ENCODING_UCS_4BE */
+/* #undef _ICONV_TO_ENCODING_UCS_4LE */
+/* #undef _ICONV_TO_ENCODING_US_ASCII */
+/* #undef _ICONV_TO_ENCODING_UTF_16 */
+/* #undef _ICONV_TO_ENCODING_UTF_16BE */
+/* #undef _ICONV_TO_ENCODING_UTF_16LE */
+/* #undef _ICONV_TO_ENCODING_UTF_8 */
+/* #undef _ICONV_TO_ENCODING_WIN_1250 */
+/* #undef _ICONV_TO_ENCODING_WIN_1251 */
+/* #undef _ICONV_TO_ENCODING_WIN_1252 */
+/* #undef _ICONV_TO_ENCODING_WIN_1253 */
+/* #undef _ICONV_TO_ENCODING_WIN_1254 */
+/* #undef _ICONV_TO_ENCODING_WIN_1255 */
+/* #undef _ICONV_TO_ENCODING_WIN_1256 */
+/* #undef _ICONV_TO_ENCODING_WIN_1257 */
+/* #undef _ICONV_TO_ENCODING_WIN_1258 */
+
+/*
+ * Iconv encodings enabled ("from" direction)
+ */
+/* #undef _ICONV_FROM_ENCODING_BIG5 */
+/* #undef _ICONV_FROM_ENCODING_CP775 */
+/* #undef _ICONV_FROM_ENCODING_CP850 */
+/* #undef _ICONV_FROM_ENCODING_CP852 */
+/* #undef _ICONV_FROM_ENCODING_CP855 */
+/* #undef _ICONV_FROM_ENCODING_CP866 */
+/* #undef _ICONV_FROM_ENCODING_EUC_JP */
+/* #undef _ICONV_FROM_ENCODING_EUC_TW */
+/* #undef _ICONV_FROM_ENCODING_EUC_KR */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_1 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_10 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_11 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_13 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_14 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_15 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_2 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_3 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_4 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_5 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_6 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_7 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_8 */
+/* #undef _ICONV_FROM_ENCODING_ISO_8859_9 */
+/* #undef _ICONV_FROM_ENCODING_ISO_IR_111 */
+/* #undef _ICONV_FROM_ENCODING_KOI8_R */
+/* #undef _ICONV_FROM_ENCODING_KOI8_RU */
+/* #undef _ICONV_FROM_ENCODING_KOI8_U */
+/* #undef _ICONV_FROM_ENCODING_KOI8_UNI */
+/* #undef _ICONV_FROM_ENCODING_UCS_2 */
+/* #undef _ICONV_FROM_ENCODING_UCS_2_INTERNAL */
+/* #undef _ICONV_FROM_ENCODING_UCS_2BE */
+/* #undef _ICONV_FROM_ENCODING_UCS_2LE */
+/* #undef _ICONV_FROM_ENCODING_UCS_4 */
+/* #undef _ICONV_FROM_ENCODING_UCS_4_INTERNAL */
+/* #undef _ICONV_FROM_ENCODING_UCS_4BE */
+/* #undef _ICONV_FROM_ENCODING_UCS_4LE */
+/* #undef _ICONV_FROM_ENCODING_US_ASCII */
+/* #undef _ICONV_FROM_ENCODING_UTF_16 */
+/* #undef _ICONV_FROM_ENCODING_UTF_16BE */
+/* #undef _ICONV_FROM_ENCODING_UTF_16LE */
+/* #undef _ICONV_FROM_ENCODING_UTF_8 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1250 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1251 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1252 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1253 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1254 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1255 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1256 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1257 */
+/* #undef _ICONV_FROM_ENCODING_WIN_1258 */
+
+#endif /* !__NEWLIB_H__ */
+

src/include/printf.h

@@ -0,0 +1,117 @@
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+//             2014-2019, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on
+//        embedded systems with a very limited resources.
+//        Use this instead of bloated standard/newlib printf.
+//        These routines are thread safe and reentrant.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#ifndef _PRINTF_H_
+#define _PRINTF_H_
+
+#include <stdarg.h>
+#include <stddef.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Output a character to a custom device like UART, used by the printf() function
+ * This function is declared here only. You have to write your custom implementation somewhere
+ * \param character Character to output
+ */
+void _putchar(char character);
+
+
+/**
+ * Tiny printf implementation
+ * You have to implement _putchar if you use printf()
+ * To avoid conflicts with the regular printf() API it is overridden by macro defines
+ * and internal underscore-appended functions like printf_() are used
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are written into the array, not counting the terminating null character
+ */
+#define printf printf_
+#define __printf__ printf_
+int printf_(const char* format, ...);
+
+
+/**
+ * Tiny sprintf implementation
+ * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD!
+ * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output!
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ */
+#define sprintf sprintf_
+int sprintf_(char* buffer, const char* format, ...);
+
+
+/**
+ * Tiny snprintf/vsnprintf implementation
+ * \param buffer A pointer to the buffer where to store the formatted string
+ * \param count The maximum number of characters to store in the buffer, including a terminating null character
+ * \param format A string that specifies the format of the output
+ * \param va A value identifying a variable arguments list
+ * \return The number of characters that COULD have been written into the buffer, not counting the terminating
+ *         null character. A value equal or larger than count indicates truncation. Only when the returned value
+ *         is non-negative and less than count, the string has been completely written.
+ */
+#define snprintf  snprintf_
+#define vsnprintf vsnprintf_
+int  snprintf_(char* buffer, size_t count, const char* format, ...);
+int vsnprintf_(char* buffer, size_t count, const char* format, va_list va);
+
+
+/**
+ * Tiny vprintf implementation
+ * \param format A string that specifies the format of the output
+ * \param va A value identifying a variable arguments list
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ */
+#define vprintf vprintf_
+int vprintf_(const char* format, va_list va);
+
+
+/**
+ * printf with output function
+ * You may use this as dynamic alternative to printf() with its fixed _putchar() output
+ * \param out An output function which takes one character and an argument pointer
+ * \param arg An argument pointer for user data passed to output function
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are sent to the output function, not counting the terminating null character
+ */
+int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  // _PRINTF_H_

src/include/stdint.h

@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2004, 2005 by
+ * Ralf Corsepius, Ulm/Germany. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+#ifndef _STDINT_H
+#define _STDINT_H
+
+#include <machine/_default_types.h>
+#include <sys/_intsup.h>
+#include <sys/_stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef ___int_least8_t_defined
+typedef __int_least8_t int_least8_t;
+typedef __uint_least8_t uint_least8_t;
+#define __int_least8_t_defined 1
+#endif
+
+#ifdef ___int_least16_t_defined
+typedef __int_least16_t int_least16_t;
+typedef __uint_least16_t uint_least16_t;
+#define __int_least16_t_defined 1
+#endif
+
+#ifdef ___int_least32_t_defined
+typedef __int_least32_t int_least32_t;
+typedef __uint_least32_t uint_least32_t;
+#define __int_least32_t_defined 1
+#endif
+
+#ifdef ___int_least64_t_defined
+typedef __int_least64_t int_least64_t;
+typedef __uint_least64_t uint_least64_t;
+#define __int_least64_t_defined 1
+#endif
+
+/*
+ * Fastest minimum-width integer types
+ *
+ * Assume int to be the fastest type for all types with a width 
+ * less than __INT_MAX__ rsp. INT_MAX
+ */
+#ifdef __INT_FAST8_TYPE__
+  typedef __INT_FAST8_TYPE__ int_fast8_t;
+  typedef __UINT_FAST8_TYPE__ uint_fast8_t;
+#define __int_fast8_t_defined 1
+#elif __STDINT_EXP(INT_MAX) >= 0x7f
+  typedef signed int int_fast8_t;
+  typedef unsigned int uint_fast8_t;
+#define __int_fast8_t_defined 1
+#endif
+
+#ifdef __INT_FAST16_TYPE__
+  typedef __INT_FAST16_TYPE__ int_fast16_t;
+  typedef __UINT_FAST16_TYPE__ uint_fast16_t;
+#define __int_fast16_t_defined 1
+#elif __STDINT_EXP(INT_MAX) >= 0x7fff
+  typedef signed int int_fast16_t;
+  typedef unsigned int uint_fast16_t;
+#define __int_fast16_t_defined 1
+#endif
+
+#ifdef __INT_FAST32_TYPE__
+  typedef __INT_FAST32_TYPE__ int_fast32_t;
+  typedef __UINT_FAST32_TYPE__ uint_fast32_t;
+#define __int_fast32_t_defined 1
+#elif __STDINT_EXP(INT_MAX) >= 0x7fffffff
+  typedef signed int int_fast32_t;
+  typedef unsigned int uint_fast32_t;
+#define __int_fast32_t_defined 1
+#endif
+
+#ifdef __INT_FAST64_TYPE__
+  typedef __INT_FAST64_TYPE__ int_fast64_t;
+  typedef __UINT_FAST64_TYPE__ uint_fast64_t;
+#define __int_fast64_t_defined 1
+#elif __STDINT_EXP(INT_MAX) > 0x7fffffff
+  typedef signed int int_fast64_t;
+  typedef unsigned int uint_fast64_t;
+#define __int_fast64_t_defined 1
+#endif
+
+/*
+ * Fall back to [u]int_least<N>_t for [u]int_fast<N>_t types
+ * not having been defined, yet.
+ * Leave undefined, if [u]int_least<N>_t should not be available.
+ */
+#if !__int_fast8_t_defined
+#if __int_least8_t_defined
+  typedef int_least8_t int_fast8_t;
+  typedef uint_least8_t uint_fast8_t;
+#define __int_fast8_t_defined 1
+#endif
+#endif
+
+#if !__int_fast16_t_defined
+#if __int_least16_t_defined
+  typedef int_least16_t int_fast16_t;
+  typedef uint_least16_t uint_fast16_t;
+#define __int_fast16_t_defined 1
+#endif
+#endif
+
+#if !__int_fast32_t_defined
+#if __int_least32_t_defined
+  typedef int_least32_t int_fast32_t;
+  typedef uint_least32_t uint_fast32_t;
+#define __int_fast32_t_defined 1
+#endif
+#endif
+
+#if !__int_fast64_t_defined
+#if __int_least64_t_defined
+  typedef int_least64_t int_fast64_t;
+  typedef uint_least64_t uint_fast64_t;
+#define __int_fast64_t_defined 1
+#endif
+#endif
+
+#ifdef __INTPTR_TYPE__
+#define INTPTR_MIN (-__INTPTR_MAX__ - 1)
+#define INTPTR_MAX (__INTPTR_MAX__)
+#define UINTPTR_MAX (__UINTPTR_MAX__)
+#elif defined(__PTRDIFF_TYPE__)
+#define INTPTR_MAX PTRDIFF_MAX
+#define INTPTR_MIN PTRDIFF_MIN
+#ifdef __UINTPTR_MAX__
+#define UINTPTR_MAX (__UINTPTR_MAX__)
+#else
+#define UINTPTR_MAX (2UL * PTRDIFF_MAX + 1)
+#endif
+#else
+/*
+ * Fallback to hardcoded values, 
+ * should be valid on cpu's with 32bit int/32bit void*
+ */
+#define INTPTR_MAX (__STDINT_EXP(LONG_MAX))
+#define INTPTR_MIN (-__STDINT_EXP(LONG_MAX) - 1)
+#define UINTPTR_MAX (__STDINT_EXP(LONG_MAX) * 2UL + 1)
+#endif
+
+/* Limits of Specified-Width Integer Types */
+
+#ifdef __INT8_MAX__
+#define INT8_MIN (-__INT8_MAX__ - 1)
+#define INT8_MAX (__INT8_MAX__)
+#define UINT8_MAX (__UINT8_MAX__)
+#elif defined(__int8_t_defined)
+#define INT8_MIN 	(-128)
+#define INT8_MAX 	 (127)
+#define UINT8_MAX 	 (255)
+#endif
+
+#ifdef __INT_LEAST8_MAX__
+#define INT_LEAST8_MIN (-__INT_LEAST8_MAX__ - 1)
+#define INT_LEAST8_MAX (__INT_LEAST8_MAX__)
+#define UINT_LEAST8_MAX (__UINT_LEAST8_MAX__)
+#elif defined(__int_least8_t_defined)
+#define INT_LEAST8_MIN 	(-128)
+#define INT_LEAST8_MAX 	 (127)
+#define UINT_LEAST8_MAX	 (255)
+#else
+#error required type int_least8_t missing
+#endif
+
+#ifdef __INT16_MAX__
+#define INT16_MIN (-__INT16_MAX__ - 1)
+#define INT16_MAX (__INT16_MAX__)
+#define UINT16_MAX (__UINT16_MAX__)
+#elif defined(__int16_t_defined)
+#define INT16_MIN 	(-32768)
+#define INT16_MAX 	 (32767)
+#define UINT16_MAX 	 (65535)
+#endif
+
+#ifdef __INT_LEAST16_MAX__
+#define INT_LEAST16_MIN (-__INT_LEAST16_MAX__ - 1)
+#define INT_LEAST16_MAX (__INT_LEAST16_MAX__)
+#define UINT_LEAST16_MAX (__UINT_LEAST16_MAX__)
+#elif defined(__int_least16_t_defined)
+#define INT_LEAST16_MIN	(-32768)
+#define INT_LEAST16_MAX	 (32767)
+#define UINT_LEAST16_MAX (65535)
+#else
+#error required type int_least16_t missing
+#endif
+
+#ifdef __INT32_MAX__
+#define INT32_MIN (-__INT32_MAX__ - 1)
+#define INT32_MAX (__INT32_MAX__)
+#define UINT32_MAX (__UINT32_MAX__)
+#elif defined(__int32_t_defined)
+#if defined (_INT32_EQ_LONG)
+#define INT32_MIN 	 (-2147483647L-1)
+#define INT32_MAX 	 (2147483647L)
+#define UINT32_MAX       (4294967295UL)
+#else
+#define INT32_MIN 	 (-2147483647-1)
+#define INT32_MAX 	 (2147483647)
+#define UINT32_MAX       (4294967295U)
+#endif
+#endif
+
+#ifdef __INT_LEAST32_MAX__
+#define INT_LEAST32_MIN (-__INT_LEAST32_MAX__ - 1)
+#define INT_LEAST32_MAX (__INT_LEAST32_MAX__)
+#define UINT_LEAST32_MAX (__UINT_LEAST32_MAX__)
+#elif defined(__int_least32_t_defined)
+#if defined (_INT32_EQ_LONG)
+#define INT_LEAST32_MIN  (-2147483647L-1)
+#define INT_LEAST32_MAX  (2147483647L)
+#define UINT_LEAST32_MAX (4294967295UL)
+#else
+#define INT_LEAST32_MIN  (-2147483647-1)
+#define INT_LEAST32_MAX  (2147483647)
+#define UINT_LEAST32_MAX (4294967295U)
+#endif
+#else
+#error required type int_least32_t missing
+#endif
+
+#ifdef __INT64_MAX__
+#define INT64_MIN (-__INT64_MAX__ - 1)
+#define INT64_MAX (__INT64_MAX__)
+#define UINT64_MAX (__UINT64_MAX__)
+#elif defined(__int64_t_defined)
+#if __have_long64
+#define INT64_MIN 	(-9223372036854775807L-1L)
+#define INT64_MAX 	 (9223372036854775807L)
+#define UINT64_MAX 	(18446744073709551615U)
+#elif __have_longlong64
+#define INT64_MIN 	(-9223372036854775807LL-1LL)
+#define INT64_MAX 	 (9223372036854775807LL)
+#define UINT64_MAX 	(18446744073709551615ULL)
+#endif
+#endif
+
+#ifdef __INT_LEAST64_MAX__
+#define INT_LEAST64_MIN (-__INT_LEAST64_MAX__ - 1)
+#define INT_LEAST64_MAX (__INT_LEAST64_MAX__)
+#define UINT_LEAST64_MAX (__UINT_LEAST64_MAX__)
+#elif defined(__int_least64_t_defined)
+#if __have_long64
+#define INT_LEAST64_MIN  (-9223372036854775807L-1L)
+#define INT_LEAST64_MAX  (9223372036854775807L)
+#define UINT_LEAST64_MAX (18446744073709551615U)
+#elif __have_longlong64
+#define INT_LEAST64_MIN  (-9223372036854775807LL-1LL)
+#define INT_LEAST64_MAX  (9223372036854775807LL)
+#define UINT_LEAST64_MAX (18446744073709551615ULL)
+#endif
+#endif
+
+#ifdef __INT_FAST8_MAX__
+#define INT_FAST8_MIN (-__INT_FAST8_MAX__ - 1)
+#define INT_FAST8_MAX (__INT_FAST8_MAX__)
+#define UINT_FAST8_MAX (__UINT_FAST8_MAX__)
+#elif defined(__int_fast8_t_defined)
+#if __STDINT_EXP(INT_MAX) >= 0x7f
+#define INT_FAST8_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST8_MAX	(__STDINT_EXP(INT_MAX))
+#define UINT_FAST8_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST8_MIN	INT_LEAST8_MIN
+#define INT_FAST8_MAX	INT_LEAST8_MAX
+#define UINT_FAST8_MAX	UINT_LEAST8_MAX
+#endif
+#endif
+
+#ifdef __INT_FAST16_MAX__
+#define INT_FAST16_MIN (-__INT_FAST16_MAX__ - 1)
+#define INT_FAST16_MAX (__INT_FAST16_MAX__)
+#define UINT_FAST16_MAX (__UINT_FAST16_MAX__)
+#elif defined(__int_fast16_t_defined)
+#if __STDINT_EXP(INT_MAX) >= 0x7fff
+#define INT_FAST16_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST16_MAX	(__STDINT_EXP(INT_MAX))
+#define UINT_FAST16_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST16_MIN	INT_LEAST16_MIN
+#define INT_FAST16_MAX	INT_LEAST16_MAX
+#define UINT_FAST16_MAX	UINT_LEAST16_MAX
+#endif
+#endif
+
+#ifdef __INT_FAST32_MAX__
+#define INT_FAST32_MIN (-__INT_FAST32_MAX__ - 1)
+#define INT_FAST32_MAX (__INT_FAST32_MAX__)
+#define UINT_FAST32_MAX (__UINT_FAST32_MAX__)
+#elif defined(__int_fast32_t_defined)
+#if __STDINT_EXP(INT_MAX) >= 0x7fffffff
+#define INT_FAST32_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST32_MAX	(__STDINT_EXP(INT_MAX))
+#define UINT_FAST32_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST32_MIN	INT_LEAST32_MIN
+#define INT_FAST32_MAX	INT_LEAST32_MAX
+#define UINT_FAST32_MAX	UINT_LEAST32_MAX
+#endif
+#endif
+
+#ifdef __INT_FAST64_MAX__
+#define INT_FAST64_MIN (-__INT_FAST64_MAX__ - 1)
+#define INT_FAST64_MAX (__INT_FAST64_MAX__)
+#define UINT_FAST64_MAX (__UINT_FAST64_MAX__)
+#elif defined(__int_fast64_t_defined)
+#if __STDINT_EXP(INT_MAX) > 0x7fffffff
+#define INT_FAST64_MIN	(-__STDINT_EXP(INT_MAX)-1)
+#define INT_FAST64_MAX	(__STDINT_EXP(INT_MAX))
+#define UINT_FAST64_MAX	(__STDINT_EXP(INT_MAX)*2U+1U)
+#else
+#define INT_FAST64_MIN	INT_LEAST64_MIN
+#define INT_FAST64_MAX	INT_LEAST64_MAX
+#define UINT_FAST64_MAX	UINT_LEAST64_MAX
+#endif
+#endif
+
+#ifdef __INTMAX_MAX__
+#define INTMAX_MAX (__INTMAX_MAX__)
+#define INTMAX_MIN (-INTMAX_MAX - 1)
+#elif defined(__INTMAX_TYPE__)
+/* All relevant GCC versions prefer long to long long for intmax_t.  */
+#define INTMAX_MAX INT64_MAX
+#define INTMAX_MIN INT64_MIN
+#endif
+
+#ifdef __UINTMAX_MAX__
+#define UINTMAX_MAX (__UINTMAX_MAX__)
+#elif defined(__UINTMAX_TYPE__)
+/* All relevant GCC versions prefer long to long long for intmax_t.  */
+#define UINTMAX_MAX UINT64_MAX
+#endif
+
+/* This must match size_t in stddef.h, currently long unsigned int */
+#ifdef __SIZE_MAX__
+#define SIZE_MAX (__SIZE_MAX__)
+#else
+#define SIZE_MAX (__STDINT_EXP(LONG_MAX) * 2UL + 1)
+#endif
+
+/* This must match sig_atomic_t in <signal.h> (currently int) */
+#define SIG_ATOMIC_MIN (-__STDINT_EXP(INT_MAX) - 1)
+#define SIG_ATOMIC_MAX (__STDINT_EXP(INT_MAX))
+
+/* This must match ptrdiff_t  in <stddef.h> (currently long int) */
+#ifdef __PTRDIFF_MAX__
+#define PTRDIFF_MAX (__PTRDIFF_MAX__)
+#else
+#define PTRDIFF_MAX (__STDINT_EXP(LONG_MAX))
+#endif
+#define PTRDIFF_MIN (-PTRDIFF_MAX - 1)
+
+/* This must match definition in <wchar.h> */
+#ifndef WCHAR_MIN
+#ifdef __WCHAR_MIN__
+#define WCHAR_MIN (__WCHAR_MIN__)
+#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
+#define WCHAR_MIN (0 + L'\0')
+#else
+#define WCHAR_MIN (-0x7fffffff - 1 + L'\0')
+#endif
+#endif
+
+/* This must match definition in <wchar.h> */
+#ifndef WCHAR_MAX
+#ifdef __WCHAR_MAX__
+#define WCHAR_MAX (__WCHAR_MAX__)
+#elif defined(__WCHAR_UNSIGNED__) || (L'\0' - 1 > 0)
+#define WCHAR_MAX (0xffffffffu + L'\0')
+#else
+#define WCHAR_MAX (0x7fffffff + L'\0')
+#endif
+#endif
+
+/* wint_t is unsigned int on almost all GCC targets.  */
+#ifdef __WINT_MAX__
+#define WINT_MAX (__WINT_MAX__)
+#else
+#define WINT_MAX (__STDINT_EXP(INT_MAX) * 2U + 1U)
+#endif
+#ifdef __WINT_MIN__
+#define WINT_MIN (__WINT_MIN__)
+#else
+#define WINT_MIN (0U)
+#endif
+
+/** Macros for minimum-width integer constant expressions */
+#ifdef __INT8_C
+#define INT8_C(x) __INT8_C(x)
+#define UINT8_C(x) __UINT8_C(x)
+#else
+#define INT8_C(x)	x
+#if __STDINT_EXP(INT_MAX) > 0x7f
+#define UINT8_C(x)	x
+#else
+#define UINT8_C(x)	x##U
+#endif
+#endif
+
+#ifdef __INT16_C
+#define INT16_C(x) __INT16_C(x)
+#define UINT16_C(x) __UINT16_C(x)
+#else
+#define INT16_C(x)	x
+#if __STDINT_EXP(INT_MAX) > 0x7fff
+#define UINT16_C(x)	x
+#else
+#define UINT16_C(x)	x##U
+#endif
+#endif
+
+#ifdef __INT32_C
+#define INT32_C(x) __INT32_C(x)
+#define UINT32_C(x) __UINT32_C(x)
+#else
+#if defined (_INT32_EQ_LONG)
+#define INT32_C(x)	x##L
+#define UINT32_C(x)	x##UL
+#else
+#define INT32_C(x)	x
+#define UINT32_C(x)	x##U
+#endif
+#endif
+
+#ifdef __INT64_C
+#define INT64_C(x) __INT64_C(x)
+#define UINT64_C(x) __UINT64_C(x)
+#else
+#if __int64_t_defined
+#if __have_long64
+#define INT64_C(x)	x##L
+#define UINT64_C(x)	x##UL
+#else
+#define INT64_C(x)	x##LL
+#define UINT64_C(x)	x##ULL
+#endif
+#endif
+#endif
+
+/** Macros for greatest-width integer constant expression */
+#ifdef __INTMAX_C
+#define INTMAX_C(x) __INTMAX_C(x)
+#define UINTMAX_C(x) __UINTMAX_C(x)
+#else
+#if __have_long64
+#define INTMAX_C(x)	x##L
+#define UINTMAX_C(x)	x##UL
+#else
+#define INTMAX_C(x)	x##LL
+#define UINTMAX_C(x)	x##ULL
+#endif
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STDINT_H */

src/include/stdio.h

@@ -0,0 +1,804 @@
+/*
+ * Copyright (c) 1990 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Berkeley.  The name of the
+ * University may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *	@(#)stdio.h	5.3 (Berkeley) 3/15/86
+ */
+
+/*
+ * NB: to fit things in six character monocase externals, the
+ * stdio code uses the prefix `__s' for stdio objects, typically
+ * followed by a three-character attempt at a mnemonic.
+ */
+
+#ifndef _STDIO_H_
+#define	_STDIO_H_
+
+#include "_ansi.h"
+
+#define	_FSTDIO			/* ``function stdio'' */
+
+#define __need_size_t
+#define __need_NULL
+#include <sys/cdefs.h>
+#include <stddef.h>
+#include <printf.h>
+
+/* typedef only __gnuc_va_list, used throughout the header */
+#define __need___va_list
+#include <stdarg.h>
+
+/* typedef va_list only when required */
+#if __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE
+#ifdef __GNUC__
+#ifndef _VA_LIST_DEFINED
+typedef __gnuc_va_list va_list;
+#define _VA_LIST_DEFINED
+#endif
+#else /* !__GNUC__ */
+#include <stdarg.h>
+#endif
+#endif /* __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE */
+
+/*
+ * <sys/reent.h> defines __FILE, _fpos_t.
+ * They must be defined there because struct _reent needs them (and we don't
+ * want reent.h to include this file.
+ */
+
+#include <sys/reent.h>
+#include <sys/types.h>
+
+_BEGIN_STD_C
+
+#if !defined(__FILE_defined)
+typedef __FILE FILE;
+# define __FILE_defined
+#endif
+
+#ifdef __CYGWIN__
+typedef _fpos64_t fpos_t;
+#else
+typedef _fpos_t fpos_t;
+#ifdef __LARGE64_FILES
+typedef _fpos64_t fpos64_t;
+#endif
+#endif /* !__CYGWIN__ */
+
+#include <sys/stdio.h>
+
+#define	__SLBF	0x0001		/* line buffered */
+#define	__SNBF	0x0002		/* unbuffered */
+#define	__SRD	0x0004		/* OK to read */
+#define	__SWR	0x0008		/* OK to write */
+	/* RD and WR are never simultaneously asserted */
+#define	__SRW	0x0010		/* open for reading & writing */
+#define	__SEOF	0x0020		/* found EOF */
+#define	__SERR	0x0040		/* found error */
+#define	__SMBF	0x0080		/* _buf is from malloc */
+#define	__SAPP	0x0100		/* fdopen()ed in append mode - so must  write to end */
+#define	__SSTR	0x0200		/* this is an sprintf/snprintf string */
+#define	__SOPT	0x0400		/* do fseek() optimisation */
+#define	__SNPT	0x0800		/* do not do fseek() optimisation */
+#define	__SOFF	0x1000		/* set iff _offset is in fact correct */
+#define	__SORD	0x2000		/* true => stream orientation (byte/wide) decided */
+#if defined(__CYGWIN__)
+#  define __SCLE  0x4000        /* convert line endings CR/LF <-> NL */
+#endif
+#define	__SL64	0x8000		/* is 64-bit offset large file */
+
+/* _flags2 flags */
+#define	__SNLK  0x0001		/* stdio functions do not lock streams themselves */
+#define	__SWID	0x2000		/* true => stream orientation wide, false => byte, only valid if __SORD in _flags is true */
+
+/*
+ * The following three definitions are for ANSI C, which took them
+ * from System V, which stupidly took internal interface macros and
+ * made them official arguments to setvbuf(), without renaming them.
+ * Hence, these ugly _IOxxx names are *supposed* to appear in user code.
+ *
+ * Although these happen to match their counterparts above, the
+ * implementation does not rely on that (so these could be renumbered).
+ */
+#define	_IOFBF	0		/* setvbuf should set fully buffered */
+#define	_IOLBF	1		/* setvbuf should set line buffered */
+#define	_IONBF	2		/* setvbuf should set unbuffered */
+
+#define	EOF	(-1)
+
+#ifdef __BUFSIZ__
+#define	BUFSIZ		__BUFSIZ__
+#else
+#define	BUFSIZ		1024
+#endif
+
+#ifdef __FOPEN_MAX__
+#define FOPEN_MAX	__FOPEN_MAX__
+#else
+#define	FOPEN_MAX	20
+#endif
+
+#ifdef __FILENAME_MAX__
+#define FILENAME_MAX    __FILENAME_MAX__
+#else
+#define	FILENAME_MAX	1024
+#endif
+
+#ifdef __L_tmpnam__
+#define L_tmpnam	__L_tmpnam__
+#else
+#define	L_tmpnam	FILENAME_MAX
+#endif
+
+#if __BSD_VISIBLE || __XSI_VISIBLE
+#define P_tmpdir        "/tmp"
+#endif
+
+#ifndef SEEK_SET
+#define	SEEK_SET	0	/* set file offset to offset */
+#endif
+#ifndef SEEK_CUR
+#define	SEEK_CUR	1	/* set file offset to current plus offset */
+#endif
+#ifndef SEEK_END
+#define	SEEK_END	2	/* set file offset to EOF plus offset */
+#endif
+
+#define	TMP_MAX		26
+
+#define	stdin	(_REENT->_stdin)
+#define	stdout	(_REENT->_stdout)
+#define	stderr	(_REENT->_stderr)
+
+#define _stdin_r(x)	((x)->_stdin)
+#define _stdout_r(x)	((x)->_stdout)
+#define _stderr_r(x)	((x)->_stderr)
+
+/*
+ * Functions defined in ANSI C standard.
+ */
+
+#ifndef __VALIST
+#ifdef __GNUC__
+#define __VALIST __gnuc_va_list
+#else
+#define __VALIST char*
+#endif
+#endif
+
+#if __POSIX_VISIBLE
+char *	ctermid (char *);
+#endif
+#if __GNU_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 600)
+char *	cuserid (char *);
+#endif
+FILE *	tmpfile (void);
+char *	tmpnam (char *);
+#if __BSD_VISIBLE || __XSI_VISIBLE || __POSIX_VISIBLE >= 200112
+char *	tempnam (const char *, const char *) __malloc_like __result_use_check;
+#endif
+int	fclose (FILE *);
+int	fflush (FILE *);
+FILE *	freopen (const char *__restrict, const char *__restrict, FILE *__restrict);
+void	setbuf (FILE *__restrict, char *__restrict);
+int	setvbuf (FILE *__restrict, char *__restrict, int, size_t);
+int	fprintf (FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+int	fscanf (FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3)));
+int	printf (const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 2)));
+int	scanf (const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 2)));
+int	sscanf (const char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3)));
+int	vfprintf (FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+int	vprintf (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 0)));
+int	vsprintf (char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+int	fgetc (FILE *);
+char *  fgets (char *__restrict, int, FILE *__restrict);
+int	fputc (int, FILE *);
+int	fputs (const char *__restrict, FILE *__restrict);
+int	getc (FILE *);
+int	getchar (void);
+char *  gets (char *);
+int	putc (int, FILE *);
+int	putchar (int);
+int	puts (const char *);
+int	ungetc (int, FILE *);
+size_t	fread (void *__restrict, size_t _size, size_t _n, FILE *__restrict);
+size_t	fwrite (const void *__restrict , size_t _size, size_t _n, FILE *);
+#ifdef _COMPILING_NEWLIB
+int	fgetpos (FILE *, _fpos_t *);
+#else
+int	fgetpos (FILE *__restrict, fpos_t *__restrict);
+#endif
+int	fseek (FILE *, long, int);
+#ifdef _COMPILING_NEWLIB
+int	fsetpos (FILE *, const _fpos_t *);
+#else
+int	fsetpos (FILE *, const fpos_t *);
+#endif
+long	ftell ( FILE *);
+void	rewind (FILE *);
+void	clearerr (FILE *);
+int	feof (FILE *);
+int	ferror (FILE *);
+void    perror (const char *);
+#ifndef _REENT_ONLY
+FILE *	fopen (const char *__restrict _name, const char *__restrict _type);
+int	sprintf (char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+int	remove (const char *);
+int	rename (const char *, const char *);
+#ifdef _COMPILING_NEWLIB
+int	_rename (const char *, const char *);
+#endif
+#endif
+#if __LARGEFILE_VISIBLE || __POSIX_VISIBLE >= 200112
+#ifdef _COMPILING_NEWLIB
+int	fseeko (FILE *, _off_t, int);
+_off_t	ftello (FILE *);
+#else
+int	fseeko (FILE *, off_t, int);
+off_t	ftello (FILE *);
+#endif
+#endif
+#if __GNU_VISIBLE
+int	fcloseall (void);
+#endif
+#ifndef _REENT_ONLY
+#if __ISO_C_VISIBLE >= 1999
+int	snprintf (char *__restrict, size_t, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	vsnprintf (char *__restrict, size_t, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	vfscanf (FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0)));
+int	vscanf (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 0)));
+int	vsscanf (const char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0)));
+#endif
+#if __GNU_VISIBLE
+int	asprintf (char **__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+int	vasprintf (char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+#endif
+#if __MISC_VISIBLE /* Newlib-specific */
+int	asiprintf (char **, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+char *	asniprintf (char *, size_t *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+char *	asnprintf (char *__restrict, size_t *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+#ifndef diprintf
+int	diprintf (int, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+#endif
+int	fiprintf (FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+int	fiscanf (FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3)));
+int	iprintf (const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 2)));
+int	iscanf (const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 2)));
+int	siprintf (char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+int	siscanf (const char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3)));
+int	sniprintf (char *, size_t, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	vasiprintf (char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+char *	vasniprintf (char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+char *	vasnprintf (char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	vdiprintf (int, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+int	vfiprintf (FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+int	vfiscanf (FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0)));
+int	viprintf (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 1, 0)));
+int	viscanf (const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 1, 0)));
+int	vsiprintf (char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+int	vsiscanf (const char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0)));
+int	vsniprintf (char *, size_t, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+#endif /* __MISC_VISIBLE */
+#endif /* !_REENT_ONLY */
+
+/*
+ * Routines in POSIX 1003.1:2001.
+ */
+
+#if __POSIX_VISIBLE
+#ifndef _REENT_ONLY
+FILE *	fdopen (int, const char *);
+#endif
+int	fileno (FILE *);
+#endif
+#if __MISC_VISIBLE || __POSIX_VISIBLE >= 199209
+int	pclose (FILE *);
+FILE *  popen (const char *, const char *);
+#endif
+
+#if __BSD_VISIBLE
+void    setbuffer (FILE *, char *, int);
+int	setlinebuf (FILE *);
+#endif
+
+#if __MISC_VISIBLE || (__XSI_VISIBLE && __POSIX_VISIBLE < 200112)
+int	getw (FILE *);
+int	putw (int, FILE *);
+#endif
+#if __MISC_VISIBLE || __POSIX_VISIBLE
+int	getc_unlocked (FILE *);
+int	getchar_unlocked (void);
+void	flockfile (FILE *);
+int	ftrylockfile (FILE *);
+void	funlockfile (FILE *);
+int	putc_unlocked (int, FILE *);
+int	putchar_unlocked (int);
+#endif
+
+/*
+ * Routines in POSIX 1003.1:200x.
+ */
+
+#if __POSIX_VISIBLE >= 200809
+# ifndef _REENT_ONLY
+#  ifndef dprintf
+int	dprintf (int, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+#  endif
+FILE *	fmemopen (void *__restrict, size_t, const char *__restrict);
+/* getdelim - see __getdelim for now */
+/* getline - see __getline for now */
+FILE *	open_memstream (char **, size_t *);
+int	vdprintf (int, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+# endif
+#endif
+#if __ATFILE_VISIBLE
+int	renameat (int, const char *, int, const char *);
+# ifdef __CYGWIN__
+int	renameat2 (int, const char *, int, const char *, unsigned int);
+# endif
+#endif
+
+/*
+ * Recursive versions of the above.
+ */
+
+int	_asiprintf_r (struct _reent *, char **, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+char *	_asniprintf_r (struct _reent *, char *, size_t *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5)));
+char *	_asnprintf_r (struct _reent *, char *__restrict, size_t *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5)));
+int	_asprintf_r (struct _reent *, char **__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	_diprintf_r (struct _reent *, int, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	_dprintf_r (struct _reent *, int, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	_fclose_r (struct _reent *, FILE *);
+int	_fcloseall_r (struct _reent *);
+FILE *	_fdopen_r (struct _reent *, int, const char *);
+int	_fflush_r (struct _reent *, FILE *);
+int	_fgetc_r (struct _reent *, FILE *);
+int	_fgetc_unlocked_r (struct _reent *, FILE *);
+char *  _fgets_r (struct _reent *, char *__restrict, int, FILE *__restrict);
+char *  _fgets_unlocked_r (struct _reent *, char *__restrict, int, FILE *__restrict);
+#ifdef _COMPILING_NEWLIB
+int	_fgetpos_r (struct _reent *, FILE *__restrict, _fpos_t *__restrict);
+int	_fsetpos_r (struct _reent *, FILE *, const _fpos_t *);
+#else
+int	_fgetpos_r (struct _reent *, FILE *, fpos_t *);
+int	_fsetpos_r (struct _reent *, FILE *, const fpos_t *);
+#endif
+int	_fiprintf_r (struct _reent *, FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	_fiscanf_r (struct _reent *, FILE *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4)));
+FILE *	_fmemopen_r (struct _reent *, void *__restrict, size_t, const char *__restrict);
+FILE *	_fopen_r (struct _reent *, const char *__restrict, const char *__restrict);
+FILE *	_freopen_r (struct _reent *, const char *__restrict, const char *__restrict, FILE *__restrict);
+int	_fprintf_r (struct _reent *, FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	_fpurge_r (struct _reent *, FILE *);
+int	_fputc_r (struct _reent *, int, FILE *);
+int	_fputc_unlocked_r (struct _reent *, int, FILE *);
+int	_fputs_r (struct _reent *, const char *__restrict, FILE *__restrict);
+int	_fputs_unlocked_r (struct _reent *, const char *__restrict, FILE *__restrict);
+size_t	_fread_r (struct _reent *, void *__restrict, size_t _size, size_t _n, FILE *__restrict);
+size_t	_fread_unlocked_r (struct _reent *, void *__restrict, size_t _size, size_t _n, FILE *__restrict);
+int	_fscanf_r (struct _reent *, FILE *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4)));
+int	_fseek_r (struct _reent *, FILE *, long, int);
+int	_fseeko_r (struct _reent *, FILE *, _off_t, int);
+long	_ftell_r (struct _reent *, FILE *);
+_off_t	_ftello_r (struct _reent *, FILE *);
+void	_rewind_r (struct _reent *, FILE *);
+size_t	_fwrite_r (struct _reent *, const void *__restrict, size_t _size, size_t _n, FILE *__restrict);
+size_t	_fwrite_unlocked_r (struct _reent *, const void *__restrict, size_t _size, size_t _n, FILE *__restrict);
+int	_getc_r (struct _reent *, FILE *);
+int	_getc_unlocked_r (struct _reent *, FILE *);
+int	_getchar_r (struct _reent *);
+int	_getchar_unlocked_r (struct _reent *);
+char *	_gets_r (struct _reent *, char *);
+int	_iprintf_r (struct _reent *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+int	_iscanf_r (struct _reent *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3)));
+FILE *	_open_memstream_r (struct _reent *, char **, size_t *);
+void	_perror_r (struct _reent *, const char *);
+int	_printf_r (struct _reent *, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 3)));
+int	_putc_r (struct _reent *, int, FILE *);
+int	_putc_unlocked_r (struct _reent *, int, FILE *);
+int	_putchar_unlocked_r (struct _reent *, int);
+int	_putchar_r (struct _reent *, int);
+int	_puts_r (struct _reent *, const char *);
+int	_remove_r (struct _reent *, const char *);
+int	_rename_r (struct _reent *,
+			   const char *_old, const char *_new);
+int	_scanf_r (struct _reent *, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 3)));
+int	_siprintf_r (struct _reent *, char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	_siscanf_r (struct _reent *, const char *, const char *, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4)));
+int	_sniprintf_r (struct _reent *, char *, size_t, const char *, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5)));
+int	_snprintf_r (struct _reent *, char *__restrict, size_t, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 5)));
+int	_sprintf_r (struct _reent *, char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 4)));
+int	_sscanf_r (struct _reent *, const char *__restrict, const char *__restrict, ...)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 4)));
+char *	_tempnam_r (struct _reent *, const char *, const char *);
+FILE *	_tmpfile_r (struct _reent *);
+char *	_tmpnam_r (struct _reent *, char *);
+int	_ungetc_r (struct _reent *, int, FILE *);
+int	_vasiprintf_r (struct _reent *, char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+char *	_vasniprintf_r (struct _reent*, char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0)));
+char *	_vasnprintf_r (struct _reent*, char *, size_t *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0)));
+int	_vasprintf_r (struct _reent *, char **, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	_vdiprintf_r (struct _reent *, int, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	_vdprintf_r (struct _reent *, int, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	_vfiprintf_r (struct _reent *, FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	_vfiscanf_r (struct _reent *, FILE *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0)));
+int	_vfprintf_r (struct _reent *, FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	_vfscanf_r (struct _reent *, FILE *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0)));
+int	_viprintf_r (struct _reent *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+int	_viscanf_r (struct _reent *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0)));
+int	_vprintf_r (struct _reent *, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 2, 0)));
+int	_vscanf_r (struct _reent *, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 2, 0)));
+int	_vsiprintf_r (struct _reent *, char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	_vsiscanf_r (struct _reent *, const char *, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0)));
+int	_vsniprintf_r (struct _reent *, char *, size_t, const char *, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0)));
+int	_vsnprintf_r (struct _reent *, char *__restrict, size_t, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 4, 0)));
+int	_vsprintf_r (struct _reent *, char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__printf__, 3, 0)));
+int	_vsscanf_r (struct _reent *, const char *__restrict, const char *__restrict, __VALIST)
+               _ATTRIBUTE ((__format__ (__scanf__, 3, 0)));
+
+/* Other extensions.  */
+
+int	fpurge (FILE *);
+ssize_t __getdelim (char **, size_t *, int, FILE *);
+ssize_t __getline (char **, size_t *, FILE *);
+
+#if __MISC_VISIBLE
+void	clearerr_unlocked (FILE *);
+int	feof_unlocked (FILE *);
+int	ferror_unlocked (FILE *);
+int	fileno_unlocked (FILE *);
+int	fflush_unlocked (FILE *);
+int	fgetc_unlocked (FILE *);
+int	fputc_unlocked (int, FILE *);
+size_t	fread_unlocked (void *__restrict, size_t _size, size_t _n, FILE *__restrict);
+size_t	fwrite_unlocked (const void *__restrict , size_t _size, size_t _n, FILE *);
+#endif
+
+#if __GNU_VISIBLE
+char *  fgets_unlocked (char *__restrict, int, FILE *__restrict);
+int	fputs_unlocked (const char *__restrict, FILE *__restrict);
+#endif
+
+#ifdef __LARGE64_FILES
+#if !defined(__CYGWIN__) || defined(_COMPILING_NEWLIB)
+FILE *	fdopen64 (int, const char *);
+FILE *  fopen64 (const char *, const char *);
+FILE *  freopen64 (const char *, const char *, FILE *);
+_off64_t ftello64 (FILE *);
+_off64_t fseeko64 (FILE *, _off64_t, int);
+int     fgetpos64 (FILE *, _fpos64_t *);
+int     fsetpos64 (FILE *, const _fpos64_t *);
+FILE *  tmpfile64 (void);
+
+FILE *	_fdopen64_r (struct _reent *, int, const char *);
+FILE *  _fopen64_r (struct _reent *,const char *, const char *);
+FILE *  _freopen64_r (struct _reent *, const char *, const char *, FILE *);
+_off64_t _ftello64_r (struct _reent *, FILE *);
+_off64_t _fseeko64_r (struct _reent *, FILE *, _off64_t, int);
+int     _fgetpos64_r (struct _reent *, FILE *, _fpos64_t *);
+int     _fsetpos64_r (struct _reent *, FILE *, const _fpos64_t *);
+FILE *  _tmpfile64_r (struct _reent *);
+#endif /* !__CYGWIN__ */
+#endif /* __LARGE64_FILES */
+
+/*
+ * Routines internal to the implementation.
+ */
+
+int	__srget_r (struct _reent *, FILE *);
+int	__swbuf_r (struct _reent *, int, FILE *);
+
+/*
+ * Stdio function-access interface.
+ */
+
+#if __BSD_VISIBLE
+# ifdef __LARGE64_FILES
+FILE	*funopen (const void *__cookie,
+		int (*__readfn)(void *__c, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(void *__c, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		_fpos64_t (*__seekfn)(void *__c, _fpos64_t __off, int __whence),
+		int (*__closefn)(void *__c));
+FILE	*_funopen_r (struct _reent *, const void *__cookie,
+		int (*__readfn)(void *__c, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(void *__c, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		_fpos64_t (*__seekfn)(void *__c, _fpos64_t __off, int __whence),
+		int (*__closefn)(void *__c));
+# else
+FILE	*funopen (const void *__cookie,
+		int (*__readfn)(void *__cookie, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(void *__cookie, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		fpos_t (*__seekfn)(void *__cookie, fpos_t __off, int __whence),
+		int (*__closefn)(void *__cookie));
+FILE	*_funopen_r (struct _reent *, const void *__cookie,
+		int (*__readfn)(void *__cookie, char *__buf,
+				_READ_WRITE_BUFSIZE_TYPE __n),
+		int (*__writefn)(void *__cookie, const char *__buf,
+				 _READ_WRITE_BUFSIZE_TYPE __n),
+		fpos_t (*__seekfn)(void *__cookie, fpos_t __off, int __whence),
+		int (*__closefn)(void *__cookie));
+# endif /* !__LARGE64_FILES */
+
+# define	fropen(__cookie, __fn) funopen(__cookie, __fn, (int (*)())0, \
+					       (fpos_t (*)())0, (int (*)())0)
+# define	fwopen(__cookie, __fn) funopen(__cookie, (int (*)())0, __fn, \
+					       (fpos_t (*)())0, (int (*)())0)
+#endif /* __BSD_VISIBLE */
+
+#if __GNU_VISIBLE
+typedef ssize_t cookie_read_function_t(void *__cookie, char *__buf, size_t __n);
+typedef ssize_t cookie_write_function_t(void *__cookie, const char *__buf,
+					size_t __n);
+# ifdef __LARGE64_FILES
+typedef int cookie_seek_function_t(void *__cookie, _off64_t *__off,
+				   int __whence);
+# else
+typedef int cookie_seek_function_t(void *__cookie, off_t *__off, int __whence);
+# endif /* !__LARGE64_FILES */
+typedef int cookie_close_function_t(void *__cookie);
+typedef struct
+{
+  /* These four struct member names are dictated by Linux; hopefully,
+     they don't conflict with any macros.  */
+  cookie_read_function_t  *read;
+  cookie_write_function_t *write;
+  cookie_seek_function_t  *seek;
+  cookie_close_function_t *close;
+} cookie_io_functions_t;
+FILE *fopencookie (void *__cookie,
+		const char *__mode, cookie_io_functions_t __functions);
+FILE *_fopencookie_r (struct _reent *, void *__cookie,
+		const char *__mode, cookie_io_functions_t __functions);
+#endif /* __GNU_VISIBLE */
+
+#ifndef __CUSTOM_FILE_IO__
+/*
+ * The __sfoo macros are here so that we can 
+ * define function versions in the C library.
+ */
+#define       __sgetc_raw_r(__ptr, __f) (--(__f)->_r < 0 ? __srget_r(__ptr, __f) : (int)(*(__f)->_p++))
+
+#ifdef __SCLE
+/*  For a platform with CR/LF, additional logic is required by
+  __sgetc_r which would otherwise simply be a macro; therefore we
+  use an inlined function.  The function is only meant to be inlined
+  in place as used and the function body should never be emitted.  
+
+  There are two possible means to this end when compiling with GCC,
+  one when compiling with a standard C99 compiler, and for other
+  compilers we're just stuck.  At the moment, this issue only
+  affects the Cygwin target, so we'll most likely be using GCC. */
+
+_ELIDABLE_INLINE int __sgetc_r(struct _reent *__ptr, FILE *__p);
+
+_ELIDABLE_INLINE int __sgetc_r(struct _reent *__ptr, FILE *__p)
+  {
+    int __c = __sgetc_raw_r(__ptr, __p);
+    if ((__p->_flags & __SCLE) && (__c == '\r'))
+      {
+      int __c2 = __sgetc_raw_r(__ptr, __p);
+      if (__c2 == '\n')
+        __c = __c2;
+      else
+        ungetc(__c2, __p);
+      }
+    return __c;
+  }
+#else
+#define __sgetc_r(__ptr, __p) __sgetc_raw_r(__ptr, __p)
+#endif
+
+#ifdef __GNUC__
+_ELIDABLE_INLINE int __sputc_r(struct _reent *_ptr, int _c, FILE *_p) {
+#ifdef __SCLE
+	if ((_p->_flags & __SCLE) && _c == '\n')
+	  __sputc_r (_ptr, '\r', _p);
+#endif
+	if (--_p->_w >= 0 || (_p->_w >= _p->_lbfsize && (char)_c != '\n'))
+		return (*_p->_p++ = _c);
+	else
+		return (__swbuf_r(_ptr, _c, _p));
+}
+#else
+/*
+ * This has been tuned to generate reasonable code on the vax using pcc
+ */
+#define       __sputc_raw_r(__ptr, __c, __p) \
+	(--(__p)->_w < 0 ? \
+		(__p)->_w >= (__p)->_lbfsize ? \
+			(*(__p)->_p = (__c)), *(__p)->_p != '\n' ? \
+				(int)*(__p)->_p++ : \
+				__swbuf_r(__ptr, '\n', __p) : \
+			__swbuf_r(__ptr, (int)(__c), __p) : \
+		(*(__p)->_p = (__c), (int)*(__p)->_p++))
+#ifdef __SCLE
+#define __sputc_r(__ptr, __c, __p) \
+        ((((__p)->_flags & __SCLE) && ((__c) == '\n')) \
+          ? __sputc_raw_r(__ptr, '\r', (__p)) : 0 , \
+        __sputc_raw_r((__ptr), (__c), (__p)))
+#else
+#define __sputc_r(__ptr, __c, __p) __sputc_raw_r(__ptr, __c, __p)
+#endif
+#endif
+
+#define	__sfeof(p)	((int)(((p)->_flags & __SEOF) != 0))
+#define	__sferror(p)	((int)(((p)->_flags & __SERR) != 0))
+#define	__sclearerr(p)	((void)((p)->_flags &= ~(__SERR|__SEOF)))
+#define	__sfileno(p)	((p)->_file)
+
+#ifndef __cplusplus
+#ifndef _REENT_SMALL
+#define	feof(p)		__sfeof(p)
+#define	ferror(p)	__sferror(p)
+#define	clearerr(p)	__sclearerr(p)
+
+#if __MISC_VISIBLE
+#define	feof_unlocked(p)	__sfeof(p)
+#define	ferror_unlocked(p)	__sferror(p)
+#define	clearerr_unlocked(p)	__sclearerr(p)
+#endif /* __MISC_VISIBLE */
+#endif /* _REENT_SMALL */
+
+#if 0 /* __POSIX_VISIBLE - FIXME: must initialize stdio first, use fn */
+#define	fileno(p)	__sfileno(p)
+#endif
+
+static __inline int
+_getchar_unlocked(void)
+{
+	struct _reent *_ptr;
+
+	_ptr = _REENT;
+	return (__sgetc_r(_ptr, _stdin_r(_ptr)));
+}
+
+static __inline int
+_putchar_unlocked(int _c)
+{
+	struct _reent *_ptr;
+
+	_ptr = _REENT;
+	return (__sputc_r(_ptr, _c, _stdout_r(_ptr)));
+}
+
+#ifdef __SINGLE_THREAD__
+#define	getc(_p)	__sgetc_r(_REENT, _p)
+#define	putc(_c, _p)	__sputc_r(_REENT, _c, _p)
+#define	getchar()	_getchar_unlocked()
+#define	putchar(_c)	_putchar_unlocked(_c)
+#endif /* __SINGLE_THREAD__ */
+
+#if __MISC_VISIBLE || __POSIX_VISIBLE
+#define	getchar_unlocked()	_getchar_unlocked()
+#define	putchar_unlocked(_c)	_putchar_unlocked(_c)
+#endif
+#endif /* __cplusplus */
+
+#if __MISC_VISIBLE
+/* fast always-buffered version, true iff error */
+#define	fast_putc(x,p) (--(p)->_w < 0 ? \
+	__swbuf_r(_REENT, (int)(x), p) == EOF : (*(p)->_p = (x), (p)->_p++, 0))
+#endif
+
+#if __GNU_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 600)
+#define	L_cuserid	9		/* posix says it goes in stdio.h :( */
+#endif
+#if __POSIX_VISIBLE
+#define L_ctermid       16
+#endif
+
+#else /* __CUSTOM_FILE_IO__ */
+
+#define	getchar()	getc(stdin)
+#define	putchar(x)	putc(x, stdout)
+
+#if __MISC_VISIBLE || __POSIX_VISIBLE
+#define	getchar_unlocked()	getc_unlocked(stdin)
+#define	putchar_unlocked(x)	putc_unlocked(x, stdout)
+#endif
+
+#endif /* !__CUSTOM_FILE_IO__ */
+
+_END_STD_C
+
+#if __SSP_FORTIFY_LEVEL > 0
+#include <ssp/stdio.h>
+#endif
+
+#endif /* _STDIO_H_ */

src/include/stdlib.h

@@ -0,0 +1,342 @@
+/*
+ * stdlib.h
+ *
+ * Definitions for common types, variables, and functions.
+ */
+
+#ifndef _STDLIB_H_
+#define _STDLIB_H_
+
+#include <machine/ieeefp.h>
+#include "_ansi.h"
+
+#define __need_size_t
+#define __need_wchar_t
+#define __need_NULL
+#include <stddef.h>
+
+#include <sys/reent.h>
+#include <sys/cdefs.h>
+#include <machine/stdlib.h>
+#ifndef __STRICT_ANSI__
+#include <alloca.h>
+#endif
+
+#ifdef __CYGWIN__
+#include <cygwin/stdlib.h>
+#endif
+
+#if __GNU_VISIBLE
+#include <xlocale.h>
+#endif
+
+_BEGIN_STD_C
+
+typedef struct 
+{
+  int quot; /* quotient */
+  int rem; /* remainder */
+} div_t;
+
+typedef struct 
+{
+  long quot; /* quotient */
+  long rem; /* remainder */
+} ldiv_t;
+
+#if __ISO_C_VISIBLE >= 1999
+typedef struct
+{
+  long long int quot; /* quotient */
+  long long int rem; /* remainder */
+} lldiv_t;
+#endif
+
+#ifndef __compar_fn_t_defined
+#define __compar_fn_t_defined
+typedef int (*__compar_fn_t) (const void *, const void *);
+#endif
+
+#define EXIT_FAILURE 1
+#define EXIT_SUCCESS 0
+
+#define RAND_MAX __RAND_MAX
+
+int	__locale_mb_cur_max (void);
+
+#define MB_CUR_MAX __locale_mb_cur_max()
+
+void	abort (void) _ATTRIBUTE ((__noreturn__));
+int	abs (int);
+#if __BSD_VISIBLE
+__uint32_t arc4random (void);
+__uint32_t arc4random_uniform (__uint32_t);
+void    arc4random_buf (void *, size_t);
+#endif
+int	atexit (void (*__func)(void));
+double	atof (const char *__nptr);
+#if __MISC_VISIBLE
+float	atoff (const char *__nptr);
+#endif
+int	atoi (const char *__nptr);
+int	_atoi_r (struct _reent *, const char *__nptr);
+long	atol (const char *__nptr);
+long	_atol_r (struct _reent *, const char *__nptr);
+void *	bsearch (const void *__key,
+		       const void *__base,
+		       size_t __nmemb,
+		       size_t __size,
+		       __compar_fn_t _compar);
+void	*calloc(size_t, size_t) __malloc_like __result_use_check
+	     __alloc_size2(1, 2) _NOTHROW;
+div_t	div (int __numer, int __denom);
+void	exit (int __status) _ATTRIBUTE ((__noreturn__));
+void	free (void *) _NOTHROW;
+char *  getenv (const char *__string);
+char *	_getenv_r (struct _reent *, const char *__string);
+char *	_findenv (const char *, int *);
+char *	_findenv_r (struct _reent *, const char *, int *);
+#if __POSIX_VISIBLE >= 200809
+extern char *suboptarg;			/* getsubopt(3) external variable */
+int	getsubopt (char **, char * const *, char **);
+#endif
+long	labs (long);
+ldiv_t	ldiv (long __numer, long __denom);
+void	*malloc(size_t) __malloc_like __result_use_check __alloc_size(1) _NOTHROW;
+int	mblen (const char *, size_t);
+int	_mblen_r (struct _reent *, const char *, size_t, _mbstate_t *);
+int	mbtowc (wchar_t *__restrict, const char *__restrict, size_t);
+int	_mbtowc_r (struct _reent *, wchar_t *__restrict, const char *__restrict, size_t, _mbstate_t *);
+int	wctomb (char *, wchar_t);
+int	_wctomb_r (struct _reent *, char *, wchar_t, _mbstate_t *);
+size_t	mbstowcs (wchar_t *__restrict, const char *__restrict, size_t);
+size_t	_mbstowcs_r (struct _reent *, wchar_t *__restrict, const char *__restrict, size_t, _mbstate_t *);
+size_t	wcstombs (char *__restrict, const wchar_t *__restrict, size_t);
+size_t	_wcstombs_r (struct _reent *, char *__restrict, const wchar_t *__restrict, size_t, _mbstate_t *);
+#ifndef _REENT_ONLY
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809
+char *	mkdtemp (char *);
+#endif
+#if __GNU_VISIBLE
+int	mkostemp (char *, int);
+int	mkostemps (char *, int, int);
+#endif
+#if __MISC_VISIBLE || __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE >= 4
+int	mkstemp (char *);
+#endif
+#if __MISC_VISIBLE
+int	mkstemps (char *, int);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE >= 4 && __POSIX_VISIBLE < 200112)
+char *	mktemp (char *) _ATTRIBUTE ((__deprecated__("the use of `mktemp' is dangerous; use `mkstemp' instead")));
+#endif
+#endif /* !_REENT_ONLY */
+char *	_mkdtemp_r (struct _reent *, char *);
+int	_mkostemp_r (struct _reent *, char *, int);
+int	_mkostemps_r (struct _reent *, char *, int, int);
+int	_mkstemp_r (struct _reent *, char *);
+int	_mkstemps_r (struct _reent *, char *, int);
+char *	_mktemp_r (struct _reent *, char *) _ATTRIBUTE ((__deprecated__("the use of `mktemp' is dangerous; use `mkstemp' instead")));
+void	qsort (void *__base, size_t __nmemb, size_t __size, __compar_fn_t _compar);
+int	rand (void);
+void	*realloc(void *, size_t) __result_use_check __alloc_size(2) _NOTHROW;
+#if __BSD_VISIBLE
+void	*reallocarray(void *, size_t, size_t) __result_use_check __alloc_size2(2, 3);
+void	*reallocf(void *, size_t) __result_use_check __alloc_size(2);
+#endif
+#if __BSD_VISIBLE || __XSI_VISIBLE >= 4
+char *	realpath (const char *__restrict path, char *__restrict resolved_path);
+#endif
+#if __BSD_VISIBLE
+int	rpmatch (const char *response);
+#endif
+#if __XSI_VISIBLE
+void	setkey (const char *__key);
+#endif
+void	srand (unsigned __seed);
+double	strtod (const char *__restrict __n, char **__restrict __end_PTR);
+double	_strtod_r (struct _reent *,const char *__restrict __n, char **__restrict __end_PTR);
+#if __ISO_C_VISIBLE >= 1999
+float	strtof (const char *__restrict __n, char **__restrict __end_PTR);
+#endif
+#if __MISC_VISIBLE
+/* the following strtodf interface is deprecated...use strtof instead */
+# ifndef strtodf
+#  define strtodf strtof
+# endif
+#endif
+long	strtol (const char *__restrict __n, char **__restrict __end_PTR, int __base);
+long	_strtol_r (struct _reent *,const char *__restrict __n, char **__restrict __end_PTR, int __base);
+unsigned long strtoul (const char *__restrict __n, char **__restrict __end_PTR, int __base);
+unsigned long _strtoul_r (struct _reent *,const char *__restrict __n, char **__restrict __end_PTR, int __base);
+
+#if __GNU_VISIBLE
+double	strtod_l (const char *__restrict, char **__restrict, locale_t);
+float	strtof_l (const char *__restrict, char **__restrict, locale_t);
+#ifdef _HAVE_LONG_DOUBLE
+extern long double strtold_l (const char *__restrict, char **__restrict,
+			      locale_t);
+#endif /* _HAVE_LONG_DOUBLE */
+long	strtol_l (const char *__restrict, char **__restrict, int, locale_t);
+unsigned long strtoul_l (const char *__restrict, char **__restrict, int,
+			 locale_t __loc);
+long long strtoll_l (const char *__restrict, char **__restrict, int, locale_t);
+unsigned long long strtoull_l (const char *__restrict, char **__restrict, int,
+			       locale_t __loc);
+#endif
+
+int	system (const char *__string);
+
+#if __SVID_VISIBLE || __XSI_VISIBLE >= 4
+long    a64l (const char *__input);
+char *  l64a (long __input);
+char *  _l64a_r (struct _reent *,long __input);
+#endif
+#if __MISC_VISIBLE
+int	on_exit (void (*__func)(int, void *),void *__arg);
+#endif
+#if __ISO_C_VISIBLE >= 1999
+void	_Exit (int __status) _ATTRIBUTE ((__noreturn__));
+#endif
+#if __SVID_VISIBLE || __XSI_VISIBLE
+int	putenv (char *__string);
+#endif
+int	_putenv_r (struct _reent *, char *__string);
+void *	_reallocf_r (struct _reent *, void *, size_t);
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200112
+int	setenv (const char *__string, const char *__value, int __overwrite);
+#endif
+int	_setenv_r (struct _reent *, const char *__string, const char *__value, int __overwrite);
+
+#if __XSI_VISIBLE >= 4 && __POSIX_VISIBLE < 200112
+char *	gcvt (double,int,char *);
+char *	gcvtf (float,int,char *);
+char *	fcvt (double,int,int *,int *);
+char *	fcvtf (float,int,int *,int *);
+char *	ecvt (double,int,int *,int *);
+char *	ecvtbuf (double, int, int*, int*, char *);
+char *	fcvtbuf (double, int, int*, int*, char *);
+char *	ecvtf (float,int,int *,int *);
+#endif
+char *	__itoa (int, char *, int);
+char *	__utoa (unsigned, char *, int);
+#if __MISC_VISIBLE
+char *	itoa (int, char *, int);
+char *	utoa (unsigned, char *, int);
+#endif
+#if __POSIX_VISIBLE
+int	rand_r (unsigned *__seed);
+#endif
+
+#if __SVID_VISIBLE || __XSI_VISIBLE
+double drand48 (void);
+double _drand48_r (struct _reent *);
+double erand48 (unsigned short [3]);
+double _erand48_r (struct _reent *, unsigned short [3]);
+long   jrand48 (unsigned short [3]);
+long   _jrand48_r (struct _reent *, unsigned short [3]);
+void  lcong48 (unsigned short [7]);
+void  _lcong48_r (struct _reent *, unsigned short [7]);
+long   lrand48 (void);
+long   _lrand48_r (struct _reent *);
+long   mrand48 (void);
+long   _mrand48_r (struct _reent *);
+long   nrand48 (unsigned short [3]);
+long   _nrand48_r (struct _reent *, unsigned short [3]);
+unsigned short *
+       seed48 (unsigned short [3]);
+unsigned short *
+       _seed48_r (struct _reent *, unsigned short [3]);
+void  srand48 (long);
+void  _srand48_r (struct _reent *, long);
+#endif /* __SVID_VISIBLE || __XSI_VISIBLE */
+#if __SVID_VISIBLE || __XSI_VISIBLE >= 4 || __BSD_VISIBLE
+char *	initstate (unsigned, char *, size_t);
+long	random (void);
+char *	setstate (char *);
+void	srandom (unsigned);
+#endif
+#if __ISO_C_VISIBLE >= 1999
+long long atoll (const char *__nptr);
+#endif
+long long _atoll_r (struct _reent *, const char *__nptr);
+#if __ISO_C_VISIBLE >= 1999
+long long llabs (long long);
+lldiv_t	lldiv (long long __numer, long long __denom);
+long long strtoll (const char *__restrict __n, char **__restrict __end_PTR, int __base);
+#endif
+long long _strtoll_r (struct _reent *, const char *__restrict __n, char **__restrict __end_PTR, int __base);
+#if __ISO_C_VISIBLE >= 1999
+unsigned long long strtoull (const char *__restrict __n, char **__restrict __end_PTR, int __base);
+#endif
+unsigned long long _strtoull_r (struct _reent *, const char *__restrict __n, char **__restrict __end_PTR, int __base);
+
+#ifndef __CYGWIN__
+#if __MISC_VISIBLE
+void	cfree (void *);
+#endif
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200112
+int	unsetenv (const char *__string);
+#endif
+int	_unsetenv_r (struct _reent *, const char *__string);
+#endif /* !__CYGWIN__ */
+
+#if __POSIX_VISIBLE >= 200112
+int	posix_memalign (void **, size_t, size_t) __nonnull((1))
+	    __result_use_check;
+#endif
+
+char *	_dtoa_r (struct _reent *, double, int, int, int *, int*, char**);
+#ifndef __CYGWIN__
+void *	_malloc_r (struct _reent *, size_t) _NOTHROW;
+void *	_calloc_r (struct _reent *, size_t, size_t) _NOTHROW;
+void	_free_r (struct _reent *, void *) _NOTHROW;
+void *	_realloc_r (struct _reent *, void *, size_t) _NOTHROW;
+void	_mstats_r (struct _reent *, char *);
+#endif
+int	_system_r (struct _reent *, const char *);
+
+void	__eprintf (const char *, const char *, unsigned int, const char *);
+
+/* There are two common qsort_r variants.  If you request
+   _BSD_SOURCE, you get the BSD version; otherwise you get the GNU
+   version.  We want that #undef qsort_r will still let you
+   invoke the underlying function, but that requires gcc support. */
+#if __GNU_VISIBLE
+void	qsort_r (void *__base, size_t __nmemb, size_t __size, int (*_compar)(const void *, const void *, void *), void *__thunk);
+#elif __BSD_VISIBLE
+# ifdef __GNUC__
+void	qsort_r (void *__base, size_t __nmemb, size_t __size, void *__thunk, int (*_compar)(void *, const void *, const void *))
+             __asm__ (__ASMNAME ("__bsd_qsort_r"));
+# else
+void	__bsd_qsort_r (void *__base, size_t __nmemb, size_t __size, void *__thunk, int (*_compar)(void *, const void *, const void *));
+#  define qsort_r __bsd_qsort_r
+# endif
+#endif
+
+/* On platforms where long double equals double.  */
+#ifdef _HAVE_LONG_DOUBLE
+extern long double _strtold_r (struct _reent *, const char *__restrict, char **__restrict);
+#if __ISO_C_VISIBLE >= 1999
+extern long double strtold (const char *__restrict, char **__restrict);
+#endif
+#endif /* _HAVE_LONG_DOUBLE */
+
+/*
+ * If we're in a mode greater than C99, expose C11 functions.
+ */
+#if __ISO_C_VISIBLE >= 2011
+void *	aligned_alloc(size_t, size_t) __malloc_like __alloc_align(1)
+	    __alloc_size(2) __result_use_check;
+int	at_quick_exit(void (*)(void));
+_Noreturn void
+	quick_exit(int);
+#endif /* __ISO_C_VISIBLE >= 2011 */
+
+_END_STD_C
+
+#if __SSP_FORTIFY_LEVEL > 0
+#include <ssp/stdlib.h>
+#endif
+
+#endif /* _STDLIB_H_ */

src/include/string.h

@@ -0,0 +1,183 @@
+/*
+ * string.h
+ *
+ * Definitions for memory and string functions.
+ */
+
+#ifndef _STRING_H_
+#define	_STRING_H_
+
+#include "_ansi.h"
+#include <sys/reent.h>
+#include <sys/cdefs.h>
+#include <sys/features.h>
+
+#define __need_size_t
+#define __need_NULL
+#include <stddef.h>
+
+#if __POSIX_VISIBLE >= 200809
+#include <xlocale.h>
+#endif
+
+#if __BSD_VISIBLE
+#include <strings.h>
+#endif
+
+_BEGIN_STD_C
+
+void *	 memchr (const void *, int, size_t);
+int 	 memcmp (const void *, const void *, size_t);
+void *	 memcpy (void *__restrict, const void *__restrict, size_t);
+void *	 memmove (void *, const void *, size_t);
+void *	 memset (void *, int, size_t);
+char 	*strcat (char *__restrict, const char *__restrict);
+char 	*strchr (const char *, int);
+int	 strcmp (const char *, const char *);
+int	 strcoll (const char *, const char *);
+char 	*strcpy (char *__restrict, const char *__restrict);
+size_t	 strcspn (const char *, const char *);
+char 	*strerror (int);
+size_t	 strlen (const char *);
+char 	*strncat (char *__restrict, const char *__restrict, size_t);
+int	 strncmp (const char *, const char *, size_t);
+char 	*strncpy (char *__restrict, const char *__restrict, size_t);
+char 	*strpbrk (const char *, const char *);
+char 	*strrchr (const char *, int);
+size_t	 strspn (const char *, const char *);
+char 	*strstr (const char *, const char *);
+#ifndef _REENT_ONLY
+char 	*strtok (char *__restrict, const char *__restrict);
+#endif
+size_t	 strxfrm (char *__restrict, const char *__restrict, size_t);
+
+#if __POSIX_VISIBLE >= 200809
+int	 strcoll_l (const char *, const char *, locale_t);
+char	*strerror_l (int, locale_t);
+size_t	 strxfrm_l (char *__restrict, const char *__restrict, size_t, locale_t);
+#endif
+#if __MISC_VISIBLE || __POSIX_VISIBLE
+char 	*strtok_r (char *__restrict, const char *__restrict, char **__restrict);
+#endif
+#if __BSD_VISIBLE
+int	 timingsafe_bcmp (const void *, const void *, size_t);
+int	 timingsafe_memcmp (const void *, const void *, size_t);
+#endif
+#if __MISC_VISIBLE || __POSIX_VISIBLE
+void *	 memccpy (void *__restrict, const void *__restrict, int, size_t);
+#endif
+#if __GNU_VISIBLE
+void *	 mempcpy (void *, const void *, size_t);
+void *	 memmem (const void *, size_t, const void *, size_t);
+void *	 memrchr (const void *, int, size_t);
+void *	 rawmemchr (const void *, int);
+#endif
+#if __POSIX_VISIBLE >= 200809
+char 	*stpcpy (char *__restrict, const char *__restrict);
+char 	*stpncpy (char *__restrict, const char *__restrict, size_t);
+#endif
+#if __GNU_VISIBLE
+char	*strcasestr (const char *, const char *);
+char 	*strchrnul (const char *, int);
+#endif
+#if __MISC_VISIBLE || __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE >= 4
+char 	*strdup (const char *) __malloc_like __result_use_check;
+#endif
+char 	*_strdup_r (struct _reent *, const char *);
+#if __POSIX_VISIBLE >= 200809
+char 	*strndup (const char *, size_t) __malloc_like __result_use_check;
+#endif
+char 	*_strndup_r (struct _reent *, const char *, size_t);
+
+/* There are two common strerror_r variants.  If you request
+   _GNU_SOURCE, you get the GNU version; otherwise you get the POSIX
+   version.  POSIX requires that #undef strerror_r will still let you
+   invoke the underlying function, but that requires gcc support.  */
+#if __GNU_VISIBLE
+char	*strerror_r (int, char *, size_t);
+#elif __POSIX_VISIBLE >= 200112
+# ifdef __GNUC__
+int	strerror_r (int, char *, size_t)
+#ifdef __ASMNAME
+             __asm__ (__ASMNAME ("__xpg_strerror_r"))
+#endif
+  ;
+# else
+int	__xpg_strerror_r (int, char *, size_t);
+#  define strerror_r __xpg_strerror_r
+# endif
+#endif
+
+/* Reentrant version of strerror.  */
+char *	_strerror_r (struct _reent *, int, int, int *);
+
+#if __BSD_VISIBLE
+size_t	strlcat (char *, const char *, size_t);
+size_t	strlcpy (char *, const char *, size_t);
+#endif
+#if __POSIX_VISIBLE >= 200809
+size_t	 strnlen (const char *, size_t);
+#endif
+#if __BSD_VISIBLE
+char 	*strsep (char **, const char *);
+#endif
+#if __BSD_VISIBLE
+char    *strnstr(const char *, const char *, size_t) __pure;
+#endif
+
+#if __MISC_VISIBLE
+char	*strlwr (char *);
+char	*strupr (char *);
+#endif
+
+#ifndef DEFS_H	/* Kludge to work around problem compiling in gdb */
+char	*strsignal (int __signo);
+#endif
+
+#ifdef __CYGWIN__
+int	strtosigno (const char *__name);
+#endif
+
+#if __GNU_VISIBLE
+int	 strverscmp (const char *, const char *);
+#endif
+
+#if __GNU_VISIBLE && defined(__GNUC__)
+#define strdupa(__s) \
+	(__extension__ ({const char *__sin = (__s); \
+			 size_t __len = strlen (__sin) + 1; \
+			 char * __sout = (char *) __builtin_alloca (__len); \
+			 (char *) memcpy (__sout, __sin, __len);}))
+#define strndupa(__s, __n) \
+	(__extension__ ({const char *__sin = (__s); \
+			 size_t __len = strnlen (__sin, (__n)) + 1; \
+			 char *__sout = (char *) __builtin_alloca (__len); \
+			 __sout[__len-1] = '\0'; \
+			 (char *) memcpy (__sout, __sin, __len-1);}))
+#endif /* __GNU_VISIBLE && __GNUC__ */
+
+/* There are two common basename variants.  If you do NOT #include <libgen.h>
+   and you do
+
+     #define _GNU_SOURCE
+     #include <string.h>
+
+   you get the GNU version.  Otherwise you get the POSIX versionfor which you
+   should #include <libgen.h>i for the function prototype.  POSIX requires that
+   #undef basename will still let you invoke the underlying function.  However,
+   this also implies that the POSIX version is used in this case.  That's made
+   sure here. */
+#if __GNU_VISIBLE && !defined(basename)
+# define basename basename
+char	*__nonnull ((1)) basename (const char *) __asm__(__ASMNAME("__gnu_basename"));
+#endif
+
+#include <sys/string.h>
+
+_END_STD_C
+
+#if __SSP_FORTIFY_LEVEL > 0
+#include <ssp/string.h>
+#endif
+
+#endif /* _STRING_H_ */

src/include/strings.h

@@ -0,0 +1,80 @@
+/*-
+ * Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD: head/include/strings.h 272673 2014-10-07 04:54:11Z delphij $
+ */
+
+#ifndef _STRINGS_H_
+#define	_STRINGS_H_
+
+#include <sys/cdefs.h>
+#include <sys/_types.h>
+
+#if __POSIX_VISIBLE >= 200809
+#include <xlocale.h>
+#endif
+
+#ifndef _SIZE_T_DECLARED
+typedef	__size_t	size_t;
+#define	_SIZE_T_DECLARED
+#endif
+
+__BEGIN_DECLS
+#if __BSD_VISIBLE || __POSIX_VISIBLE <= 200112
+int	 bcmp(const void *, const void *, size_t) __pure;	/* LEGACY */
+void	 bcopy(const void *, void *, size_t);			/* LEGACY */
+void	 bzero(void *, size_t);					/* LEGACY */
+#endif
+#if __BSD_VISIBLE
+void	 explicit_bzero(void *, size_t);
+#endif
+#if __MISC_VISIBLE || __POSIX_VISIBLE < 200809 || __XSI_VISIBLE >= 700
+int	 ffs(int) __pure2;
+#endif
+#if __BSD_VISIBLE
+int	 ffsl(long) __pure2;
+int	 ffsll(long long) __pure2;
+int	 fls(int) __pure2;
+int	 flsl(long) __pure2;
+int	 flsll(long long) __pure2;
+#endif
+#if __BSD_VISIBLE || __POSIX_VISIBLE <= 200112
+char	*index(const char *, int) __pure;			/* LEGACY */
+char	*rindex(const char *, int) __pure;			/* LEGACY */
+#endif
+int	 strcasecmp(const char *, const char *) __pure;
+int	 strncasecmp(const char *, const char *, size_t) __pure;
+
+#if __POSIX_VISIBLE >= 200809
+int	 strcasecmp_l (const char *, const char *, locale_t);
+int	 strncasecmp_l (const char *, const char *, size_t, locale_t);
+#endif
+__END_DECLS
+
+#if __SSP_FORTIFY_LEVEL > 0
+#include <ssp/strings.h>
+#endif
+
+#endif /* _STRINGS_H_ */

src/include/sys/_intsup.h

@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2004, 2005 by
+ * Ralf Corsepius, Ulm/Germany. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+#ifndef _SYS__INTSUP_H
+#define _SYS__INTSUP_H
+
+#include <sys/features.h>
+
+#if __GNUC_PREREQ (3, 2)
+/* gcc > 3.2 implicitly defines the values we are interested */
+#define __STDINT_EXP(x) __##x##__
+#else
+#define __STDINT_EXP(x) x
+#include <limits.h>
+#endif
+
+/* Determine how intptr_t and intN_t fastN_t and leastN_t are defined by gcc
+   for this target.  This is used to determine the correct printf() constant in
+   inttypes.h and other  constants in stdint.h.
+   So we end up with
+   ?(signed|unsigned) char == 0
+   ?(signed|unsigned) short == 1
+   ?(signed|unsigned) int == 2
+   ?(signed|unsigned) short int == 3
+   ?(signed|unsigned) long == 4
+   ?(signed|unsigned) long int == 6
+   ?(signed|unsigned) long long == 8
+   ?(signed|unsigned) long long int == 10
+ */
+#pragma push_macro("signed")
+#pragma push_macro("unsigned")
+#pragma push_macro("char")
+#pragma push_macro("short")
+#pragma push_macro("__int20")
+#pragma push_macro("int")
+#pragma push_macro("long")
+#undef signed
+#undef unsigned
+#undef char
+#undef short
+#undef int
+#undef __int20
+#undef long
+#define signed +0
+#define unsigned +0
+#define char +0
+#define short +1
+#define __int20 +2
+#define int +2
+#define long +4
+#if (__INTPTR_TYPE__ == 8 || __INTPTR_TYPE__ == 10)
+#define _INTPTR_EQ_LONGLONG
+#elif (__INTPTR_TYPE__ == 4 || __INTPTR_TYPE__ == 6)
+#define _INTPTR_EQ_LONG
+/* Note - the tests for _INTPTR_EQ_INT and _INTPTR_EQ_SHORT are currently
+   redundant as the values are not used.  But one day they may be needed
+   and so the tests remain.  */
+#elif __INTPTR_TYPE__ == 2
+#define _INTPTR_EQ_INT
+#elif (__INTPTR_TYPE__ == 1 || __INTPTR_TYPE__ == 3)
+#define _INTPTR_EQ_SHORT
+#else
+#error "Unable to determine type definition of intptr_t"
+#endif
+#if (__INT32_TYPE__ == 4 || __INT32_TYPE__ == 6)
+#define _INT32_EQ_LONG
+#elif __INT32_TYPE__ == 2
+/* Nothing to define because int32_t is safe to print as an int. */
+#else
+#error "Unable to determine type definition of int32_t"
+#endif
+
+#if (__INT8_TYPE__ == 0)
+#define __INT8 "hh"
+#elif (__INT8_TYPE__ == 1 || __INT8_TYPE__ == 3)
+#define __INT8 "h"
+#elif (__INT8_TYPE__ == 2)
+#define __INT8
+#elif (__INT8_TYPE__ == 4 || __INT8_TYPE__ == 6)
+#define __INT8 "l"
+#elif (__INT8_TYPE__ == 8 || __INT8_TYPE__ == 10)
+#define __INT8 "ll"
+#endif
+#if (__INT16_TYPE__ == 1 || __INT16_TYPE__ == 3)
+#define __INT16 "h"
+#elif (__INT16_TYPE__ == 2)
+#define __INT16
+#elif (__INT16_TYPE__ == 4 || __INT16_TYPE__ == 6)
+#define __INT16 "l"
+#elif (__INT16_TYPE__ == 8 || __INT16_TYPE__ == 10)
+#define __INT16 "ll"
+#endif
+#if (__INT32_TYPE__ == 2)
+#define __INT32
+#elif (__INT32_TYPE__ == 4 || __INT32_TYPE__ == 6)
+#define __INT32 "l"
+#elif (__INT32_TYPE__ == 8 || __INT32_TYPE__ == 10)
+#define __INT32 "ll"
+#endif
+#if (__INT64_TYPE__ == 2)
+#define __INT64
+#elif (__INT64_TYPE__ == 4 || __INT64_TYPE__ == 6)
+#define __INT64 "l"
+#elif (__INT64_TYPE__ == 8 || __INT64_TYPE__ == 10)
+#define __INT64 "ll"
+#endif
+#if (__INT_FAST8_TYPE__ == 0)
+#define __FAST8 "hh"
+#elif (__INT_FAST8_TYPE__ == 1 || __INT_FAST8_TYPE__ == 3)
+#define __FAST8 "h"
+#elif (__INT_FAST8_TYPE__ == 2)
+#define __FAST8
+#elif (__INT_FAST8_TYPE__ == 4 || __INT_FAST8_TYPE__ == 6)
+#define __FAST8 "l"
+#elif (__INT_FAST8_TYPE__ == 8 || __INT_FAST8_TYPE__ == 10)
+#define __FAST8 "ll"
+#endif
+#if (__INT_FAST16_TYPE__ == 1 || __INT_FAST16_TYPE__ == 3)
+#define __FAST16 "h"
+#elif (__INT_FAST16_TYPE__ == 2)
+#define __FAST16
+#elif (__INT_FAST16_TYPE__ == 4 || __INT_FAST16_TYPE__ == 6)
+#define __FAST16 "l"
+#elif (__INT_FAST16_TYPE__ == 8 || __INT_FAST16_TYPE__ == 10)
+#define __FAST16 "ll"
+#endif
+#if (__INT_FAST32_TYPE__ == 2)
+#define __FAST32
+#elif (__INT_FAST32_TYPE__ == 4 || __INT_FAST32_TYPE__ == 6)
+#define __FAST32 "l"
+#elif (__INT_FAST32_TYPE__ == 8 || __INT_FAST32_TYPE__ == 10)
+#define __FAST32 "ll"
+#endif
+#if (__INT_FAST64_TYPE__ == 2)
+#define __FAST64
+#elif (__INT_FAST64_TYPE__ == 4 || __INT_FAST64_TYPE__ == 6)
+#define __FAST64 "l"
+#elif (__INT_FAST64_TYPE__ == 8 || __INT_FAST64_TYPE__ == 10)
+#define __FAST64 "ll"
+#endif
+
+#if (__INT_LEAST8_TYPE__ == 0)
+#define __LEAST8 "hh"
+#elif (__INT_LEAST8_TYPE__ == 1 || __INT_LEAST8_TYPE__ == 3)
+#define __LEAST8 "h"
+#elif (__INT_LEAST8_TYPE__ == 2)
+#define __LEAST8
+#elif (__INT_LEAST8_TYPE__ == 4 || __INT_LEAST8_TYPE__ == 6)
+#define __LEAST8 "l"
+#elif (__INT_LEAST8_TYPE__ == 8 || __INT_LEAST8_TYPE__ == 10)
+#define __LEAST8 "ll"
+#endif
+#if (__INT_LEAST16_TYPE__ == 1 || __INT_LEAST16_TYPE__ == 3)
+#define __LEAST16 "h"
+#elif (__INT_LEAST16_TYPE__ == 2)
+#define __LEAST16
+#elif (__INT_LEAST16_TYPE__ == 4 || __INT_LEAST16_TYPE__ == 6)
+#define __LEAST16 "l"
+#elif (__INT_LEAST16_TYPE__ == 8 || __INT_LEAST16_TYPE__ == 10)
+#define __LEAST16 "ll"
+#endif
+#if (__INT_LEAST32_TYPE__ == 2)
+#define __LEAST32
+#elif (__INT_LEAST32_TYPE__ == 4 || __INT_LEAST32_TYPE__ == 6)
+#define __LEAST32 "l"
+#elif (__INT_LEAST32_TYPE__ == 8 || __INT_LEAST32_TYPE__ == 10)
+#define __LEAST32 "ll"
+#endif
+#if (__INT_LEAST64_TYPE__ == 2)
+#define __LEAST64
+#elif (__INT_LEAST64_TYPE__ == 4 || __INT_LEAST64_TYPE__ == 6)
+#define __LEAST64 "l"
+#elif (__INT_LEAST64_TYPE__ == 8 || __INT_LEAST64_TYPE__ == 10)
+#define __LEAST64 "ll"
+#endif
+#undef signed
+#undef unsigned
+#undef char
+#undef short
+#undef int
+#undef long
+#pragma pop_macro("signed")
+#pragma pop_macro("unsigned")
+#pragma pop_macro("char")
+#pragma pop_macro("short")
+#pragma pop_macro("__int20")
+#pragma pop_macro("int")
+#pragma pop_macro("long")
+
+#endif /* _SYS__INTSUP_H */

src/include/sys/_pthreadtypes.h

@@ -0,0 +1,233 @@
+/*
+ *  Written by Joel Sherrill <joel.sherrill@OARcorp.com>.
+ *
+ *  COPYRIGHT (c) 1989-2013, 2015.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Permission to use, copy, modify, and distribute this software for any
+ *  purpose without fee is hereby granted, provided that this entire notice
+ *  is included in all copies of any software which is or includes a copy
+ *  or modification of this software.
+ *
+ *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
+ *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
+ *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
+ */
+
+#ifndef _SYS__PTHREADTYPES_H_
+#define	_SYS__PTHREADTYPES_H_
+
+#if defined(_POSIX_THREADS) || __POSIX_VISIBLE >= 199506
+
+#include <sys/sched.h>
+
+/*
+ *  2.5 Primitive System Data Types,  P1003.1c/D10, p. 19.
+ */
+
+#if defined(__XMK__)
+typedef unsigned int pthread_t;          /* identify a thread */
+#else
+typedef __uint32_t pthread_t;            /* identify a thread */
+#endif
+
+/* P1003.1c/D10, p. 118-119 */
+#define PTHREAD_SCOPE_PROCESS 0
+#define PTHREAD_SCOPE_SYSTEM  1
+
+/* P1003.1c/D10, p. 111 */
+#define PTHREAD_INHERIT_SCHED  1      /* scheduling policy and associated */
+                                      /*   attributes are inherited from */
+                                      /*   the calling thread. */
+#define PTHREAD_EXPLICIT_SCHED 2      /* set from provided attribute object */
+
+/* P1003.1c/D10, p. 141 */
+#define PTHREAD_CREATE_DETACHED 0
+#define PTHREAD_CREATE_JOINABLE  1
+
+#if defined(__XMK__)
+typedef struct pthread_attr_s {
+  int contentionscope;
+  struct sched_param schedparam;
+  int  detachstate;
+  void *stackaddr;
+  size_t stacksize;
+} pthread_attr_t;
+
+#define PTHREAD_STACK_MIN       200
+
+#else /* !defined(__XMK__) */
+typedef struct {
+  int is_initialized;
+  void *stackaddr;
+  int stacksize;
+  int contentionscope;
+  int inheritsched;
+  int schedpolicy;
+  struct sched_param schedparam;
+
+  /* P1003.4b/D8, p. 54 adds cputime_clock_allowed attribute.  */
+#if defined(_POSIX_THREAD_CPUTIME)
+  int  cputime_clock_allowed;  /* see time.h */
+#endif
+  int  detachstate;
+} pthread_attr_t;
+
+#endif /* !defined(__XMK__) */
+
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+/* NOTE: P1003.1c/D10, p. 81 defines following values for process_shared.  */
+
+#define PTHREAD_PROCESS_PRIVATE 0 /* visible within only the creating process */
+#define PTHREAD_PROCESS_SHARED  1 /* visible too all processes with access to */
+                                  /*   the memory where the resource is */
+                                  /*   located */
+#endif
+
+#if defined(_POSIX_THREAD_PRIO_PROTECT)
+/* Mutexes */
+
+/* Values for blocking protocol. */
+
+#define PTHREAD_PRIO_NONE    0
+#define PTHREAD_PRIO_INHERIT 1
+#define PTHREAD_PRIO_PROTECT 2
+#endif
+
+#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
+
+/* Values for mutex type */
+
+/* The following defines are part of the X/Open System Interface (XSI). */
+
+/*
+ * This type of mutex does not detect deadlock. A thread attempting to
+ * relock this mutex without first unlocking it shall deadlock. Attempting
+ * to unlock a mutex locked by a different thread results in undefined
+ * behavior.  Attempting to unlock an unlocked mutex results in undefined
+ * behavior.
+ */
+#define PTHREAD_MUTEX_NORMAL     0
+
+/*
+ * A thread attempting to relock this mutex without first unlocking
+ * it shall succeed in locking the mutex.  The relocking deadlock which
+ * can occur with mutexes of type PTHREAD_MUTEX_NORMAL cannot occur with
+ * this type of mutex.  Multiple locks of this mutex shall require the
+ * same number of unlocks to release the mutex before another thread can
+ * acquire the mutex. A thread attempting to unlock a mutex which another
+ * thread has locked shall return with an error.  A thread attempting to
+ * unlock an unlocked mutex shall return with an error.
+ */
+#define PTHREAD_MUTEX_RECURSIVE  1
+
+/*
+ * This type of mutex provides error checking. A thread attempting
+ * to relock this mutex without first unlocking it shall return with an
+ * error. A thread attempting to unlock a mutex which another thread has
+ * locked shall return with an error. A thread attempting to unlock an
+ * unlocked mutex shall return with an error.
+ */
+#define PTHREAD_MUTEX_ERRORCHECK 2
+
+/*
+ * Attempting to recursively lock a mutex of this type results
+ * in undefined behavior. Attempting to unlock a mutex of this type
+ * which was not locked by the calling thread results in undefined
+ * behavior. Attempting to unlock a mutex of this type which is not locked
+ * results in undefined behavior. An implementation may map this mutex to
+ * one of the other mutex types.
+ */
+#define PTHREAD_MUTEX_DEFAULT    3
+
+#endif /* !defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES) */
+
+#if defined(__XMK__)
+typedef unsigned int pthread_mutex_t;    /* identify a mutex */
+
+typedef struct {
+  int type;
+} pthread_mutexattr_t;
+
+#else /* !defined(__XMK__) */
+typedef __uint32_t pthread_mutex_t;      /* identify a mutex */
+
+typedef struct {
+  int   is_initialized;
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int   process_shared;  /* allow mutex to be shared amongst processes */
+#endif
+#if defined(_POSIX_THREAD_PRIO_PROTECT)
+  int   prio_ceiling;
+  int   protocol;
+#endif
+#if defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES)
+  int type;
+#endif
+  int   recursive;
+} pthread_mutexattr_t;
+#endif /* !defined(__XMK__) */
+
+#define _PTHREAD_MUTEX_INITIALIZER ((pthread_mutex_t) 0xFFFFFFFF)
+
+/* Condition Variables */
+
+typedef __uint32_t pthread_cond_t;       /* identify a condition variable */
+
+#define _PTHREAD_COND_INITIALIZER ((pthread_cond_t) 0xFFFFFFFF)
+
+typedef struct {
+  int      is_initialized;
+  clock_t  clock;             /* specifiy clock for timeouts */
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int      process_shared;    /* allow this to be shared amongst processes */
+#endif
+} pthread_condattr_t;         /* a condition attribute object */
+
+/* Keys */
+
+typedef __uint32_t pthread_key_t;        /* thread-specific data keys */
+
+typedef struct {
+  int   is_initialized;  /* is this structure initialized? */
+  int   init_executed;   /* has the initialization routine been run? */
+} pthread_once_t;       /* dynamic package initialization */
+
+#define _PTHREAD_ONCE_INIT  { 1, 0 }  /* is initialized and not run */
+#endif /* defined(_POSIX_THREADS) || __POSIX_VISIBLE >= 199506 */
+
+/* POSIX Barrier Types */
+
+#if defined(_POSIX_BARRIERS)
+typedef __uint32_t pthread_barrier_t;        /* POSIX Barrier Object */
+typedef struct {
+  int   is_initialized;  /* is this structure initialized? */
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int   process_shared;       /* allow this to be shared amongst processes */
+#endif
+} pthread_barrierattr_t;
+#endif /* defined(_POSIX_BARRIERS) */
+
+/* POSIX Spin Lock Types */
+
+#if defined(_POSIX_SPIN_LOCKS)
+typedef __uint32_t pthread_spinlock_t;        /* POSIX Spin Lock Object */
+#endif /* defined(_POSIX_SPIN_LOCKS) */
+
+/* POSIX Reader/Writer Lock Types */
+
+#if defined(_POSIX_READER_WRITER_LOCKS)
+typedef __uint32_t pthread_rwlock_t;         /* POSIX RWLock Object */
+
+#define _PTHREAD_RWLOCK_INITIALIZER ((pthread_rwlock_t) 0xFFFFFFFF)
+
+typedef struct {
+  int   is_initialized;       /* is this structure initialized? */
+#if defined(_POSIX_THREAD_PROCESS_SHARED)
+  int   process_shared;       /* allow this to be shared amongst processes */
+#endif
+} pthread_rwlockattr_t;
+#endif /* defined(_POSIX_READER_WRITER_LOCKS) */
+
+#endif /* ! _SYS__PTHREADTYPES_H_ */

src/include/sys/_sigset.h

@@ -0,0 +1,43 @@
+/*-
+ * Copyright (c) 1982, 1986, 1989, 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ * (c) UNIX System Laboratories, Inc.
+ * All or some portions of this file are derived from material licensed
+ * to the University of California by American Telephone and Telegraph
+ * Co. or Unix System Laboratories, Inc. and are reproduced herein with
+ * the permission of UNIX System Laboratories, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)signal.h	8.4 (Berkeley) 5/4/95
+ * $FreeBSD$
+ */
+
+#ifndef _SYS__SIGSET_H_
+#define	_SYS__SIGSET_H_
+
+typedef unsigned long __sigset_t;
+
+#endif /* !_SYS__SIGSET_H_ */

src/include/sys/_stdint.h

@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2004, 2005 by
+ * Ralf Corsepius, Ulm/Germany. All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software
+ * is freely granted, provided that this notice is preserved.
+ */
+
+#ifndef _SYS__STDINT_H
+#define _SYS__STDINT_H
+
+#include <machine/_default_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef ___int8_t_defined
+#ifndef _INT8_T_DECLARED
+typedef __int8_t int8_t ;
+#define _INT8_T_DECLARED
+#endif
+#ifndef _UINT8_T_DECLARED
+typedef __uint8_t uint8_t ;
+#define _UINT8_T_DECLARED
+#endif
+#define __int8_t_defined 1
+#endif /* ___int8_t_defined */
+
+#ifdef ___int16_t_defined
+#ifndef _INT16_T_DECLARED
+typedef __int16_t int16_t ;
+#define _INT16_T_DECLARED
+#endif
+#ifndef _UINT16_T_DECLARED
+typedef __uint16_t uint16_t ;
+#define _UINT16_T_DECLARED
+#endif
+#define __int16_t_defined 1
+#endif /* ___int16_t_defined */
+
+#ifdef ___int32_t_defined
+#ifndef _INT32_T_DECLARED
+typedef __int32_t int32_t ;
+#define _INT32_T_DECLARED
+#endif
+#ifndef _UINT32_T_DECLARED
+typedef __uint32_t uint32_t ;
+#define _UINT32_T_DECLARED
+#endif
+#define __int32_t_defined 1
+#endif /* ___int32_t_defined */
+
+#ifdef ___int64_t_defined
+#ifndef _INT64_T_DECLARED
+typedef __int64_t int64_t ;
+#define _INT64_T_DECLARED
+#endif
+#ifndef _UINT64_T_DECLARED
+typedef __uint64_t uint64_t ;
+#define _UINT64_T_DECLARED
+#endif
+#define __int64_t_defined 1
+#endif /* ___int64_t_defined */
+
+#ifndef _INTMAX_T_DECLARED
+typedef __intmax_t intmax_t;
+#define _INTMAX_T_DECLARED
+#endif
+
+#ifndef _UINTMAX_T_DECLARED
+typedef __uintmax_t uintmax_t;
+#define _UINTMAX_T_DECLARED
+#endif
+
+#ifndef _INTPTR_T_DECLARED
+typedef __intptr_t intptr_t;
+#define _INTPTR_T_DECLARED
+#endif
+
+#ifndef _UINTPTR_T_DECLARED
+typedef __uintptr_t uintptr_t;
+#define _UINTPTR_T_DECLARED
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYS__STDINT_H */

src/include/sys/_timespec.h

@@ -0,0 +1,50 @@
+/*-
+ * Copyright (c) 1982, 1986, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)time.h	8.5 (Berkeley) 5/4/95
+ * from: FreeBSD: src/sys/sys/time.h,v 1.43 2000/03/20 14:09:05 phk Exp
+ *	$FreeBSD$
+ */
+
+#ifndef _SYS__TIMESPEC_H_
+#define	_SYS__TIMESPEC_H_
+
+#include <sys/_types.h>
+
+#if !defined(__time_t_defined) && !defined(_TIME_T_DECLARED)
+typedef	_TIME_T_	time_t;
+#define	__time_t_defined
+#define	_TIME_T_DECLARED
+#endif
+
+struct timespec {
+	time_t	tv_sec;		/* seconds */
+	long	tv_nsec;	/* and nanoseconds */
+};
+
+#endif /* !_SYS__TIMESPEC_H_ */

src/include/sys/_timeval.h

@@ -0,0 +1,89 @@
+/*-
+ * Copyright (c) 2002 Mike Barcroft <mike@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _SYS__TIMEVAL_H_
+#define _SYS__TIMEVAL_H_
+
+#include <sys/_types.h>
+
+#ifndef _SUSECONDS_T_DECLARED
+typedef	__suseconds_t	suseconds_t;
+#define	_SUSECONDS_T_DECLARED
+#endif
+
+#if !defined(__time_t_defined) && !defined(_TIME_T_DECLARED)
+typedef	_TIME_T_	time_t;
+#define	__time_t_defined
+#define	_TIME_T_DECLARED
+#endif
+
+/* This define is also used outside of Newlib, e.g. in MinGW-w64 */
+#ifndef _TIMEVAL_DEFINED
+#define _TIMEVAL_DEFINED
+
+/*
+ * Structure returned by gettimeofday(2) system call, and used in other calls.
+ */
+struct timeval {
+	time_t		tv_sec;		/* seconds */
+	suseconds_t	tv_usec;	/* and microseconds */
+};
+
+#if __BSD_VISIBLE
+#ifndef _KERNEL			/* NetBSD/OpenBSD compatible interfaces */
+
+#define	timerclear(tvp)		((tvp)->tv_sec = (tvp)->tv_usec = 0)
+#define	timerisset(tvp)		((tvp)->tv_sec || (tvp)->tv_usec)
+#define	timercmp(tvp, uvp, cmp)					\
+	(((tvp)->tv_sec == (uvp)->tv_sec) ?				\
+	    ((tvp)->tv_usec cmp (uvp)->tv_usec) :			\
+	    ((tvp)->tv_sec cmp (uvp)->tv_sec))
+#define	timeradd(tvp, uvp, vvp)						\
+	do {								\
+		(vvp)->tv_sec = (tvp)->tv_sec + (uvp)->tv_sec;		\
+		(vvp)->tv_usec = (tvp)->tv_usec + (uvp)->tv_usec;	\
+		if ((vvp)->tv_usec >= 1000000) {			\
+			(vvp)->tv_sec++;				\
+			(vvp)->tv_usec -= 1000000;			\
+		}							\
+	} while (0)
+#define	timersub(tvp, uvp, vvp)						\
+	do {								\
+		(vvp)->tv_sec = (tvp)->tv_sec - (uvp)->tv_sec;		\
+		(vvp)->tv_usec = (tvp)->tv_usec - (uvp)->tv_usec;	\
+		if ((vvp)->tv_usec < 0) {				\
+			(vvp)->tv_sec--;				\
+			(vvp)->tv_usec += 1000000;			\
+		}							\
+	} while (0)
+#endif
+#endif /* __BSD_VISIBLE */
+
+#endif /* _TIMEVAL_DEFINED */
+
+#endif /* !_SYS__TIMEVAL_H_ */

src/include/sys/_types.h

@@ -0,0 +1,224 @@
+/* ANSI C namespace clean utility typedefs */
+
+/* This file defines various typedefs needed by the system calls that support
+   the C library.  Basically, they're just the POSIX versions with an '_'
+   prepended.  Targets shall use <machine/_types.h> to define their own
+   internal types if desired.
+
+   There are three define patterns used for type definitions.  Lets assume
+   xyz_t is a user type.
+
+   The internal type definition uses __machine_xyz_t_defined.  It is defined by
+   <machine/_types.h> to disable a default definition in <sys/_types.h>. It
+   must not be used in other files.
+
+   User type definitions are guarded by __xyz_t_defined in glibc and
+   _XYZ_T_DECLARED in BSD compatible systems.
+*/
+
+#ifndef	_SYS__TYPES_H
+#define _SYS__TYPES_H
+
+#include <newlib.h>
+#include <sys/config.h>
+#include <machine/_types.h>
+#include <sys/lock.h>
+
+#ifndef __machine_blkcnt_t_defined
+typedef long __blkcnt_t;
+#endif
+
+#ifndef __machine_blksize_t_defined
+typedef long __blksize_t;
+#endif
+
+#ifndef __machine_fsblkcnt_t_defined
+typedef __uint64_t __fsblkcnt_t;
+#endif
+
+#ifndef __machine_fsfilcnt_t_defined
+typedef __uint32_t __fsfilcnt_t;
+#endif
+
+#ifndef __machine_off_t_defined
+typedef long _off_t;
+#endif
+
+#if defined(__XMK__)
+typedef signed char __pid_t;
+#else
+typedef int __pid_t;
+#endif
+
+#ifndef __machine_dev_t_defined
+typedef short __dev_t;
+#endif
+
+#ifndef __machine_uid_t_defined
+typedef unsigned short __uid_t;
+#endif
+#ifndef __machine_gid_t_defined
+typedef unsigned short __gid_t;
+#endif
+
+#ifndef __machine_id_t_defined
+typedef __uint32_t __id_t;
+#endif
+
+#ifndef __machine_ino_t_defined
+#if (defined(__i386__) && (defined(GO32) || defined(__MSDOS__))) || \
+    defined(__sparc__) || defined(__SPU__)
+typedef unsigned long __ino_t;
+#else
+typedef unsigned short __ino_t;
+#endif
+#endif
+
+#ifndef __machine_mode_t_defined
+#if defined(__i386__) && (defined(GO32) || defined(__MSDOS__))
+typedef int __mode_t;
+#else
+#if defined(__sparc__) && !defined(__sparc_v9__)
+#ifdef __svr4__
+typedef unsigned long __mode_t;
+#else
+typedef unsigned short __mode_t;
+#endif
+#else
+typedef __uint32_t __mode_t;
+#endif
+#endif
+#endif
+
+#ifndef __machine_off64_t_defined
+__extension__ typedef long long _off64_t;
+#endif
+
+#if defined(__CYGWIN__) && !defined(__LP64__)
+typedef _off64_t __off_t;
+#else
+typedef _off_t __off_t;
+#endif
+
+typedef _off64_t __loff_t;
+
+#ifndef __machine_key_t_defined
+typedef long __key_t;
+#endif
+
+/*
+ * We need fpos_t for the following, but it doesn't have a leading "_",
+ * so we use _fpos_t instead.
+ */
+#ifndef __machine_fpos_t_defined
+typedef long _fpos_t;		/* XXX must match off_t in <sys/types.h> */
+				/* (and must be `long' for now) */
+#endif
+
+#ifdef __LARGE64_FILES
+#ifndef __machine_fpos64_t_defined
+typedef _off64_t _fpos64_t;
+#endif
+#endif
+
+/* Defined by GCC provided <stddef.h> */
+#undef __size_t
+
+#ifndef __machine_size_t_defined
+#ifdef __SIZE_TYPE__
+typedef __SIZE_TYPE__ __size_t;
+#else
+#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
+typedef unsigned int __size_t;
+#else
+typedef unsigned long __size_t;
+#endif
+#endif
+#endif
+
+#ifndef __machine_ssize_t_defined
+#ifdef __SIZE_TYPE__
+/* If __SIZE_TYPE__ is defined (gcc) we define ssize_t based on size_t.
+   We simply change "unsigned" to "signed" for this single definition
+   to make sure ssize_t and size_t only differ by their signedness. */
+#define unsigned signed
+typedef __SIZE_TYPE__ _ssize_t;
+#undef unsigned
+#else
+#if defined(__INT_MAX__) && __INT_MAX__ == 2147483647
+typedef int _ssize_t;
+#else
+typedef long _ssize_t;
+#endif
+#endif
+#endif
+
+typedef _ssize_t __ssize_t;
+
+#define __need_wint_t
+#include <stddef.h>
+
+#ifndef __machine_mbstate_t_defined
+/* Conversion state information.  */
+typedef struct
+{
+  int __count;
+  union
+  {
+    wint_t __wch;
+    unsigned char __wchb[4];
+  } __value;		/* Value so far.  */
+} _mbstate_t;
+#endif
+
+#ifndef __machine_flock_t_defined
+typedef _LOCK_RECURSIVE_T _flock_t;
+#endif
+
+#ifndef __machine_iconv_t_defined
+/* Iconv descriptor type */
+typedef void *_iconv_t;
+#endif
+
+#ifndef __machine_clock_t_defined
+#define	_CLOCK_T_	unsigned long	/* clock() */
+#endif
+
+typedef	_CLOCK_T_	__clock_t;
+
+#if defined(_USE_LONG_TIME_T) || __LONG_MAX__ > 0x7fffffffL
+#define	_TIME_T_ long
+#else
+#define	_TIME_T_ __int_least64_t
+#endif
+typedef	_TIME_T_	__time_t;
+
+#ifndef __machine_clockid_t_defined
+#define	_CLOCKID_T_ 	unsigned long
+#endif
+
+typedef	_CLOCKID_T_	__clockid_t;
+
+#define	_TIMER_T_	unsigned long
+typedef	_TIMER_T_	__timer_t;
+
+#ifndef __machine_sa_family_t_defined
+typedef	__uint8_t	__sa_family_t;
+#endif
+
+#ifndef __machine_socklen_t_defined
+typedef	__uint32_t	__socklen_t;
+#endif
+
+typedef	int		__nl_item;
+typedef	unsigned short	__nlink_t;
+typedef	long		__suseconds_t;	/* microseconds (signed) */
+typedef	unsigned long	__useconds_t;	/* microseconds (unsigned) */
+
+#ifdef __GNUCLIKE_BUILTIN_VARARGS
+typedef	__builtin_va_list	__va_list;
+#else
+typedef	char *			__va_list;
+#endif /* __GNUCLIKE_BUILTIN_VARARGS */
+
+#endif	/* _SYS__TYPES_H */

src/include/sys/cdefs.h

@@ -0,0 +1,716 @@
+/* libc/sys/linux/sys/cdefs.h - Helper macros for K&R vs. ANSI C compat. */
+
+/* Written 2000 by Werner Almesberger */
+
+/*-
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * Berkeley Software Design, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)cdefs.h	8.8 (Berkeley) 1/9/95
+ * $FreeBSD$
+ */
+
+#ifndef	_SYS_CDEFS_H_
+#define	_SYS_CDEFS_H_
+
+#include <machine/_default_types.h>
+#include <sys/features.h>
+#include <stddef.h>
+
+#define __PMT(args)	args
+#define __DOTS    	, ...
+#define __THROW
+
+#ifdef __GNUC__
+# define __ASMNAME(cname)  __XSTRING (__USER_LABEL_PREFIX__) cname
+#endif
+
+#define __ptr_t void *
+#define __long_double_t  long double
+
+#define __attribute_malloc__
+#define __attribute_pure__
+#define __attribute_format_strfmon__(a,b)
+#define __flexarr      [0]
+
+#ifndef __BOUNDED_POINTERS__
+# define __bounded      /* nothing */
+# define __unbounded    /* nothing */
+# define __ptrvalue     /* nothing */
+#endif
+
+/*
+ * Testing against Clang-specific extensions.
+ */
+#ifndef	__has_attribute
+#define	__has_attribute(x)	0
+#endif
+#ifndef	__has_extension
+#define	__has_extension		__has_feature
+#endif
+#ifndef	__has_feature
+#define	__has_feature(x)	0
+#endif
+#ifndef	__has_include
+#define	__has_include(x)	0
+#endif
+#ifndef	__has_builtin
+#define	__has_builtin(x)	0
+#endif
+
+#if defined(__cplusplus)
+#define	__BEGIN_DECLS	extern "C" {
+#define	__END_DECLS	}
+#else
+#define	__BEGIN_DECLS
+#define	__END_DECLS
+#endif
+
+/*
+ * This code has been put in place to help reduce the addition of
+ * compiler specific defines in FreeBSD code.  It helps to aid in
+ * having a compiler-agnostic source tree.
+ */
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+
+#if __GNUC__ >= 3 || defined(__INTEL_COMPILER)
+#define	__GNUCLIKE_ASM 3
+#define	__GNUCLIKE_MATH_BUILTIN_CONSTANTS
+#else
+#define	__GNUCLIKE_ASM 2
+#endif
+#define	__GNUCLIKE___TYPEOF 1
+#define	__GNUCLIKE___OFFSETOF 1
+#define	__GNUCLIKE___SECTION 1
+
+#ifndef __INTEL_COMPILER
+#define	__GNUCLIKE_CTOR_SECTION_HANDLING 1
+#endif
+
+#define	__GNUCLIKE_BUILTIN_CONSTANT_P 1
+#if defined(__INTEL_COMPILER) && defined(__cplusplus) && \
+   __INTEL_COMPILER < 800
+#undef __GNUCLIKE_BUILTIN_CONSTANT_P
+#endif
+
+#if (__GNUC_MINOR__ > 95 || __GNUC__ >= 3)
+#define	__GNUCLIKE_BUILTIN_VARARGS 1
+#define	__GNUCLIKE_BUILTIN_STDARG 1
+#define	__GNUCLIKE_BUILTIN_VAALIST 1
+#endif
+
+#if defined(__GNUC__)
+#define	__GNUC_VA_LIST_COMPATIBILITY 1
+#endif
+
+/*
+ * Compiler memory barriers, specific to gcc and clang.
+ */
+#if defined(__GNUC__)
+#define	__compiler_membar()	__asm __volatile(" " : : : "memory")
+#endif
+
+#ifndef __INTEL_COMPILER
+#define	__GNUCLIKE_BUILTIN_NEXT_ARG 1
+#define	__GNUCLIKE_MATH_BUILTIN_RELOPS
+#endif
+
+#define	__GNUCLIKE_BUILTIN_MEMCPY 1
+
+/* XXX: if __GNUC__ >= 2: not tested everywhere originally, where replaced */
+#define	__CC_SUPPORTS_INLINE 1
+#define	__CC_SUPPORTS___INLINE 1
+#define	__CC_SUPPORTS___INLINE__ 1
+
+#define	__CC_SUPPORTS___FUNC__ 1
+#define	__CC_SUPPORTS_WARNING 1
+
+#define	__CC_SUPPORTS_VARADIC_XXX 1 /* see varargs.h */
+
+#define	__CC_SUPPORTS_DYNAMIC_ARRAY_INIT 1
+
+#endif /* __GNUC__ || __INTEL_COMPILER */
+
+/*
+ * The __CONCAT macro is used to concatenate parts of symbol names, e.g.
+ * with "#define OLD(foo) __CONCAT(old,foo)", OLD(foo) produces oldfoo.
+ * The __CONCAT macro is a bit tricky to use if it must work in non-ANSI
+ * mode -- there must be no spaces between its arguments, and for nested
+ * __CONCAT's, all the __CONCAT's must be at the left.  __CONCAT can also
+ * concatenate double-quoted strings produced by the __STRING macro, but
+ * this only works with ANSI C.
+ *
+ * __XSTRING is like __STRING, but it expands any macros in its argument
+ * first.  It is only available with ANSI C.
+ */
+#if defined(__STDC__) || defined(__cplusplus)
+#define	__P(protos)	protos		/* full-blown ANSI C */
+#define	__CONCAT1(x,y)	x ## y
+#define	__CONCAT(x,y)	__CONCAT1(x,y)
+#define	__STRING(x)	#x		/* stringify without expanding x */
+#define	__XSTRING(x)	__STRING(x)	/* expand x, then stringify */
+
+#define	__const		const		/* define reserved names to standard */
+#define	__signed	signed
+#define	__volatile	volatile
+#if defined(__cplusplus)
+#define	__inline	inline		/* convert to C++ keyword */
+#else
+#if !(defined(__CC_SUPPORTS___INLINE))
+#define	__inline			/* delete GCC keyword */
+#endif /* ! __CC_SUPPORTS___INLINE */
+#endif /* !__cplusplus */
+
+#else	/* !(__STDC__ || __cplusplus) */
+#define	__P(protos)	()		/* traditional C preprocessor */
+#define	__CONCAT(x,y)	x/**/y
+#define	__STRING(x)	"x"
+
+#if !defined(__CC_SUPPORTS___INLINE)
+#define	__const				/* delete pseudo-ANSI C keywords */
+#define	__inline
+#define	__signed
+#define	__volatile
+/*
+ * In non-ANSI C environments, new programs will want ANSI-only C keywords
+ * deleted from the program and old programs will want them left alone.
+ * When using a compiler other than gcc, programs using the ANSI C keywords
+ * const, inline etc. as normal identifiers should define -DNO_ANSI_KEYWORDS.
+ * When using "gcc -traditional", we assume that this is the intent; if
+ * __GNUC__ is defined but __STDC__ is not, we leave the new keywords alone.
+ */
+#ifndef	NO_ANSI_KEYWORDS
+#define	const				/* delete ANSI C keywords */
+#define	inline
+#define	signed
+#define	volatile
+#endif	/* !NO_ANSI_KEYWORDS */
+#endif	/* !__CC_SUPPORTS___INLINE */
+#endif	/* !(__STDC__ || __cplusplus) */
+
+/*
+ * Compiler-dependent macros to help declare dead (non-returning) and
+ * pure (no side effects) functions, and unused variables.  They are
+ * null except for versions of gcc that are known to support the features
+ * properly (old versions of gcc-2 supported the dead and pure features
+ * in a different (wrong) way).  If we do not provide an implementation
+ * for a given compiler, let the compile fail if it is told to use
+ * a feature that we cannot live without.
+ */
+#define	__weak_symbol	__attribute__((__weak__))
+#if !__GNUC_PREREQ__(2, 5) && !defined(__INTEL_COMPILER)
+#define	__dead2
+#define	__pure2
+#define	__unused
+#endif
+#if __GNUC__ == 2 && __GNUC_MINOR__ >= 5 && __GNUC_MINOR__ < 7 && !defined(__INTEL_COMPILER)
+#define	__dead2		__attribute__((__noreturn__))
+#define	__pure2		__attribute__((__const__))
+#define	__unused
+/* XXX Find out what to do for __packed, __aligned and __section */
+#endif
+#if __GNUC_PREREQ__(2, 7) || defined(__INTEL_COMPILER)
+#define	__dead2		__attribute__((__noreturn__))
+#define	__pure2		__attribute__((__const__))
+#define	__unused	__attribute__((__unused__))
+#define	__used		__attribute__((__used__))
+#define	__packed	__attribute__((__packed__))
+#define	__aligned(x)	__attribute__((__aligned__(x)))
+#define	__section(x)	__attribute__((__section__(x)))
+#endif
+#if __GNUC_PREREQ__(4, 3) || __has_attribute(__alloc_size__)
+#define	__alloc_size(x)	__attribute__((__alloc_size__(x)))
+#define	__alloc_size2(n, x)	__attribute__((__alloc_size__(n, x)))
+#else
+#define	__alloc_size(x)
+#define	__alloc_size2(n, x)
+#endif
+#if __GNUC_PREREQ__(4, 9) || __has_attribute(__alloc_align__)
+#define	__alloc_align(x)	__attribute__((__alloc_align__(x)))
+#else
+#define	__alloc_align(x)
+#endif
+
+#if !__GNUC_PREREQ__(2, 95)
+#define	__alignof(x)	__offsetof(struct { char __a; x __b; }, __b)
+#endif
+
+/*
+ * Keywords added in C11.
+ */
+
+#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 201112L
+
+#if !__has_extension(c_alignas)
+#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
+    __has_extension(cxx_alignas)
+#define	_Alignas(x)		alignas(x)
+#else
+/* XXX: Only emulates _Alignas(constant-expression); not _Alignas(type-name). */
+#define	_Alignas(x)		__aligned(x)
+#endif
+#endif
+
+#if defined(__cplusplus) && __cplusplus >= 201103L
+#define	_Alignof(x)		alignof(x)
+#else
+#define	_Alignof(x)		__alignof(x)
+#endif
+
+#if !defined(__cplusplus) && !__has_extension(c_atomic) && \
+    !__has_extension(cxx_atomic)
+/*
+ * No native support for _Atomic(). Place object in structure to prevent
+ * most forms of direct non-atomic access.
+ */
+#define	_Atomic(T)		struct { T volatile __val; }
+#endif
+
+#if defined(__cplusplus) && __cplusplus >= 201103L
+#define	_Noreturn		[[noreturn]]
+#else
+#define	_Noreturn		__dead2
+#endif
+
+#if !__has_extension(c_static_assert)
+#if (defined(__cplusplus) && __cplusplus >= 201103L) || \
+    __has_extension(cxx_static_assert)
+#define	_Static_assert(x, y)	static_assert(x, y)
+#elif __GNUC_PREREQ__(4,6) && !defined(__cplusplus)
+/* Nothing, gcc 4.6 and higher has _Static_assert built-in */
+#elif defined(__COUNTER__)
+#define	_Static_assert(x, y)	__Static_assert(x, __COUNTER__)
+#define	__Static_assert(x, y)	___Static_assert(x, y)
+#define	___Static_assert(x, y)	typedef char __assert_ ## y[(x) ? 1 : -1] \
+				__unused
+#else
+#define	_Static_assert(x, y)	struct __hack
+#endif
+#endif
+
+#if !__has_extension(c_thread_local)
+/*
+ * XXX: Some compilers (Clang 3.3, GCC 4.7) falsely announce C++11 mode
+ * without actually supporting the thread_local keyword. Don't check for
+ * the presence of C++11 when defining _Thread_local.
+ */
+#if /* (defined(__cplusplus) && __cplusplus >= 201103L) || */ \
+    __has_extension(cxx_thread_local)
+#define	_Thread_local		thread_local
+#else
+#define	_Thread_local		__thread
+#endif
+#endif
+
+#endif /* __STDC_VERSION__ || __STDC_VERSION__ < 201112L */
+
+/*
+ * Emulation of C11 _Generic().  Unlike the previously defined C11
+ * keywords, it is not possible to implement this using exactly the same
+ * syntax.  Therefore implement something similar under the name
+ * __generic().  Unlike _Generic(), this macro can only distinguish
+ * between a single type, so it requires nested invocations to
+ * distinguish multiple cases.
+ */
+
+#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \
+    __has_extension(c_generic_selections)
+#define	__generic(expr, t, yes, no)					\
+	_Generic(expr, t: yes, default: no)
+#elif __GNUC_PREREQ__(3, 1) && !defined(__cplusplus)
+#define	__generic(expr, t, yes, no)					\
+	__builtin_choose_expr(						\
+	    __builtin_types_compatible_p(__typeof(expr), t), yes, no)
+#endif
+
+/*
+ * C99 Static array indices in function parameter declarations.  Syntax such as:
+ * void bar(int myArray[static 10]);
+ * is allowed in C99 but not in C++.  Define __min_size appropriately so
+ * headers using it can be compiled in either language.  Use like this:
+ * void bar(int myArray[__min_size(10)]);
+ */
+#if !defined(__cplusplus) && \
+    (defined(__clang__) || __GNUC_PREREQ__(4, 6)) && \
+    (!defined(__STDC_VERSION__) || (__STDC_VERSION__ >= 199901))
+#define __min_size(x)	static (x)
+#else
+#define __min_size(x)	(x)
+#endif
+
+#if __GNUC_PREREQ__(2, 96)
+#define	__malloc_like	__attribute__((__malloc__))
+#define	__pure		__attribute__((__pure__))
+#else
+#define	__malloc_like
+#define	__pure
+#endif
+
+#if __GNUC_PREREQ__(3, 1) || (defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 800)
+#define	__always_inline	__inline__ __attribute__((__always_inline__))
+#else
+#define	__always_inline
+#endif
+
+#if __GNUC_PREREQ__(3, 1)
+#define	__noinline	__attribute__ ((__noinline__))
+#else
+#define	__noinline
+#endif
+
+#if __GNUC_PREREQ__(3, 3)
+#define	__nonnull(x)	__attribute__((__nonnull__ x))
+#define	__nonnull_all	__attribute__((__nonnull__))
+#else
+#define	__nonnull(x)
+#define	__nonnull_all
+#endif
+
+#if __GNUC_PREREQ__(3, 4)
+#define	__fastcall	__attribute__((__fastcall__))
+#define	__result_use_check	__attribute__((__warn_unused_result__))
+#else
+#define	__fastcall
+#define	__result_use_check
+#endif
+
+#if __GNUC_PREREQ__(4, 1)
+#define	__returns_twice	__attribute__((__returns_twice__))
+#else
+#define	__returns_twice
+#endif
+
+#if __GNUC_PREREQ__(4, 6) || __has_builtin(__builtin_unreachable)
+#define	__unreachable()	__builtin_unreachable()
+#else
+#define	__unreachable()	((void)0)
+#endif
+
+/* XXX: should use `#if __STDC_VERSION__ < 199901'. */
+#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
+#define	__func__	NULL
+#endif
+
+/*
+ * GCC 2.95 provides `__restrict' as an extension to C90 to support the
+ * C99-specific `restrict' type qualifier.  We happen to use `__restrict' as
+ * a way to define the `restrict' type qualifier without disturbing older
+ * software that is unaware of C99 keywords.
+ */
+#if !(__GNUC__ == 2 && __GNUC_MINOR__ == 95)
+#if !defined(__STDC_VERSION__) || __STDC_VERSION__ < 199901
+#define	__restrict
+#else
+#define	__restrict	restrict
+#endif
+#endif
+
+/*
+ * GNU C version 2.96 adds explicit branch prediction so that
+ * the CPU back-end can hint the processor and also so that
+ * code blocks can be reordered such that the predicted path
+ * sees a more linear flow, thus improving cache behavior, etc.
+ *
+ * The following two macros provide us with a way to utilize this
+ * compiler feature.  Use __predict_true() if you expect the expression
+ * to evaluate to true, and __predict_false() if you expect the
+ * expression to evaluate to false.
+ *
+ * A few notes about usage:
+ *
+ *	* Generally, __predict_false() error condition checks (unless
+ *	  you have some _strong_ reason to do otherwise, in which case
+ *	  document it), and/or __predict_true() `no-error' condition
+ *	  checks, assuming you want to optimize for the no-error case.
+ *
+ *	* Other than that, if you don't know the likelihood of a test
+ *	  succeeding from empirical or other `hard' evidence, don't
+ *	  make predictions.
+ *
+ *	* These are meant to be used in places that are run `a lot'.
+ *	  It is wasteful to make predictions in code that is run
+ *	  seldomly (e.g. at subsystem initialization time) as the
+ *	  basic block reordering that this affects can often generate
+ *	  larger code.
+ */
+#if __GNUC_PREREQ__(2, 96)
+#define	__predict_true(exp)     __builtin_expect((exp), 1)
+#define	__predict_false(exp)    __builtin_expect((exp), 0)
+#else
+#define	__predict_true(exp)     (exp)
+#define	__predict_false(exp)    (exp)
+#endif
+
+#if __GNUC_PREREQ__(4, 0)
+#define	__null_sentinel	__attribute__((__sentinel__))
+#define	__exported	__attribute__((__visibility__("default")))
+/* Only default visibility is supported on PE/COFF targets. */
+#ifndef __CYGWIN__
+#define	__hidden	__attribute__((__visibility__("hidden")))
+#else
+#define	__hidden
+#endif
+#else
+#define	__null_sentinel
+#define	__exported
+#define	__hidden
+#endif
+
+#define __offsetof(type, field)	offsetof(type, field)
+#define	__rangeof(type, start, end) \
+	(__offsetof(type, end) - __offsetof(type, start))
+
+/*
+ * Given the pointer x to the member m of the struct s, return
+ * a pointer to the containing structure.  When using GCC, we first
+ * assign pointer x to a local variable, to check that its type is
+ * compatible with member m.
+ */
+#if __GNUC_PREREQ__(3, 1)
+#define	__containerof(x, s, m) ({					\
+	const volatile __typeof(((s *)0)->m) *__x = (x);		\
+	__DEQUALIFY(s *, (const volatile char *)__x - __offsetof(s, m));\
+})
+#else
+#define	__containerof(x, s, m)						\
+	__DEQUALIFY(s *, (const volatile char *)(x) - __offsetof(s, m))
+#endif
+
+/*
+ * Compiler-dependent macros to declare that functions take printf-like
+ * or scanf-like arguments.  They are null except for versions of gcc
+ * that are known to support the features properly (old versions of gcc-2
+ * didn't permit keeping the keywords out of the application namespace).
+ */
+#if !__GNUC_PREREQ__(2, 7) && !defined(__INTEL_COMPILER)
+#define	__printflike(fmtarg, firstvararg)
+#define	__scanflike(fmtarg, firstvararg)
+#define	__format_arg(fmtarg)
+#define	__strfmonlike(fmtarg, firstvararg)
+#define	__strftimelike(fmtarg, firstvararg)
+#else
+#define	__printflike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__printf__, fmtarg, firstvararg)))
+#define	__scanflike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__scanf__, fmtarg, firstvararg)))
+#define	__format_arg(fmtarg)	__attribute__((__format_arg__ (fmtarg)))
+#define	__strfmonlike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__strfmon__, fmtarg, firstvararg)))
+#define	__strftimelike(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__strftime__, fmtarg, firstvararg)))
+#endif
+
+/* Compiler-dependent macros that rely on FreeBSD-specific extensions. */
+#if defined(__FreeBSD_cc_version) && __FreeBSD_cc_version >= 300001 && \
+    defined(__GNUC__) && !defined(__INTEL_COMPILER)
+#define	__printf0like(fmtarg, firstvararg) \
+	    __attribute__((__format__ (__printf0__, fmtarg, firstvararg)))
+#else
+#define	__printf0like(fmtarg, firstvararg)
+#endif
+
+#if defined(__GNUC__) || defined(__INTEL_COMPILER)
+#ifndef __INTEL_COMPILER
+#define	__strong_reference(sym,aliassym)	\
+	extern __typeof (sym) aliassym __attribute__ ((__alias__ (#sym)))
+#endif
+#ifdef __ELF__
+#ifdef __STDC__
+#define	__weak_reference(sym,alias)	\
+	__asm__(".weak " #alias);	\
+	__asm__(".equ "  #alias ", " #sym)
+#define	__warn_references(sym,msg)	\
+	__asm__(".section .gnu.warning." #sym);	\
+	__asm__(".asciz \"" msg "\"");	\
+	__asm__(".previous")
+#define	__sym_compat(sym,impl,verid)	\
+	__asm__(".symver " #impl ", " #sym "@" #verid)
+#define	__sym_default(sym,impl,verid)	\
+	__asm__(".symver " #impl ", " #sym "@@" #verid)
+#else
+#define	__weak_reference(sym,alias)	\
+	__asm__(".weak alias");		\
+	__asm__(".equ alias, sym")
+#define	__warn_references(sym,msg)	\
+	__asm__(".section .gnu.warning.sym"); \
+	__asm__(".asciz \"msg\"");	\
+	__asm__(".previous")
+#define	__sym_compat(sym,impl,verid)	\
+	__asm__(".symver impl, sym@verid")
+#define	__sym_default(impl,sym,verid)	\
+	__asm__(".symver impl, sym@@verid")
+#endif	/* __STDC__ */
+#else	/* !__ELF__ */
+#ifdef __STDC__
+#define	__weak_reference(sym,alias)	\
+	__asm__(".stabs \"_" #alias "\",11,0,0,0");	\
+	__asm__(".stabs \"_" #sym "\",1,0,0,0")
+#define	__warn_references(sym,msg)	\
+	__asm__(".stabs \"" msg "\",30,0,0,0");		\
+	__asm__(".stabs \"_" #sym "\",1,0,0,0")
+#else
+#define	__weak_reference(sym,alias)	\
+	__asm__(".stabs \"_/**/alias\",11,0,0,0");	\
+	__asm__(".stabs \"_/**/sym\",1,0,0,0")
+#define	__warn_references(sym,msg)	\
+	__asm__(".stabs msg,30,0,0,0");			\
+	__asm__(".stabs \"_/**/sym\",1,0,0,0")
+#endif	/* __STDC__ */
+#endif	/* __ELF__ */
+#endif	/* __GNUC__ || __INTEL_COMPILER */
+
+#ifndef	__FBSDID
+#define	__FBSDID(s)	struct __hack
+#endif
+
+#ifndef	__RCSID
+#define	__RCSID(s)	struct __hack
+#endif
+
+#ifndef	__RCSID_SOURCE
+#define	__RCSID_SOURCE(s)	struct __hack
+#endif
+
+#ifndef	__SCCSID
+#define	__SCCSID(s)	struct __hack
+#endif
+
+#ifndef	__COPYRIGHT
+#define	__COPYRIGHT(s)	struct __hack
+#endif
+
+#ifndef	__DECONST
+#define	__DECONST(type, var)	((type)(__uintptr_t)(const void *)(var))
+#endif
+
+#ifndef	__DEVOLATILE
+#define	__DEVOLATILE(type, var)	((type)(__uintptr_t)(volatile void *)(var))
+#endif
+
+#ifndef	__DEQUALIFY
+#define	__DEQUALIFY(type, var)	((type)(__uintptr_t)(const volatile void *)(var))
+#endif
+
+/*
+ * Nullability qualifiers: currently only supported by Clang.
+ */
+#if !(defined(__clang__) && __has_feature(nullability))
+#define	_Nonnull
+#define	_Nullable
+#define	_Null_unspecified
+#define	__NULLABILITY_PRAGMA_PUSH
+#define	__NULLABILITY_PRAGMA_POP
+#else
+#define	__NULLABILITY_PRAGMA_PUSH _Pragma("clang diagnostic push")	\
+	_Pragma("clang diagnostic ignored \"-Wnullability-completeness\"")
+#define	__NULLABILITY_PRAGMA_POP _Pragma("clang diagnostic pop")
+#endif
+
+/*
+ * Type Safety Checking
+ *
+ * Clang provides additional attributes to enable checking type safety
+ * properties that cannot be enforced by the C type system. 
+ */
+
+#if __has_attribute(__argument_with_type_tag__) && \
+    __has_attribute(__type_tag_for_datatype__)
+#define	__arg_type_tag(arg_kind, arg_idx, type_tag_idx) \
+	    __attribute__((__argument_with_type_tag__(arg_kind, arg_idx, type_tag_idx)))
+#define	__datatype_type_tag(kind, type) \
+	    __attribute__((__type_tag_for_datatype__(kind, type)))
+#else
+#define	__arg_type_tag(arg_kind, arg_idx, type_tag_idx)
+#define	__datatype_type_tag(kind, type)
+#endif
+
+/*
+ * Lock annotations.
+ *
+ * Clang provides support for doing basic thread-safety tests at
+ * compile-time, by marking which locks will/should be held when
+ * entering/leaving a functions.
+ *
+ * Furthermore, it is also possible to annotate variables and structure
+ * members to enforce that they are only accessed when certain locks are
+ * held.
+ */
+
+#if __has_extension(c_thread_safety_attributes)
+#define	__lock_annotate(x)	__attribute__((x))
+#else
+#define	__lock_annotate(x)
+#endif
+
+/* Structure implements a lock. */
+/* FIXME: Use __lockable__, etc. to avoid colliding with user namespace macros,
+ * once clang is fixed: https://bugs.llvm.org/show_bug.cgi?id=34319 */
+#define	__lockable		__lock_annotate(lockable)
+
+/* Function acquires an exclusive or shared lock. */
+#define	__locks_exclusive(...) \
+	__lock_annotate(exclusive_lock_function(__VA_ARGS__))
+#define	__locks_shared(...) \
+	__lock_annotate(shared_lock_function(__VA_ARGS__))
+
+/* Function attempts to acquire an exclusive or shared lock. */
+#define	__trylocks_exclusive(...) \
+	__lock_annotate(exclusive_trylock_function(__VA_ARGS__))
+#define	__trylocks_shared(...) \
+	__lock_annotate(shared_trylock_function(__VA_ARGS__))
+
+/* Function releases a lock. */
+#define	__unlocks(...)		__lock_annotate(unlock_function(__VA_ARGS__))
+
+/* Function asserts that an exclusive or shared lock is held. */
+#define	__asserts_exclusive(...) \
+	__lock_annotate(assert_exclusive_lock(__VA_ARGS__))
+#define	__asserts_shared(...) \
+	__lock_annotate(assert_shared_lock(__VA_ARGS__))
+
+/* Function requires that an exclusive or shared lock is or is not held. */
+#define	__requires_exclusive(...) \
+	__lock_annotate(exclusive_locks_required(__VA_ARGS__))
+#define	__requires_shared(...) \
+	__lock_annotate(shared_locks_required(__VA_ARGS__))
+#define	__requires_unlocked(...) \
+	__lock_annotate(locks_excluded(__VA_ARGS__))
+
+/* Function should not be analyzed. */
+#define	__no_lock_analysis	__lock_annotate(no_thread_safety_analysis)
+
+/* Guard variables and structure members by lock. */
+#define	__guarded_by(x)		__lock_annotate(guarded_by(x))
+#define	__pt_guarded_by(x)	__lock_annotate(pt_guarded_by(x))
+
+#endif /* !_SYS_CDEFS_H_ */

src/include/sys/config.h

@@ -0,0 +1,300 @@
+#ifndef __SYS_CONFIG_H__
+#define __SYS_CONFIG_H__
+
+#include <machine/ieeefp.h>  /* floating point macros */
+#include <sys/features.h>	/* POSIX defs */
+
+#ifdef __aarch64__
+#define MALLOC_ALIGNMENT 16
+#endif
+
+/* exceptions first */
+#if defined(__H8500__) || defined(__W65__)
+#define __SMALL_BITFIELDS
+/* ???  This conditional is true for the h8500 and the w65, defining H8300
+   in those cases probably isn't the right thing to do.  */
+#define H8300 1
+#endif
+
+/* 16 bit integer machines */
+#if defined(__Z8001__) || defined(__Z8002__) || defined(__H8500__) || defined(__W65__) || defined (__mn10200__) || defined (__AVR__)
+
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX 32767
+#define UINT_MAX 65535
+#endif
+
+#if defined (__H8300__) || defined (__H8300H__) || defined(__H8300S__) || defined (__H8300SX__)
+#define __SMALL_BITFIELDS
+#define H8300 1
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#endif
+
+#if (defined(__CR16__) || defined(__CR16C__) ||defined(__CR16CP__))
+#ifndef __INT32__
+#define __SMALL_BITFIELDS      
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX 32767
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#else /* INT32 */
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX 2147483647
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#endif /* INT32 */
+
+#endif /* CR16C */
+
+#if defined (__xc16x__) || defined (__xc16xL__) || defined (__xc16xS__)
+#define __SMALL_BITFIELDS
+#endif
+
+#ifdef __W65__
+#define __SMALL_BITFIELDS
+#endif
+
+#if defined(__D10V__)
+#define __SMALL_BITFIELDS
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define _POINTER_INT short
+#endif
+
+#if defined(__mc68hc11__) || defined(__mc68hc12__) || defined(__mc68hc1x__)
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define _POINTER_INT short
+#endif
+
+#if defined(__m68k__) || defined(__mc68000__) || defined(__riscv)
+#define _READ_WRITE_RETURN_TYPE _ssize_t
+#endif
+
+#ifdef ___AM29K__
+#define _FLOAT_RET double
+#endif
+
+#ifdef __i386__
+#ifndef __unix__
+/* in other words, go32 */
+#define _FLOAT_RET double
+#endif
+#if defined(__linux__) || defined(__RDOS__)
+/* we want the reentrancy structure to be returned by a function */
+#define __DYNAMIC_REENT__
+#define HAVE_GETDATE
+#define _READ_WRITE_RETURN_TYPE _ssize_t
+#define __LARGE64_FILES 1
+/* we use some glibc header files so turn on glibc large file feature */
+#define _LARGEFILE64_SOURCE 1
+#endif
+#endif
+
+#ifdef __mn10200__
+#define __SMALL_BITFIELDS
+#endif
+
+#ifdef __AVR__
+#define __SMALL_BITFIELDS
+#define _POINTER_INT short
+#endif
+
+#if defined(__v850) && !defined(__rtems__)
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__sda__))
+#endif
+
+/* For the PowerPC eabi, force the _impure_ptr to be in .sdata */
+#if defined(__PPC__)
+#if defined(_CALL_SYSV)
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
+#endif
+#ifdef __SPE__
+#define _LONG_DOUBLE double
+#endif
+#endif
+
+/* Configure small REENT structure for Xilinx MicroBlaze platforms */
+#if defined (__MICROBLAZE__)
+#ifndef _REENT_SMALL
+#define _REENT_SMALL
+#endif
+/* Xilinx XMK uses Unix98 mutex */
+#ifdef __XMK__
+#define _UNIX98_THREAD_MUTEX_ATTRIBUTES
+#endif
+#endif
+
+#if defined(__mips__) && !defined(__rtems__)
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
+#endif
+
+#ifdef __xstormy16__
+#define __SMALL_BITFIELDS
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define MALLOC_ALIGNMENT 8
+#define _POINTER_INT short
+#define __BUFSIZ__ 16
+#define _REENT_SMALL
+#endif
+
+#if defined __MSP430__
+#ifndef _REENT_SMALL
+#define _REENT_SMALL
+#endif
+
+#define __BUFSIZ__ 256
+#define __SMALL_BITFIELDS
+
+#ifdef __MSP430X_LARGE__
+#define _POINTER_INT long
+#else
+#define _POINTER_INT int
+#endif
+#endif
+
+#ifdef __m32c__
+#define __SMALL_BITFIELDS
+#undef INT_MAX
+#undef UINT_MAX
+#define INT_MAX __INT_MAX__
+#define UINT_MAX (__INT_MAX__ * 2U + 1)
+#define MALLOC_ALIGNMENT 8
+#if defined(__r8c_cpu__) || defined(__m16c_cpu__)
+#define _POINTER_INT short
+#else
+#define _POINTER_INT long
+#endif
+#define __BUFSIZ__ 16
+#define _REENT_SMALL
+#endif /* __m32c__ */
+
+#ifdef __SPU__
+#define MALLOC_ALIGNMENT 16
+#define __CUSTOM_FILE_IO__
+#endif
+
+#if defined(__or1k__) || defined(__or1knd__)
+#define __DYNAMIC_REENT__
+#endif
+
+/* This block should be kept in sync with GCC's limits.h.  The point
+   of having these definitions here is to not include limits.h, which
+   would pollute the user namespace, while still using types of the
+   the correct widths when deciding how to define __int32_t and
+   __int64_t.  */
+#ifndef __INT_MAX__
+# ifdef INT_MAX
+#  define __INT_MAX__ INT_MAX
+# else
+#  define __INT_MAX__ 2147483647
+# endif
+#endif
+
+#ifndef __LONG_MAX__
+# ifdef LONG_MAX
+#  define __LONG_MAX__ LONG_MAX
+# else
+#  if defined (__alpha__) || (defined (__sparc__) && defined(__arch64__)) \
+      || defined (__sparcv9)
+#   define __LONG_MAX__ 9223372036854775807L
+#  else
+#   define __LONG_MAX__ 2147483647L
+#  endif /* __alpha__ || sparc64 */
+# endif
+#endif
+/* End of block that should be kept in sync with GCC's limits.h.  */
+
+#ifndef _POINTER_INT
+#define _POINTER_INT long
+#endif
+
+#ifdef __frv__
+#define __ATTRIBUTE_IMPURE_PTR__ __attribute__((__section__(".sdata")))
+#endif
+#undef __RAND_MAX
+#if __INT_MAX__ == 32767
+#define __RAND_MAX 32767
+#else
+#define __RAND_MAX 0x7fffffff
+#endif
+
+#if defined(__CYGWIN__)
+#include <cygwin/config.h>
+#endif
+
+#if defined(__rtems__)
+#define __FILENAME_MAX__ 255
+#define _READ_WRITE_RETURN_TYPE _ssize_t
+#define __DYNAMIC_REENT__
+#define _REENT_GLOBAL_ATEXIT
+#define _REENT_GLOBAL_STDIO_STREAMS
+#endif
+
+#ifndef __EXPORT
+#define __EXPORT
+#endif
+
+#ifndef __IMPORT
+#define __IMPORT
+#endif
+
+/* Define return type of read/write routines.  In POSIX, the return type
+   for read()/write() is "ssize_t" but legacy newlib code has been using
+   "int" for some time.  If not specified, "int" is defaulted.  */
+#ifndef _READ_WRITE_RETURN_TYPE
+#define _READ_WRITE_RETURN_TYPE int
+#endif
+/* Define `count' parameter of read/write routines.  In POSIX, the `count'
+   parameter is "size_t" but legacy newlib code has been using "int" for some
+   time.  If not specified, "int" is defaulted.  */
+#ifndef _READ_WRITE_BUFSIZE_TYPE
+#define _READ_WRITE_BUFSIZE_TYPE int
+#endif
+
+#ifndef __WCHAR_MAX__
+#if __INT_MAX__ == 32767 || defined (_WIN32)
+#define __WCHAR_MAX__ 0xffffu
+#endif
+#endif
+
+/* See if small reent asked for at configuration time and
+   is not chosen by the platform by default.  */
+#ifdef _WANT_REENT_SMALL
+#ifndef _REENT_SMALL
+#define _REENT_SMALL
+#endif
+#endif
+
+#ifdef _WANT_REENT_GLOBAL_STDIO_STREAMS
+#ifndef _REENT_GLOBAL_STDIO_STREAMS
+#define _REENT_GLOBAL_STDIO_STREAMS
+#endif
+#endif
+
+#ifdef _WANT_USE_LONG_TIME_T
+#ifndef _USE_LONG_TIME_T
+#define _USE_LONG_TIME_T
+#endif
+#endif
+
+/* If _MB_EXTENDED_CHARSETS_ALL is set, we want all of the extended
+   charsets.  The extended charsets add a few functions and a couple
+   of tables of a few K each. */
+#ifdef _MB_EXTENDED_CHARSETS_ALL
+#define _MB_EXTENDED_CHARSETS_ISO 1
+#define _MB_EXTENDED_CHARSETS_WINDOWS 1
+#endif
+
+#endif /* __SYS_CONFIG_H__ */

src/include/sys/features.h

@@ -0,0 +1,533 @@
+/*
+ *  Written by Joel Sherrill <joel@OARcorp.com>.
+ *
+ *  COPYRIGHT (c) 1989-2014.
+ *
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Permission to use, copy, modify, and distribute this software for any
+ *  purpose without fee is hereby granted, provided that this entire notice
+ *  is included in all copies of any software which is or includes a copy
+ *  or modification of this software.
+ *
+ *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
+ *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
+ *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _SYS_FEATURES_H
+#define _SYS_FEATURES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <_newlib_version.h>
+
+/* Macro to test version of GCC.  Returns 0 for non-GCC or too old GCC. */
+#ifndef __GNUC_PREREQ
+# if defined __GNUC__ && defined __GNUC_MINOR__
+#  define __GNUC_PREREQ(maj, min) \
+	((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
+# else
+#  define __GNUC_PREREQ(maj, min) 0
+# endif
+#endif /* __GNUC_PREREQ */
+/* Version with trailing underscores for BSD compatibility. */
+#define	__GNUC_PREREQ__(ma, mi)	__GNUC_PREREQ(ma, mi)
+
+
+/*
+ * Feature test macros control which symbols are exposed by the system
+ * headers.  Any of these must be defined before including any headers.
+ *
+ * __STRICT_ANSI__ (defined by gcc -ansi, -std=c90, -std=c99, or -std=c11)
+ *	ISO C
+ *
+ * _POSIX_SOURCE (deprecated by _POSIX_C_SOURCE=1)
+ * _POSIX_C_SOURCE >= 1
+ * 	POSIX.1-1990
+ *
+ * _POSIX_C_SOURCE >= 2
+ * 	POSIX.2-1992
+ *
+ * _POSIX_C_SOURCE >= 199309L
+ * 	POSIX.1b-1993 Real-time extensions
+ *
+ * _POSIX_C_SOURCE >= 199506L
+ * 	POSIX.1c-1995 Threads extensions
+ *
+ * _POSIX_C_SOURCE >= 200112L
+ * 	POSIX.1-2001 and C99
+ *
+ * _POSIX_C_SOURCE >= 200809L
+ * 	POSIX.1-2008
+ *
+ * _XOPEN_SOURCE
+ *	POSIX.1-1990 and XPG4
+ *
+ * _XOPEN_SOURCE_EXTENDED
+ *	SUSv1 (POSIX.2-1992 plus XPG4v2)
+ *
+ * _XOPEN_SOURCE >= 500
+ *	SUSv2 (POSIX.1c-1995 plus XSI)
+ *
+ * _XOPEN_SOURCE >= 600
+ *	SUSv3 (POSIX.1-2001 plus XSI) and C99
+ *
+ * _XOPEN_SOURCE >= 700
+ *	SUSv4 (POSIX.1-2008 plus XSI)
+ *
+ * _ISOC99_SOURCE or gcc -std=c99 or g++
+ * 	ISO C99
+ *
+ * _ISOC11_SOURCE or gcc -std=c11 or g++ -std=c++11
+ * 	ISO C11
+ *
+ * _ATFILE_SOURCE (implied by _POSIX_C_SOURCE >= 200809L)
+ *	"at" functions
+ *
+ * _LARGEFILE_SOURCE (deprecated by _XOPEN_SOURCE >= 500)
+ *	fseeko, ftello
+ *
+ * _GNU_SOURCE
+ * 	All of the above plus GNU extensions
+ *
+ * _BSD_SOURCE (deprecated by _DEFAULT_SOURCE)
+ * _SVID_SOURCE (deprecated by _DEFAULT_SOURCE)
+ * _DEFAULT_SOURCE (or none of the above)
+ * 	POSIX-1.2008 with BSD and SVr4 extensions
+ *
+ * _FORTIFY_SOURCE = 1 or 2
+ * 	Object Size Checking function wrappers
+ */
+
+#ifdef _GNU_SOURCE
+#undef _ATFILE_SOURCE
+#define	_ATFILE_SOURCE		1
+#undef	_DEFAULT_SOURCE
+#define	_DEFAULT_SOURCE		1
+#undef _ISOC99_SOURCE
+#define	_ISOC99_SOURCE		1
+#undef _ISOC11_SOURCE
+#define	_ISOC11_SOURCE		1
+#undef _POSIX_SOURCE
+#define	_POSIX_SOURCE		1
+#undef _POSIX_C_SOURCE
+#define	_POSIX_C_SOURCE		200809L
+#undef _XOPEN_SOURCE
+#define	_XOPEN_SOURCE		700
+#undef _XOPEN_SOURCE_EXTENDED
+#define	_XOPEN_SOURCE_EXTENDED	1
+#endif /* _GNU_SOURCE */
+
+#if defined(_BSD_SOURCE) || defined(_SVID_SOURCE) || \
+   (!defined(__STRICT_ANSI__) && !defined(_ANSI_SOURCE) && \
+   !defined(_ISOC99_SOURCE) && !defined(_POSIX_SOURCE) && \
+   !defined(_POSIX_C_SOURCE) && !defined(_XOPEN_SOURCE))
+#undef _DEFAULT_SOURCE
+#define	_DEFAULT_SOURCE		1
+#endif
+
+#if defined(_DEFAULT_SOURCE)
+#undef _POSIX_SOURCE
+#define	_POSIX_SOURCE		1
+#undef _POSIX_C_SOURCE
+#define	_POSIX_C_SOURCE		200809L
+#endif
+
+#if !defined(_POSIX_SOURCE) && !defined(_POSIX_C_SOURCE) && \
+  ((!defined(__STRICT_ANSI__) && !defined(_ANSI_SOURCE)) || \
+   (_XOPEN_SOURCE - 0) >= 500)
+#define	_POSIX_SOURCE		1
+#if !defined(_XOPEN_SOURCE) || (_XOPEN_SOURCE - 0) >= 700
+#define	_POSIX_C_SOURCE		200809L
+#elif (_XOPEN_SOURCE - 0) >= 600
+#define	_POSIX_C_SOURCE		200112L
+#elif (_XOPEN_SOURCE - 0) >= 500
+#define	_POSIX_C_SOURCE		199506L
+#elif (_XOPEN_SOURCE - 0) < 500
+#define	_POSIX_C_SOURCE		2
+#endif
+#endif
+
+#if defined(_POSIX_C_SOURCE) && _POSIX_C_SOURCE >= 200809
+#undef _ATFILE_SOURCE
+#define	_ATFILE_SOURCE		1
+#endif
+
+/*
+ * The following private macros are used throughout the headers to control
+ * which symbols should be exposed.  They are for internal use only, as
+ * indicated by the leading double underscore, and must never be used outside
+ * of these headers.
+ *
+ * __POSIX_VISIBLE
+ * 	any version of POSIX.1; enabled by default, or with _POSIX_SOURCE,
+ * 	any value of _POSIX_C_SOURCE, or _XOPEN_SOURCE >= 500.
+ *
+ * __POSIX_VISIBLE >= 2
+ * 	POSIX.2-1992; enabled by default, with _POSIX_C_SOURCE >= 2,
+ * 	or _XOPEN_SOURCE >= 500.
+ *
+ * __POSIX_VISIBLE >= 199309
+ * 	POSIX.1b-1993; enabled by default, with _POSIX_C_SOURCE >= 199309L,
+ * 	or _XOPEN_SOURCE >= 500.
+ *
+ * __POSIX_VISIBLE >= 199506
+ * 	POSIX.1c-1995; enabled by default, with _POSIX_C_SOURCE >= 199506L,
+ * 	or _XOPEN_SOURCE >= 500.
+ *
+ * __POSIX_VISIBLE >= 200112
+ * 	POSIX.1-2001; enabled by default, with _POSIX_C_SOURCE >= 200112L,
+ * 	or _XOPEN_SOURCE >= 600.
+ *
+ * __POSIX_VISIBLE >= 200809
+ * 	POSIX.1-2008; enabled by default, with _POSIX_C_SOURCE >= 200809L,
+ * 	or _XOPEN_SOURCE >= 700.
+ *
+ * __XSI_VISIBLE
+ *	XPG4 XSI extensions; enabled with any version of _XOPEN_SOURCE.
+ *
+ * __XSI_VISIBLE >= 4
+ *	SUSv1 XSI extensions; enabled with both _XOPEN_SOURCE and
+ * 	_XOPEN_SOURCE_EXTENDED together.
+ *
+ * __XSI_VISIBLE >= 500
+ *	SUSv2 XSI extensions; enabled with _XOPEN_SOURCE >= 500.
+ *
+ * __XSI_VISIBLE >= 600
+ *	SUSv3 XSI extensions; enabled with _XOPEN_SOURCE >= 600.
+ *
+ * __XSI_VISIBLE >= 700
+ *	SUSv4 XSI extensions; enabled with _XOPEN_SOURCE >= 700.
+ *
+ * __ISO_C_VISIBLE >= 1999
+ * 	ISO C99; enabled with gcc -std=c99 or newer (on by default since GCC 5),
+ * 	any version of C++, or with _ISOC99_SOURCE, _POSIX_C_SOURCE >= 200112L,
+ * 	or _XOPEN_SOURCE >= 600.
+ *
+ * __ISO_C_VISIBLE >= 2011
+ * 	ISO C11; enabled with gcc -std=c11 or newer (on by default since GCC 5),
+ * 	g++ -std=c++11 or newer (on by default since GCC 6), or with
+ * 	_ISOC11_SOURCE.
+ *
+ * __ATFILE_VISIBLE
+ *	"at" functions; enabled by default, with _ATFILE_SOURCE,
+ * 	_POSIX_C_SOURCE >= 200809L, or _XOPEN_SOURCE >= 700.
+ *
+ * __LARGEFILE_VISIBLE
+ *	fseeko, ftello; enabled with _LARGEFILE_SOURCE or _XOPEN_SOURCE >= 500.
+ *
+ * __BSD_VISIBLE
+ * 	BSD extensions; enabled by default, or with _BSD_SOURCE.
+ *
+ * __SVID_VISIBLE
+ * 	SVr4 extensions; enabled by default, or with _SVID_SOURCE.
+ *
+ * __MISC_VISIBLE
+ * 	Extensions found in both BSD and SVr4 (shorthand for
+ * 	(__BSD_VISIBLE || __SVID_VISIBLE)), or newlib-specific
+ * 	extensions; enabled by default.
+ *
+ * __GNU_VISIBLE
+ * 	GNU extensions; enabled with _GNU_SOURCE.
+ *
+ * __SSP_FORTIFY_LEVEL
+ * 	Object Size Checking; defined to 0 (off), 1, or 2.
+ *
+ * In all cases above, "enabled by default" means either by defining
+ * _DEFAULT_SOURCE, or by not defining any of the public feature test macros.
+ */
+
+#ifdef _ATFILE_SOURCE
+#define	__ATFILE_VISIBLE	1
+#else
+#define	__ATFILE_VISIBLE	0
+#endif
+
+#ifdef _DEFAULT_SOURCE
+#define	__BSD_VISIBLE		1
+#else
+#define	__BSD_VISIBLE		0
+#endif
+
+#ifdef _GNU_SOURCE
+#define	__GNU_VISIBLE		1
+#else
+#define	__GNU_VISIBLE		0
+#endif
+
+#if defined(_ISOC11_SOURCE) || \
+  (__STDC_VERSION__ - 0) >= 201112L || (__cplusplus - 0) >= 201103L
+#define	__ISO_C_VISIBLE		2011
+#elif defined(_ISOC99_SOURCE) || (_POSIX_C_SOURCE - 0) >= 200112L || \
+  (__STDC_VERSION__ - 0) >= 199901L || defined(__cplusplus)
+#define	__ISO_C_VISIBLE		1999
+#else
+#define	__ISO_C_VISIBLE		1990
+#endif
+
+#if defined(_LARGEFILE_SOURCE) || (_XOPEN_SOURCE - 0) >= 500
+#define	__LARGEFILE_VISIBLE	1
+#else
+#define	__LARGEFILE_VISIBLE	0
+#endif
+
+#ifdef _DEFAULT_SOURCE
+#define	__MISC_VISIBLE		1
+#else
+#define	__MISC_VISIBLE		0
+#endif
+
+#if (_POSIX_C_SOURCE - 0) >= 200809L
+#define	__POSIX_VISIBLE		200809
+#elif (_POSIX_C_SOURCE - 0) >= 200112L
+#define	__POSIX_VISIBLE		200112
+#elif (_POSIX_C_SOURCE - 0) >= 199506L
+#define	__POSIX_VISIBLE		199506
+#elif (_POSIX_C_SOURCE - 0) >= 199309L
+#define	__POSIX_VISIBLE		199309
+#elif (_POSIX_C_SOURCE - 0) >= 2 || defined(_XOPEN_SOURCE)
+#define	__POSIX_VISIBLE		199209
+#elif defined(_POSIX_SOURCE) || defined(_POSIX_C_SOURCE)
+#define	__POSIX_VISIBLE		199009
+#else
+#define	__POSIX_VISIBLE		0
+#endif
+
+#ifdef _DEFAULT_SOURCE
+#define	__SVID_VISIBLE		1
+#else
+#define	__SVID_VISIBLE		0
+#endif
+
+#if (_XOPEN_SOURCE - 0) >= 700
+#define	__XSI_VISIBLE		700
+#elif (_XOPEN_SOURCE - 0) >= 600
+#define	__XSI_VISIBLE		600
+#elif (_XOPEN_SOURCE - 0) >= 500
+#define	__XSI_VISIBLE		500
+#elif defined(_XOPEN_SOURCE) && defined(_XOPEN_SOURCE_EXTENDED)
+#define	__XSI_VISIBLE		4
+#elif defined(_XOPEN_SOURCE)
+#define	__XSI_VISIBLE		1
+#else
+#define	__XSI_VISIBLE		0
+#endif
+
+#if _FORTIFY_SOURCE > 0 && !defined(__cplusplus) && !defined(__lint__) && \
+   (__OPTIMIZE__ > 0 || defined(__clang__)) && __GNUC_PREREQ__(4, 1)
+#  if _FORTIFY_SOURCE > 1
+#    define __SSP_FORTIFY_LEVEL 2
+#  else
+#    define __SSP_FORTIFY_LEVEL 1
+#  endif
+#else
+#  define __SSP_FORTIFY_LEVEL 0
+#endif
+
+/* RTEMS adheres to POSIX -- 1003.1b with some features from annexes.  */
+
+#ifdef __rtems__
+#define _POSIX_JOB_CONTROL     		1
+#define _POSIX_SAVED_IDS       		1
+#define _POSIX_VERSION			199309L
+#define _POSIX_ASYNCHRONOUS_IO		1
+#define _POSIX_FSYNC			1
+#define _POSIX_MAPPED_FILES		1
+#define _POSIX_MEMLOCK			1
+#define _POSIX_MEMLOCK_RANGE		1
+#define _POSIX_MEMORY_PROTECTION	1
+#define _POSIX_MESSAGE_PASSING		1
+#define _POSIX_MONOTONIC_CLOCK		200112L
+#define _POSIX_CLOCK_SELECTION		200112L
+#define _POSIX_PRIORITIZED_IO		1
+#define _POSIX_PRIORITY_SCHEDULING	1
+#define _POSIX_REALTIME_SIGNALS		1
+#define _POSIX_SEMAPHORES		1
+#define _POSIX_SHARED_MEMORY_OBJECTS	1
+#define _POSIX_SYNCHRONIZED_IO		1
+#define _POSIX_TIMERS			1
+#define _POSIX_BARRIERS                 200112L
+#define _POSIX_READER_WRITER_LOCKS      200112L
+#define _POSIX_SPIN_LOCKS               200112L
+
+
+/* In P1003.1b but defined by drafts at least as early as P1003.1c/D10  */
+#define _POSIX_THREADS				1
+#define _POSIX_THREAD_ATTR_STACKADDR		1
+#define _POSIX_THREAD_ATTR_STACKSIZE		1
+#define _POSIX_THREAD_PRIORITY_SCHEDULING	1
+#define _POSIX_THREAD_PRIO_INHERIT		1
+#define _POSIX_THREAD_PRIO_PROTECT		1
+#define _POSIX_THREAD_PROCESS_SHARED		1
+#define _POSIX_THREAD_SAFE_FUNCTIONS		1
+
+/* P1003.4b/D8 defines the constants below this comment. */
+#define _POSIX_SPAWN				1
+#define _POSIX_TIMEOUTS				1
+#define _POSIX_CPUTIME				1
+#define _POSIX_THREAD_CPUTIME			1
+#define _POSIX_SPORADIC_SERVER			1
+#define _POSIX_THREAD_SPORADIC_SERVER		1
+#define _POSIX_DEVICE_CONTROL			1
+#define _POSIX_DEVCTL_DIRECTION			1
+#define _POSIX_INTERRUPT_CONTROL		1
+#define _POSIX_ADVISORY_INFO			1
+
+/* UNIX98 added some new pthread mutex attributes */
+#define _UNIX98_THREAD_MUTEX_ATTRIBUTES         1
+
+/* POSIX 1003.26-2003 defined device control method */
+#define _POSIX_26_VERSION			200312L
+
+#endif
+
+/* XMK loosely adheres to POSIX -- 1003.1 */
+#ifdef __XMK__
+#define _POSIX_THREADS				1
+#define _POSIX_THREAD_PRIORITY_SCHEDULING	1
+#endif
+
+
+#ifdef __svr4__
+# define _POSIX_JOB_CONTROL     1
+# define _POSIX_SAVED_IDS       1
+# define _POSIX_VERSION 199009L
+#endif
+
+#ifdef __CYGWIN__
+
+#if __POSIX_VISIBLE >= 200809
+#define _POSIX_VERSION				200809L
+#define _POSIX2_VERSION				200809L
+#elif __POSIX_VISIBLE >= 200112
+#define _POSIX_VERSION				200112L
+#define _POSIX2_VERSION				200112L
+#elif __POSIX_VISIBLE >= 199506
+#define _POSIX_VERSION				199506L
+#define _POSIX2_VERSION				199506L
+#elif __POSIX_VISIBLE >= 199309
+#define _POSIX_VERSION				199309L
+#define _POSIX2_VERSION				199209L
+#elif __POSIX_VISIBLE >= 199209
+#define _POSIX_VERSION				199009L
+#define _POSIX2_VERSION				199209L
+#elif __POSIX_VISIBLE
+#define _POSIX_VERSION				199009L
+#endif
+#if __XSI_VISIBLE >= 4
+#define _XOPEN_VERSION				__XSI_VISIBLE
+#endif
+
+#define _POSIX_ADVISORY_INFO			200809L
+#define _POSIX_ASYNCHRONOUS_IO			200809L
+#define _POSIX_BARRIERS				200809L
+#define _POSIX_CHOWN_RESTRICTED			     1
+#define _POSIX_CLOCK_SELECTION			200809L
+#define _POSIX_CPUTIME				200809L
+#define _POSIX_FSYNC				200809L
+#define _POSIX_IPV6				200809L
+#define _POSIX_JOB_CONTROL			     1
+#define _POSIX_MAPPED_FILES			200809L
+/* #define _POSIX_MEMLOCK			    -1 */
+#define _POSIX_MEMLOCK_RANGE			200809L
+#define _POSIX_MEMORY_PROTECTION		200809L
+#define _POSIX_MESSAGE_PASSING			200809L
+#define _POSIX_MONOTONIC_CLOCK			200809L
+#define _POSIX_NO_TRUNC				     1
+/* #define _POSIX_PRIORITIZED_IO		    -1 */
+#define _POSIX_PRIORITY_SCHEDULING		200809L
+#define _POSIX_RAW_SOCKETS			200809L
+#define _POSIX_READER_WRITER_LOCKS		200809L
+#define _POSIX_REALTIME_SIGNALS			200809L
+#define _POSIX_REGEXP				     1
+#define _POSIX_SAVED_IDS			     1
+#define _POSIX_SEMAPHORES			200809L
+#define _POSIX_SHARED_MEMORY_OBJECTS		200809L
+#define _POSIX_SHELL				     1
+#define _POSIX_SPAWN				200809L
+#define _POSIX_SPIN_LOCKS			200809L
+/* #define _POSIX_SPORADIC_SERVER		    -1 */
+#define _POSIX_SYNCHRONIZED_IO			200809L
+#define _POSIX_THREAD_ATTR_STACKADDR		200809L
+#define _POSIX_THREAD_ATTR_STACKSIZE		200809L
+#define _POSIX_THREAD_CPUTIME			200809L
+/* #define _POSIX_THREAD_PRIO_INHERIT		    -1 */
+/* #define _POSIX_THREAD_PRIO_PROTECT		    -1 */
+#define _POSIX_THREAD_PRIORITY_SCHEDULING	200809L
+#define _POSIX_THREAD_PROCESS_SHARED		200809L
+#define _POSIX_THREAD_SAFE_FUNCTIONS		200809L
+/* #define _POSIX_THREAD_SPORADIC_SERVER	    -1 */
+#define _POSIX_THREADS				200809L
+#define _POSIX_TIMEOUTS				200809L
+#define _POSIX_TIMERS				200809L
+/* #define _POSIX_TRACE				    -1 */
+/* #define _POSIX_TRACE_EVENT_FILTER		    -1 */
+/* #define _POSIX_TRACE_INHERIT			    -1 */
+/* #define _POSIX_TRACE_LOG			    -1 */
+/* #define _POSIX_TYPED_MEMORY_OBJECTS		    -1 */
+#define _POSIX_VDISABLE				   '\0'
+
+#if __POSIX_VISIBLE >= 2
+#define _POSIX2_C_VERSION			_POSIX2_VERSION
+#define _POSIX2_C_BIND				_POSIX2_VERSION
+#define _POSIX2_C_DEV				_POSIX2_VERSION
+#define _POSIX2_CHAR_TERM			_POSIX2_VERSION
+/* #define _POSIX2_FORT_DEV			    -1 */
+/* #define _POSIX2_FORT_RUN			    -1 */
+/* #define _POSIX2_LOCALEDEF			    -1 */
+/* #define _POSIX2_PBS				    -1 */
+/* #define _POSIX2_PBS_ACCOUNTING		    -1 */
+/* #define _POSIX2_PBS_CHECKPOINT		    -1 */
+/* #define _POSIX2_PBS_LOCATE			    -1 */
+/* #define _POSIX2_PBS_MESSAGE			    -1 */
+/* #define _POSIX2_PBS_TRACK			    -1 */
+#define _POSIX2_SW_DEV				_POSIX2_VERSION
+#define _POSIX2_UPE				_POSIX2_VERSION
+#endif /* __POSIX_VISIBLE >= 2 */
+
+#define _POSIX_V6_ILP32_OFF32			    -1
+#ifdef __LP64__
+#define _POSIX_V6_ILP32_OFFBIG			    -1
+#define _POSIX_V6_LP64_OFF64			     1
+#define _POSIX_V6_LPBIG_OFFBIG			     1
+#else
+#define _POSIX_V6_ILP32_OFFBIG			     1
+#define _POSIX_V6_LP64_OFF64			    -1
+#define _POSIX_V6_LPBIG_OFFBIG			    -1
+#endif
+#define _POSIX_V7_ILP32_OFF32			_POSIX_V6_ILP32_OFF32
+#define _POSIX_V7_ILP32_OFFBIG			_POSIX_V6_ILP32_OFFBIG
+#define _POSIX_V7_LP64_OFF64			_POSIX_V6_LP64_OFF64
+#define _POSIX_V7_LPBIG_OFFBIG			_POSIX_V6_LPBIG_OFFBIG
+#define _XBS5_ILP32_OFF32			_POSIX_V6_ILP32_OFF32
+#define _XBS5_ILP32_OFFBIG			_POSIX_V6_ILP32_OFFBIG
+#define _XBS5_LP64_OFF64			_POSIX_V6_LP64_OFF64
+#define _XBS5_LPBIG_OFFBIG			_POSIX_V6_LPBIG_OFFBIG
+
+#if __XSI_VISIBLE
+#define _XOPEN_CRYPT				     1
+#define _XOPEN_ENH_I18N				     1
+/* #define _XOPEN_LEGACY			    -1 */
+/* #define _XOPEN_REALTIME			    -1 */
+/* #define _XOPEN_REALTIME_THREADS		    -1 */
+#define _XOPEN_SHM				     1
+/* #define _XOPEN_STREAMS			    -1 */
+/* #define _XOPEN_UNIX				    -1 */
+#endif /* __XSI_VISIBLE */
+
+/* The value corresponds to UNICODE version 5.2, which is the current
+   state of newlib's wide char conversion functions. */
+#define __STDC_ISO_10646__ 200910L
+
+#endif /* __CYGWIN__ */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_FEATURES_H */

src/include/sys/lock.h

@@ -0,0 +1,69 @@
+#ifndef __SYS_LOCK_H__
+#define __SYS_LOCK_H__
+
+/* dummy lock routines for single-threaded aps */
+
+#include <newlib.h>
+#include <_ansi.h>
+
+#if !defined(_RETARGETABLE_LOCKING)
+
+typedef int _LOCK_T;
+typedef int _LOCK_RECURSIVE_T;
+
+#define __LOCK_INIT(class,lock) static int lock = 0;
+#define __LOCK_INIT_RECURSIVE(class,lock) static int lock = 0;
+#define __lock_init(lock) ((void) 0)
+#define __lock_init_recursive(lock) ((void) 0)
+#define __lock_close(lock) ((void) 0)
+#define __lock_close_recursive(lock) ((void) 0)
+#define __lock_acquire(lock) ((void) 0)
+#define __lock_acquire_recursive(lock) ((void) 0)
+#define __lock_try_acquire(lock) ((void) 0)
+#define __lock_try_acquire_recursive(lock) ((void) 0)
+#define __lock_release(lock) ((void) 0)
+#define __lock_release_recursive(lock) ((void) 0)
+
+#else
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct __lock;
+typedef struct __lock * _LOCK_T;
+#define _LOCK_RECURSIVE_T _LOCK_T
+
+#define __LOCK_INIT(class,lock) extern struct __lock __lock_ ## lock; \
+	class _LOCK_T lock = &__lock_ ## lock
+#define __LOCK_INIT_RECURSIVE(class,lock) __LOCK_INIT(class,lock)
+
+extern void __retarget_lock_init(_LOCK_T *lock);
+#define __lock_init(lock) __retarget_lock_init(&lock)
+extern void __retarget_lock_init_recursive(_LOCK_T *lock);
+#define __lock_init_recursive(lock) __retarget_lock_init_recursive(&lock)
+extern void __retarget_lock_close(_LOCK_T lock);
+#define __lock_close(lock) __retarget_lock_close(lock)
+extern void __retarget_lock_close_recursive(_LOCK_T lock);
+#define __lock_close_recursive(lock) __retarget_lock_close_recursive(lock)
+extern void __retarget_lock_acquire(_LOCK_T lock);
+#define __lock_acquire(lock) __retarget_lock_acquire(lock)
+extern void __retarget_lock_acquire_recursive(_LOCK_T lock);
+#define __lock_acquire_recursive(lock) __retarget_lock_acquire_recursive(lock)
+extern int __retarget_lock_try_acquire(_LOCK_T lock);
+#define __lock_try_acquire(lock) __retarget_lock_try_acquire(lock)
+extern int __retarget_lock_try_acquire_recursive(_LOCK_T lock);
+#define __lock_try_acquire_recursive(lock) \
+  __retarget_lock_try_acquire_recursive(lock)
+extern void __retarget_lock_release(_LOCK_T lock);
+#define __lock_release(lock) __retarget_lock_release(lock)
+extern void __retarget_lock_release_recursive(_LOCK_T lock);
+#define __lock_release_recursive(lock) __retarget_lock_release_recursive(lock)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !defined(_RETARGETABLE_LOCKING) */
+
+#endif /* __SYS_LOCK_H__ */

src/include/sys/reent.h

@@ -0,0 +1,842 @@
+/* This header file provides the reentrancy.  */
+
+/* WARNING: All identifiers here must begin with an underscore.  This file is
+   included by stdio.h and others and we therefore must only use identifiers
+   in the namespace allotted to us.  */
+
+#ifndef _SYS_REENT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+#define _SYS_REENT_H_
+
+#include <_ansi.h>
+#include <stddef.h>
+#include <sys/_types.h>
+
+#define _NULL 0
+
+#ifndef __Long
+#if __LONG_MAX__ == 2147483647L
+#define __Long long
+typedef unsigned __Long __ULong;
+#elif __INT_MAX__ == 2147483647
+#define __Long int
+typedef unsigned __Long __ULong;
+#endif
+#endif
+
+#if !defined( __Long)
+#include <sys/types.h>
+#endif
+
+#ifndef __Long
+#define __Long __int32_t
+typedef __uint32_t __ULong;
+#endif
+
+struct _reent;
+
+struct __locale_t;
+
+/*
+ * If _REENT_SMALL is defined, we make struct _reent as small as possible,
+ * by having nearly everything possible allocated at first use.
+ */
+
+struct _Bigint
+{
+  struct _Bigint *_next;
+  int _k, _maxwds, _sign, _wds;
+  __ULong _x[1];
+};
+
+/* needed by reentrant structure */
+struct __tm
+{
+  int   __tm_sec;
+  int   __tm_min;
+  int   __tm_hour;
+  int   __tm_mday;
+  int   __tm_mon;
+  int   __tm_year;
+  int   __tm_wday;
+  int   __tm_yday;
+  int   __tm_isdst;
+};
+
+/*
+ * atexit() support.
+ */
+
+#define	_ATEXIT_SIZE 32	/* must be at least 32 to guarantee ANSI conformance */
+
+struct _on_exit_args {
+	void *  _fnargs[_ATEXIT_SIZE];	        /* user fn args */
+	void *	_dso_handle[_ATEXIT_SIZE];
+	/* Bitmask is set if user function takes arguments.  */
+	__ULong _fntypes;           	        /* type of exit routine -
+				   Must have at least _ATEXIT_SIZE bits */
+	/* Bitmask is set if function was registered via __cxa_atexit.  */
+	__ULong _is_cxa;
+};
+
+#ifdef _REENT_SMALL
+struct _atexit {
+	struct	_atexit *_next;			/* next in list */
+	int	_ind;				/* next index in this table */
+	void	(*_fns[_ATEXIT_SIZE])(void);	/* the table itself */
+        struct _on_exit_args * _on_exit_args_ptr;
+};
+# define _ATEXIT_INIT {_NULL, 0, {_NULL}, _NULL}
+#else
+struct _atexit {
+	struct	_atexit *_next;			/* next in list */
+	int	_ind;				/* next index in this table */
+	/* Some entries may already have been called, and will be NULL.  */
+	void	(*_fns[_ATEXIT_SIZE])(void);	/* the table itself */
+        struct _on_exit_args _on_exit_args;
+};
+# define _ATEXIT_INIT {_NULL, 0, {_NULL}, {{_NULL}, {_NULL}, 0, 0}}
+#endif
+
+#ifdef _REENT_GLOBAL_ATEXIT
+# define _REENT_INIT_ATEXIT
+#else
+# define _REENT_INIT_ATEXIT \
+  _NULL, _ATEXIT_INIT,
+#endif
+
+/*
+ * Stdio buffers.
+ *
+ * This and __FILE are defined here because we need them for struct _reent,
+ * but we don't want stdio.h included when stdlib.h is.
+ */
+
+struct __sbuf {
+	unsigned char *_base;
+	int	_size;
+};
+
+/*
+ * Stdio state variables.
+ *
+ * The following always hold:
+ *
+ *	if (_flags&(__SLBF|__SWR)) == (__SLBF|__SWR),
+ *		_lbfsize is -_bf._size, else _lbfsize is 0
+ *	if _flags&__SRD, _w is 0
+ *	if _flags&__SWR, _r is 0
+ *
+ * This ensures that the getc and putc macros (or inline functions) never
+ * try to write or read from a file that is in `read' or `write' mode.
+ * (Moreover, they can, and do, automatically switch from read mode to
+ * write mode, and back, on "r+" and "w+" files.)
+ *
+ * _lbfsize is used only to make the inline line-buffered output stream
+ * code as compact as possible.
+ *
+ * _ub, _up, and _ur are used when ungetc() pushes back more characters
+ * than fit in the current _bf, or when ungetc() pushes back a character
+ * that does not match the previous one in _bf.  When this happens,
+ * _ub._base becomes non-nil (i.e., a stream has ungetc() data iff
+ * _ub._base!=NULL) and _up and _ur save the current values of _p and _r.
+ */
+
+#if defined(_REENT_SMALL) && !defined(_REENT_GLOBAL_STDIO_STREAMS)
+/*
+ * struct __sFILE_fake is the start of a struct __sFILE, with only the
+ * minimal fields allocated.  In __sinit() we really allocate the 3
+ * standard streams, etc., and point away from this fake.
+ */
+struct __sFILE_fake {
+  unsigned char *_p;	/* current position in (some) buffer */
+  int	_r;		/* read space left for getc() */
+  int	_w;		/* write space left for putc() */
+  short	_flags;		/* flags, below; this FILE is free if 0 */
+  short	_file;		/* fileno, if Unix descriptor, else -1 */
+  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
+  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
+
+  struct _reent *_data;
+};
+
+/* Following is needed both in libc/stdio and libc/stdlib so we put it
+ * here instead of libc/stdio/local.h where it was previously. */
+
+extern void   __sinit (struct _reent *);
+
+# define _REENT_SMALL_CHECK_INIT(ptr)		\
+  do						\
+    {						\
+      if ((ptr) && !(ptr)->__sdidinit)		\
+	__sinit (ptr);				\
+    }						\
+  while (0)
+#else /* _REENT_SMALL && !_REENT_GLOBAL_STDIO_STREAMS */
+# define _REENT_SMALL_CHECK_INIT(ptr) /* nothing */
+#endif /* _REENT_SMALL && !_REENT_GLOBAL_STDIO_STREAMS */
+
+struct __sFILE {
+  unsigned char *_p;	/* current position in (some) buffer */
+  int	_r;		/* read space left for getc() */
+  int	_w;		/* write space left for putc() */
+  short	_flags;		/* flags, below; this FILE is free if 0 */
+  short	_file;		/* fileno, if Unix descriptor, else -1 */
+  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
+  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
+
+#ifdef _REENT_SMALL
+  struct _reent *_data;
+#endif
+
+  /* operations */
+  void *	_cookie;	/* cookie passed to io functions */
+
+  _READ_WRITE_RETURN_TYPE (*_read) (struct _reent *, void *,
+					   char *, _READ_WRITE_BUFSIZE_TYPE);
+  _READ_WRITE_RETURN_TYPE (*_write) (struct _reent *, void *,
+					    const char *,
+					    _READ_WRITE_BUFSIZE_TYPE);
+  _fpos_t (*_seek) (struct _reent *, void *, _fpos_t, int);
+  int (*_close) (struct _reent *, void *);
+
+  /* separate buffer for long sequences of ungetc() */
+  struct __sbuf _ub;	/* ungetc buffer */
+  unsigned char *_up;	/* saved _p when _p is doing ungetc data */
+  int	_ur;		/* saved _r when _r is counting ungetc data */
+
+  /* tricks to meet minimum requirements even when malloc() fails */
+  unsigned char _ubuf[3];	/* guarantee an ungetc() buffer */
+  unsigned char _nbuf[1];	/* guarantee a getc() buffer */
+
+  /* separate buffer for fgetline() when line crosses buffer boundary */
+  struct __sbuf _lb;	/* buffer for fgetline() */
+
+  /* Unix stdio files get aligned to block boundaries on fseek() */
+  int	_blksize;	/* stat.st_blksize (may be != _bf._size) */
+  _off_t _offset;	/* current lseek offset */
+
+#ifndef _REENT_SMALL
+  struct _reent *_data;	/* Here for binary compatibility? Remove? */
+#endif
+
+#ifndef __SINGLE_THREAD__
+  _flock_t _lock;	/* for thread-safety locking */
+#endif
+  _mbstate_t _mbstate;	/* for wide char stdio functions. */
+  int   _flags2;        /* for future use */
+};
+
+#ifdef __CUSTOM_FILE_IO__
+
+/* Get custom _FILE definition.  */
+#include <sys/custom_file.h>
+
+#else /* !__CUSTOM_FILE_IO__ */
+#ifdef __LARGE64_FILES
+struct __sFILE64 {
+  unsigned char *_p;	/* current position in (some) buffer */
+  int	_r;		/* read space left for getc() */
+  int	_w;		/* write space left for putc() */
+  short	_flags;		/* flags, below; this FILE is free if 0 */
+  short	_file;		/* fileno, if Unix descriptor, else -1 */
+  struct __sbuf _bf;	/* the buffer (at least 1 byte, if !NULL) */
+  int	_lbfsize;	/* 0 or -_bf._size, for inline putc */
+
+  struct _reent *_data;
+
+  /* operations */
+  void *	_cookie;	/* cookie passed to io functions */
+
+  _READ_WRITE_RETURN_TYPE (*_read) (struct _reent *, void *,
+					   char *, _READ_WRITE_BUFSIZE_TYPE);
+  _READ_WRITE_RETURN_TYPE (*_write) (struct _reent *, void *,
+					    const char *,
+					    _READ_WRITE_BUFSIZE_TYPE);
+  _fpos_t (*_seek) (struct _reent *, void *, _fpos_t, int);
+  int (*_close) (struct _reent *, void *);
+
+  /* separate buffer for long sequences of ungetc() */
+  struct __sbuf _ub;	/* ungetc buffer */
+  unsigned char *_up;	/* saved _p when _p is doing ungetc data */
+  int	_ur;		/* saved _r when _r is counting ungetc data */
+
+  /* tricks to meet minimum requirements even when malloc() fails */
+  unsigned char _ubuf[3];	/* guarantee an ungetc() buffer */
+  unsigned char _nbuf[1];	/* guarantee a getc() buffer */
+
+  /* separate buffer for fgetline() when line crosses buffer boundary */
+  struct __sbuf _lb;	/* buffer for fgetline() */
+
+  /* Unix stdio files get aligned to block boundaries on fseek() */
+  int	_blksize;	/* stat.st_blksize (may be != _bf._size) */
+  int   _flags2;        /* for future use */
+
+  _off64_t _offset;     /* current lseek offset */
+  _fpos64_t (*_seek64) (struct _reent *, void *, _fpos64_t, int);
+
+#ifndef __SINGLE_THREAD__
+  _flock_t _lock;	/* for thread-safety locking */
+#endif
+  _mbstate_t _mbstate;	/* for wide char stdio functions. */
+};
+typedef struct __sFILE64 __FILE;
+#else
+typedef struct __sFILE   __FILE;
+#endif /* __LARGE64_FILES */
+#endif /* !__CUSTOM_FILE_IO__ */
+
+struct _glue
+{
+  struct _glue *_next;
+  int _niobs;
+  __FILE *_iobs;
+};
+
+/*
+ * rand48 family support
+ *
+ * Copyright (c) 1993 Martin Birgmeier
+ * All rights reserved.
+ *
+ * You may redistribute unmodified or modified versions of this source
+ * code provided that the above copyright notice and this and the
+ * following conditions are retained.
+ *
+ * This software is provided ``as is'', and comes with no warranties
+ * of any kind. I shall in no event be liable for anything that happens
+ * to anyone/anything when using this software.
+ */
+#define        _RAND48_SEED_0  (0x330e)
+#define        _RAND48_SEED_1  (0xabcd)
+#define        _RAND48_SEED_2  (0x1234)
+#define        _RAND48_MULT_0  (0xe66d)
+#define        _RAND48_MULT_1  (0xdeec)
+#define        _RAND48_MULT_2  (0x0005)
+#define        _RAND48_ADD     (0x000b)
+struct _rand48 {
+  unsigned short _seed[3];
+  unsigned short _mult[3];
+  unsigned short _add;
+#ifdef _REENT_SMALL
+  /* Put this in here as well, for good luck.  */
+  __extension__ unsigned long long _rand_next;
+#endif
+};
+
+/* How big the some arrays are.  */
+#define _REENT_EMERGENCY_SIZE 25
+#define _REENT_ASCTIME_SIZE 26
+#define _REENT_SIGNAL_SIZE 24
+
+/*
+ * struct _reent
+ *
+ * This structure contains *all* globals needed by the library.
+ * It's raison d'etre is to facilitate threads by making all library routines
+ * reentrant.  IE: All state information is contained here.
+ */
+
+#ifdef _REENT_SMALL
+
+struct _mprec
+{
+  /* used by mprec routines */
+  struct _Bigint *_result;
+  int _result_k;
+  struct _Bigint *_p5s;
+  struct _Bigint **_freelist;
+};
+
+
+struct _misc_reent
+{
+  /* miscellaneous reentrant data */
+  char *_strtok_last;
+  _mbstate_t _mblen_state;
+  _mbstate_t _wctomb_state;
+  _mbstate_t _mbtowc_state;
+  char _l64a_buf[8];
+  int _getdate_err;
+  _mbstate_t _mbrlen_state;
+  _mbstate_t _mbrtowc_state;
+  _mbstate_t _mbsrtowcs_state;
+  _mbstate_t _wcrtomb_state;
+  _mbstate_t _wcsrtombs_state;
+};
+
+/* This version of _reent is laid out with "int"s in pairs, to help
+ * ports with 16-bit int's but 32-bit pointers, align nicely.  */
+struct _reent
+{
+  /* As an exception to the above put _errno first for binary
+     compatibility with non _REENT_SMALL targets.  */
+  int _errno;			/* local copy of errno */
+
+  /* FILE is a big struct and may change over time.  To try to achieve binary
+     compatibility with future versions, put stdin,stdout,stderr here.
+     These are pointers into member __sf defined below.  */
+  __FILE *_stdin, *_stdout, *_stderr;	/* XXX */
+
+  int  _inc;			/* used by tmpnam */
+
+  char *_emergency;
+
+  int __sdidinit;		/* 1 means stdio has been init'd */
+
+  int _unspecified_locale_info;	/* unused, reserved for locale stuff */
+  struct __locale_t *_locale;/* per-thread locale */
+
+  struct _mprec *_mp;
+
+  void (*__cleanup) (struct _reent *);
+
+  int _gamma_signgam;
+
+  /* used by some fp conversion routines */
+  int _cvtlen;			/* should be size_t */
+  char *_cvtbuf;
+
+  struct _rand48 *_r48;
+  struct __tm *_localtime_buf;
+  char *_asctime_buf;
+
+  /* signal info */
+  void (**(_sig_func))(int);
+
+# ifndef _REENT_GLOBAL_ATEXIT
+  /* atexit stuff */
+  struct _atexit *_atexit;
+  struct _atexit _atexit0;
+# endif
+
+  struct _glue __sglue;			/* root of glue chain */
+  __FILE *__sf;			        /* file descriptors */
+  struct _misc_reent *_misc;            /* strtok, multibyte states */
+  char *_signal_buf;                    /* strsignal */
+};
+
+#ifdef _REENT_GLOBAL_STDIO_STREAMS
+extern __FILE __sf[3];
+
+# define _REENT_INIT(var) \
+  { 0, \
+    &__sf[0], \
+    &__sf[1], \
+    &__sf[2], \
+    0,   \
+    _NULL, \
+    0, \
+    0, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    0, \
+    0, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _REENT_INIT_ATEXIT \
+    {_NULL, 0, _NULL}, \
+    _NULL, \
+    _NULL, \
+    _NULL \
+  }
+
+#define _REENT_INIT_PTR_ZEROED(var) \
+  { (var)->_stdin = &__sf[0]; \
+    (var)->_stdout = &__sf[1]; \
+    (var)->_stderr = &__sf[2]; \
+  }
+
+#else /* _REENT_GLOBAL_STDIO_STREAMS */
+
+extern const struct __sFILE_fake __sf_fake_stdin;
+extern const struct __sFILE_fake __sf_fake_stdout;
+extern const struct __sFILE_fake __sf_fake_stderr;
+
+# define _REENT_INIT(var) \
+  { 0, \
+    (__FILE *)&__sf_fake_stdin, \
+    (__FILE *)&__sf_fake_stdout, \
+    (__FILE *)&__sf_fake_stderr, \
+    0, \
+    _NULL, \
+    0, \
+    0, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    0, \
+    0, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _NULL, \
+    _REENT_INIT_ATEXIT \
+    {_NULL, 0, _NULL}, \
+    _NULL, \
+    _NULL, \
+    _NULL \
+  }
+
+#define _REENT_INIT_PTR_ZEROED(var) \
+  { (var)->_stdin = (__FILE *)&__sf_fake_stdin; \
+    (var)->_stdout = (__FILE *)&__sf_fake_stdout; \
+    (var)->_stderr = (__FILE *)&__sf_fake_stderr; \
+  }
+
+#endif /* _REENT_GLOBAL_STDIO_STREAMS */
+
+/* Only add assert() calls if we are specified to debug.  */
+#ifdef _REENT_CHECK_DEBUG
+#include <assert.h>
+#define __reent_assert(x) assert(x)
+#else
+#define __reent_assert(x) ((void)0)
+#endif
+
+#ifdef __CUSTOM_FILE_IO__
+#error Custom FILE I/O and _REENT_SMALL not currently supported.
+#endif
+
+/* Generic _REENT check macro.  */
+#define _REENT_CHECK(var, what, type, size, init) do { \
+  struct _reent *_r = (var); \
+  if (_r->what == NULL) { \
+    _r->what = (type)malloc(size); \
+    __reent_assert(_r->what); \
+    init; \
+  } \
+} while (0)
+
+#define _REENT_CHECK_TM(var) \
+  _REENT_CHECK(var, _localtime_buf, struct __tm *, sizeof *((var)->_localtime_buf), \
+    /* nothing */)
+
+#define _REENT_CHECK_ASCTIME_BUF(var) \
+  _REENT_CHECK(var, _asctime_buf, char *, _REENT_ASCTIME_SIZE, \
+    memset((var)->_asctime_buf, 0, _REENT_ASCTIME_SIZE))
+
+/* Handle the dynamically allocated rand48 structure. */
+#define _REENT_INIT_RAND48(var) do { \
+  struct _reent *_r = (var); \
+  _r->_r48->_seed[0] = _RAND48_SEED_0; \
+  _r->_r48->_seed[1] = _RAND48_SEED_1; \
+  _r->_r48->_seed[2] = _RAND48_SEED_2; \
+  _r->_r48->_mult[0] = _RAND48_MULT_0; \
+  _r->_r48->_mult[1] = _RAND48_MULT_1; \
+  _r->_r48->_mult[2] = _RAND48_MULT_2; \
+  _r->_r48->_add = _RAND48_ADD; \
+  _r->_r48->_rand_next = 1; \
+} while (0)
+#define _REENT_CHECK_RAND48(var) \
+  _REENT_CHECK(var, _r48, struct _rand48 *, sizeof *((var)->_r48), _REENT_INIT_RAND48((var)))
+
+#define _REENT_INIT_MP(var) do { \
+  struct _reent *_r = (var); \
+  _r->_mp->_result_k = 0; \
+  _r->_mp->_result = _r->_mp->_p5s = _NULL; \
+  _r->_mp->_freelist = _NULL; \
+} while (0)
+#define _REENT_CHECK_MP(var) \
+  _REENT_CHECK(var, _mp, struct _mprec *, sizeof *((var)->_mp), _REENT_INIT_MP(var))
+
+#define _REENT_CHECK_EMERGENCY(var) \
+  _REENT_CHECK(var, _emergency, char *, _REENT_EMERGENCY_SIZE, /* nothing */)
+
+#define _REENT_INIT_MISC(var) do { \
+  struct _reent *_r = (var); \
+  _r->_misc->_strtok_last = _NULL; \
+  _r->_misc->_mblen_state.__count = 0; \
+  _r->_misc->_mblen_state.__value.__wch = 0; \
+  _r->_misc->_wctomb_state.__count = 0; \
+  _r->_misc->_wctomb_state.__value.__wch = 0; \
+  _r->_misc->_mbtowc_state.__count = 0; \
+  _r->_misc->_mbtowc_state.__value.__wch = 0; \
+  _r->_misc->_mbrlen_state.__count = 0; \
+  _r->_misc->_mbrlen_state.__value.__wch = 0; \
+  _r->_misc->_mbrtowc_state.__count = 0; \
+  _r->_misc->_mbrtowc_state.__value.__wch = 0; \
+  _r->_misc->_mbsrtowcs_state.__count = 0; \
+  _r->_misc->_mbsrtowcs_state.__value.__wch = 0; \
+  _r->_misc->_wcrtomb_state.__count = 0; \
+  _r->_misc->_wcrtomb_state.__value.__wch = 0; \
+  _r->_misc->_wcsrtombs_state.__count = 0; \
+  _r->_misc->_wcsrtombs_state.__value.__wch = 0; \
+  _r->_misc->_l64a_buf[0] = '\0'; \
+  _r->_misc->_getdate_err = 0; \
+} while (0)
+#define _REENT_CHECK_MISC(var) \
+  _REENT_CHECK(var, _misc, struct _misc_reent *, sizeof *((var)->_misc), _REENT_INIT_MISC(var))
+
+#define _REENT_CHECK_SIGNAL_BUF(var) \
+  _REENT_CHECK(var, _signal_buf, char *, _REENT_SIGNAL_SIZE, /* nothing */)
+
+#define _REENT_SIGNGAM(ptr)	((ptr)->_gamma_signgam)
+#define _REENT_RAND_NEXT(ptr)	((ptr)->_r48->_rand_next)
+#define _REENT_RAND48_SEED(ptr)	((ptr)->_r48->_seed)
+#define _REENT_RAND48_MULT(ptr)	((ptr)->_r48->_mult)
+#define _REENT_RAND48_ADD(ptr)	((ptr)->_r48->_add)
+#define _REENT_MP_RESULT(ptr)	((ptr)->_mp->_result)
+#define _REENT_MP_RESULT_K(ptr)	((ptr)->_mp->_result_k)
+#define _REENT_MP_P5S(ptr)	((ptr)->_mp->_p5s)
+#define _REENT_MP_FREELIST(ptr)	((ptr)->_mp->_freelist)
+#define _REENT_ASCTIME_BUF(ptr)	((ptr)->_asctime_buf)
+#define _REENT_TM(ptr)		((ptr)->_localtime_buf)
+#define _REENT_EMERGENCY(ptr)	((ptr)->_emergency)
+#define _REENT_STRTOK_LAST(ptr)	((ptr)->_misc->_strtok_last)
+#define _REENT_MBLEN_STATE(ptr)	((ptr)->_misc->_mblen_state)
+#define _REENT_MBTOWC_STATE(ptr)((ptr)->_misc->_mbtowc_state)
+#define _REENT_WCTOMB_STATE(ptr)((ptr)->_misc->_wctomb_state)
+#define _REENT_MBRLEN_STATE(ptr) ((ptr)->_misc->_mbrlen_state)
+#define _REENT_MBRTOWC_STATE(ptr) ((ptr)->_misc->_mbrtowc_state)
+#define _REENT_MBSRTOWCS_STATE(ptr) ((ptr)->_misc->_mbsrtowcs_state)
+#define _REENT_WCRTOMB_STATE(ptr) ((ptr)->_misc->_wcrtomb_state)
+#define _REENT_WCSRTOMBS_STATE(ptr) ((ptr)->_misc->_wcsrtombs_state)
+#define _REENT_L64A_BUF(ptr)    ((ptr)->_misc->_l64a_buf)
+#define _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_misc->_getdate_err))
+#define _REENT_SIGNAL_BUF(ptr)  ((ptr)->_signal_buf)
+
+#else /* !_REENT_SMALL */
+
+struct _reent
+{
+  int _errno;			/* local copy of errno */
+
+  /* FILE is a big struct and may change over time.  To try to achieve binary
+     compatibility with future versions, put stdin,stdout,stderr here.
+     These are pointers into member __sf defined below.  */
+  __FILE *_stdin, *_stdout, *_stderr;
+
+  int  _inc;			/* used by tmpnam */
+  char _emergency[_REENT_EMERGENCY_SIZE];
+
+  /* TODO */
+  int _unspecified_locale_info;	/* unused, reserved for locale stuff */
+  struct __locale_t *_locale;/* per-thread locale */
+
+  int __sdidinit;		/* 1 means stdio has been init'd */
+
+  void (*__cleanup) (struct _reent *);
+
+  /* used by mprec routines */
+  struct _Bigint *_result;
+  int _result_k;
+  struct _Bigint *_p5s;
+  struct _Bigint **_freelist;
+
+  /* used by some fp conversion routines */
+  int _cvtlen;			/* should be size_t */
+  char *_cvtbuf;
+
+  union
+    {
+      struct
+        {
+          unsigned int _unused_rand;
+          char * _strtok_last;
+          char _asctime_buf[_REENT_ASCTIME_SIZE];
+          struct __tm _localtime_buf;
+          int _gamma_signgam;
+          __extension__ unsigned long long _rand_next;
+          struct _rand48 _r48;
+          _mbstate_t _mblen_state;
+          _mbstate_t _mbtowc_state;
+          _mbstate_t _wctomb_state;
+          char _l64a_buf[8];
+          char _signal_buf[_REENT_SIGNAL_SIZE];
+          int _getdate_err;
+          _mbstate_t _mbrlen_state;
+          _mbstate_t _mbrtowc_state;
+          _mbstate_t _mbsrtowcs_state;
+          _mbstate_t _wcrtomb_state;
+          _mbstate_t _wcsrtombs_state;
+	  int _h_errno;
+        } _reent;
+  /* Two next two fields were once used by malloc.  They are no longer
+     used. They are used to preserve the space used before so as to
+     allow addition of new reent fields and keep binary compatibility.   */
+      struct
+        {
+#define _N_LISTS 30
+          unsigned char * _nextf[_N_LISTS];
+          unsigned int _nmalloc[_N_LISTS];
+        } _unused;
+    } _new;
+
+# ifndef _REENT_GLOBAL_ATEXIT
+  /* atexit stuff */
+  struct _atexit *_atexit;	/* points to head of LIFO stack */
+  struct _atexit _atexit0;	/* one guaranteed table, required by ANSI */
+# endif
+
+  /* signal info */
+  void (**(_sig_func))(int);
+
+  /* These are here last so that __FILE can grow without changing the offsets
+     of the above members (on the off chance that future binary compatibility
+     would be broken otherwise).  */
+  struct _glue __sglue;		/* root of glue chain */
+# ifndef _REENT_GLOBAL_STDIO_STREAMS
+  __FILE __sf[3];  		/* first three file descriptors */
+# endif
+};
+
+#ifdef _REENT_GLOBAL_STDIO_STREAMS
+extern __FILE __sf[3];
+#define _REENT_STDIO_STREAM(var, index) &__sf[index]
+#else
+#define _REENT_STDIO_STREAM(var, index) &(var)->__sf[index]
+#endif
+
+#define _REENT_INIT(var) \
+  { 0, \
+    _REENT_STDIO_STREAM(&(var), 0), \
+    _REENT_STDIO_STREAM(&(var), 1), \
+    _REENT_STDIO_STREAM(&(var), 2), \
+    0, \
+    "", \
+    0, \
+    _NULL, \
+    0, \
+    _NULL, \
+    _NULL, \
+    0, \
+    _NULL, \
+    _NULL, \
+    0, \
+    _NULL, \
+    { \
+      { \
+        0, \
+        _NULL, \
+        "", \
+        {0, 0, 0, 0, 0, 0, 0, 0, 0}, \
+        0, \
+        1, \
+        { \
+          {_RAND48_SEED_0, _RAND48_SEED_1, _RAND48_SEED_2}, \
+          {_RAND48_MULT_0, _RAND48_MULT_1, _RAND48_MULT_2}, \
+          _RAND48_ADD \
+        }, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}}, \
+        "", \
+        "", \
+        0, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}}, \
+        {0, {0}} \
+      } \
+    }, \
+    _REENT_INIT_ATEXIT \
+    _NULL, \
+    {_NULL, 0, _NULL} \
+  }
+
+#define _REENT_INIT_PTR_ZEROED(var) \
+  { (var)->_stdin = _REENT_STDIO_STREAM(var, 0); \
+    (var)->_stdout = _REENT_STDIO_STREAM(var, 1); \
+    (var)->_stderr = _REENT_STDIO_STREAM(var, 2); \
+    (var)->_new._reent._rand_next = 1; \
+    (var)->_new._reent._r48._seed[0] = _RAND48_SEED_0; \
+    (var)->_new._reent._r48._seed[1] = _RAND48_SEED_1; \
+    (var)->_new._reent._r48._seed[2] = _RAND48_SEED_2; \
+    (var)->_new._reent._r48._mult[0] = _RAND48_MULT_0; \
+    (var)->_new._reent._r48._mult[1] = _RAND48_MULT_1; \
+    (var)->_new._reent._r48._mult[2] = _RAND48_MULT_2; \
+    (var)->_new._reent._r48._add = _RAND48_ADD; \
+  }
+
+#define _REENT_CHECK_RAND48(ptr)	/* nothing */
+#define _REENT_CHECK_MP(ptr)		/* nothing */
+#define _REENT_CHECK_TM(ptr)		/* nothing */
+#define _REENT_CHECK_ASCTIME_BUF(ptr)	/* nothing */
+#define _REENT_CHECK_EMERGENCY(ptr)	/* nothing */
+#define _REENT_CHECK_MISC(ptr)	        /* nothing */
+#define _REENT_CHECK_SIGNAL_BUF(ptr)	/* nothing */
+
+#define _REENT_SIGNGAM(ptr)	((ptr)->_new._reent._gamma_signgam)
+#define _REENT_RAND_NEXT(ptr)	((ptr)->_new._reent._rand_next)
+#define _REENT_RAND48_SEED(ptr)	((ptr)->_new._reent._r48._seed)
+#define _REENT_RAND48_MULT(ptr)	((ptr)->_new._reent._r48._mult)
+#define _REENT_RAND48_ADD(ptr)	((ptr)->_new._reent._r48._add)
+#define _REENT_MP_RESULT(ptr)	((ptr)->_result)
+#define _REENT_MP_RESULT_K(ptr)	((ptr)->_result_k)
+#define _REENT_MP_P5S(ptr)	((ptr)->_p5s)
+#define _REENT_MP_FREELIST(ptr)	((ptr)->_freelist)
+#define _REENT_ASCTIME_BUF(ptr)	((ptr)->_new._reent._asctime_buf)
+#define _REENT_TM(ptr)		(&(ptr)->_new._reent._localtime_buf)
+#define _REENT_EMERGENCY(ptr)	((ptr)->_emergency)
+#define _REENT_STRTOK_LAST(ptr)	((ptr)->_new._reent._strtok_last)
+#define _REENT_MBLEN_STATE(ptr)	((ptr)->_new._reent._mblen_state)
+#define _REENT_MBTOWC_STATE(ptr)((ptr)->_new._reent._mbtowc_state)
+#define _REENT_WCTOMB_STATE(ptr)((ptr)->_new._reent._wctomb_state)
+#define _REENT_MBRLEN_STATE(ptr)((ptr)->_new._reent._mbrlen_state)
+#define _REENT_MBRTOWC_STATE(ptr)((ptr)->_new._reent._mbrtowc_state)
+#define _REENT_MBSRTOWCS_STATE(ptr)((ptr)->_new._reent._mbsrtowcs_state)
+#define _REENT_WCRTOMB_STATE(ptr)((ptr)->_new._reent._wcrtomb_state)
+#define _REENT_WCSRTOMBS_STATE(ptr)((ptr)->_new._reent._wcsrtombs_state)
+#define _REENT_L64A_BUF(ptr)    ((ptr)->_new._reent._l64a_buf)
+#define _REENT_SIGNAL_BUF(ptr)  ((ptr)->_new._reent._signal_buf)
+#define _REENT_GETDATE_ERR_P(ptr) (&((ptr)->_new._reent._getdate_err))
+
+#endif /* !_REENT_SMALL */
+
+#define _REENT_INIT_PTR(var) \
+  { memset((var), 0, sizeof(*(var))); \
+    _REENT_INIT_PTR_ZEROED(var); \
+  }
+
+/* This value is used in stdlib/misc.c.  reent/reent.c has to know it
+   as well to make sure the freelist is correctly free'd.  Therefore
+   we define it here, rather than in stdlib/misc.c, as before. */
+#define _Kmax (sizeof (size_t) << 3)
+
+/*
+ * All references to struct _reent are via this pointer.
+ * Internally, newlib routines that need to reference it should use _REENT.
+ */
+
+#ifndef __ATTRIBUTE_IMPURE_PTR__
+#define __ATTRIBUTE_IMPURE_PTR__
+#endif
+
+extern struct _reent *_impure_ptr __ATTRIBUTE_IMPURE_PTR__;
+extern struct _reent *const _global_impure_ptr __ATTRIBUTE_IMPURE_PTR__;
+
+void _reclaim_reent (struct _reent *);
+
+/* #define _REENT_ONLY define this to get only reentrant routines */
+
+#if defined(__DYNAMIC_REENT__) && !defined(__SINGLE_THREAD__)
+#ifndef __getreent
+  struct _reent * __getreent (void);
+#endif
+# define _REENT (__getreent())
+#else /* __SINGLE_THREAD__ || !__DYNAMIC_REENT__ */
+# define _REENT _impure_ptr
+#endif /* __SINGLE_THREAD__ || !__DYNAMIC_REENT__ */
+
+#define _GLOBAL_REENT _global_impure_ptr
+
+#ifdef _REENT_GLOBAL_ATEXIT
+extern struct _atexit *_global_atexit; /* points to head of LIFO stack */
+# define _GLOBAL_ATEXIT _global_atexit
+#else
+# define _GLOBAL_ATEXIT (_GLOBAL_REENT->_atexit)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _SYS_REENT_H_ */

src/include/sys/sched.h

@@ -0,0 +1,69 @@
+/*
+ *  Written by Joel Sherrill <joel@OARcorp.com>.
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  Permission to use, copy, modify, and distribute this software for any
+ *  purpose without fee is hereby granted, provided that this entire notice
+ *  is included in all copies of any software which is or includes a copy
+ *  or modification of this software.
+ *
+ *  THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED
+ *  WARRANTY.  IN PARTICULAR,  THE AUTHOR MAKES NO REPRESENTATION
+ *  OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS
+ *  SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ *  $Id$
+ */
+
+
+#ifndef _SYS_SCHED_H_
+#define _SYS_SCHED_H_
+
+#include <sys/_timespec.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Scheduling Policies */
+/* Open Group Specifications Issue 6 */
+#if defined(__CYGWIN__)
+#define SCHED_OTHER    3
+#else
+#define SCHED_OTHER    0
+#endif
+
+#define SCHED_FIFO     1
+#define SCHED_RR       2
+
+#if defined(_POSIX_SPORADIC_SERVER)
+#define SCHED_SPORADIC 4
+#endif
+
+/* Scheduling Parameters */
+/* Open Group Specifications Issue 6 */
+
+struct sched_param {
+  int sched_priority;           /* Process execution scheduling priority */
+
+#if defined(_POSIX_SPORADIC_SERVER) || defined(_POSIX_THREAD_SPORADIC_SERVER)
+  int sched_ss_low_priority;    /* Low scheduling priority for sporadic */
+                                /*   server */
+  struct timespec sched_ss_repl_period;
+                                /* Replenishment period for sporadic server */
+  struct timespec sched_ss_init_budget;
+                               /* Initial budget for sporadic server */
+  int sched_ss_max_repl;       /* Maximum pending replenishments for */
+                               /* sporadic server */
+#endif
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
+

src/include/sys/select.h

@@ -0,0 +1,76 @@
+#ifndef _SYS_SELECT_H
+#define _SYS_SELECT_H
+
+/* We don't define fd_set and friends if we are compiling POSIX
+   source, or if we have included (or may include as indicated
+   by __USE_W32_SOCKETS) the W32api winsock[2].h header which
+   defines Windows versions of them.   Note that a program which
+   includes the W32api winsock[2].h header must know what it is doing;
+   it must not call the Cygwin select function.
+*/
+# if !(defined (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS))
+
+#include <sys/cdefs.h>
+#include <sys/_sigset.h>
+#include <sys/_timeval.h>
+#include <sys/timespec.h>
+
+#if !defined(_SIGSET_T_DECLARED)
+#define	_SIGSET_T_DECLARED
+typedef	__sigset_t	sigset_t;
+#endif
+
+#  define _SYS_TYPES_FD_SET
+/*
+ * Select uses bit masks of file descriptors in longs.
+ * These macros manipulate such bit fields (the filesystem macros use chars).
+ * FD_SETSIZE may be defined by the user, but the default here
+ * should be >= NOFILE (param.h).
+ */
+#  ifndef	FD_SETSIZE
+#	define	FD_SETSIZE	64
+#  endif
+
+typedef	unsigned long	fd_mask;
+#  define	NFDBITS	(sizeof (fd_mask) * 8)	/* bits per mask */
+#  ifndef	_howmany
+#	define	_howmany(x,y)	(((x)+((y)-1))/(y))
+#  endif
+
+/* We use a macro for fd_set so that including Sockets.h afterwards
+   can work.  */
+typedef	struct _types_fd_set {
+	fd_mask	fds_bits[_howmany(FD_SETSIZE, NFDBITS)];
+} _types_fd_set;
+
+#define fd_set _types_fd_set
+
+#  define	FD_SET(n, p)	((p)->fds_bits[(n)/NFDBITS] |= (1L << ((n) % NFDBITS)))
+#  define	FD_CLR(n, p)	((p)->fds_bits[(n)/NFDBITS] &= ~(1L << ((n) % NFDBITS)))
+#  define	FD_ISSET(n, p)	((p)->fds_bits[(n)/NFDBITS] & (1L << ((n) % NFDBITS)))
+#  define	FD_ZERO(p)	(__extension__ (void)({ \
+     size_t __i; \
+     char *__tmp = (char *)p; \
+     for (__i = 0; __i < sizeof (*(p)); ++__i) \
+       *__tmp++ = 0; \
+}))
+
+#if !defined (__INSIDE_CYGWIN_NET__)
+
+__BEGIN_DECLS
+
+int select __P ((int __n, fd_set *__readfds, fd_set *__writefds,
+		 fd_set *__exceptfds, struct timeval *__timeout));
+#if __POSIX_VISIBLE >= 200112
+int pselect __P ((int __n, fd_set *__readfds, fd_set *__writefds,
+		  fd_set *__exceptfds, const struct timespec *__timeout,
+		  const sigset_t *__set));
+#endif
+
+__END_DECLS
+
+#endif /* !__INSIDE_CYGWIN_NET__ */
+
+#endif /* !(_WINSOCK_H || _WINSOCKAPI_ || __USE_W32_SOCKETS) */
+
+#endif /* sys/select.h */

src/include/sys/stdio.h

@@ -0,0 +1,27 @@
+#ifndef _NEWLIB_STDIO_H
+#define _NEWLIB_STDIO_H
+
+#include <sys/lock.h>
+#include <sys/reent.h>
+
+/* Internal locking macros, used to protect stdio functions.  In the
+   general case, expand to nothing. Use __SSTR flag in FILE _flags to
+   detect if FILE is private to sprintf/sscanf class of functions; if
+   set then do nothing as lock is not initialised. */
+#if !defined(_flockfile)
+#ifndef __SINGLE_THREAD__
+#  define _flockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_acquire_recursive((fp)->_lock))
+#else
+#  define _flockfile(fp)	((void) 0)
+#endif
+#endif
+
+#if !defined(_funlockfile)
+#ifndef __SINGLE_THREAD__
+#  define _funlockfile(fp) (((fp)->_flags & __SSTR) ? 0 : __lock_release_recursive((fp)->_lock))
+#else
+#  define _funlockfile(fp)	((void) 0)
+#endif
+#endif
+
+#endif /* _NEWLIB_STDIO_H */

src/include/sys/string.h

@@ -0,0 +1,2 @@
+/* This is a dummy <sys/string.h> used as a placeholder for
+   systems that need to have a special header file.  */

src/include/sys/timespec.h

@@ -0,0 +1,63 @@
+/*-
+ * Copyright (c) 1982, 1986, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)time.h	8.5 (Berkeley) 5/4/95
+ * from: FreeBSD: src/sys/sys/time.h,v 1.43 2000/03/20 14:09:05 phk Exp
+ *	$FreeBSD$
+ */
+
+#ifndef _SYS_TIMESPEC_H_
+#define _SYS_TIMESPEC_H_
+
+#include <sys/cdefs.h>
+#include <sys/_timespec.h>
+
+#if __BSD_VISIBLE
+#define	TIMEVAL_TO_TIMESPEC(tv, ts)					\
+	do {								\
+		(ts)->tv_sec = (tv)->tv_sec;				\
+		(ts)->tv_nsec = (tv)->tv_usec * 1000;			\
+	} while (0)
+#define	TIMESPEC_TO_TIMEVAL(tv, ts)					\
+	do {								\
+		(tv)->tv_sec = (ts)->tv_sec;				\
+		(tv)->tv_usec = (ts)->tv_nsec / 1000;			\
+	} while (0)
+
+#endif /* __BSD_VISIBLE */
+
+/*
+ * Structure defined by POSIX.1b to be like a itimerval, but with
+ * timespecs. Used in the timer_*() system calls.
+ */
+struct itimerspec {
+	struct timespec  it_interval;
+	struct timespec  it_value;
+};
+
+#endif /* _SYS_TIMESPEC_H_ */

src/include/sys/types.h

@@ -0,0 +1,246 @@
+/* unified sys/types.h: 
+   start with sef's sysvi386 version.
+   merge go32 version -- a few ifdefs.
+   h8300hms, h8300xray, and sysvnecv70 disagree on the following types:
+
+   typedef int gid_t;
+   typedef int uid_t;
+   typedef int dev_t;
+   typedef int ino_t;
+   typedef int mode_t;
+   typedef int caddr_t;
+
+   however, these aren't "reasonable" values, the sysvi386 ones make far 
+   more sense, and should work sufficiently well (in particular, h8300 
+   doesn't have a stat, and the necv70 doesn't matter.) -- eichin
+ */
+
+#ifndef _SYS_TYPES_H
+
+#include <_ansi.h>
+#include <sys/cdefs.h>
+#include <machine/_types.h>
+
+/* BSD types permitted by POSIX and always exposed as in Glibc.  Only provided
+   for backward compatibility with BSD code.  The uintN_t standard types should
+   be preferred in new code. */
+#if ___int8_t_defined
+typedef __uint8_t	u_int8_t;
+#endif
+#if ___int16_t_defined
+typedef __uint16_t	u_int16_t;
+#endif 
+#if ___int32_t_defined
+typedef __uint32_t	u_int32_t;
+#endif
+#if ___int64_t_defined
+typedef __uint64_t	u_int64_t;
+#endif
+typedef int register_t;
+#define __BIT_TYPES_DEFINED__ 1
+
+#if defined(__rtems__) || defined(__XMK__)
+/*
+ *  The following section is RTEMS specific and is needed to more
+ *  closely match the types defined in the BSD sys/types.h.
+ *  This is needed to let the RTEMS/BSD TCP/IP stack compile.
+ */
+
+/* deprecated */
+#if ___int64_t_defined
+typedef	__uint64_t	u_quad_t;
+typedef	__int64_t	quad_t;
+typedef	quad_t *	qaddr_t;
+#endif
+
+#endif /* __rtems__ || __XMK__ */
+
+#ifndef __need_inttypes
+
+#define _SYS_TYPES_H
+/* <stddef.h> must be before <sys/_types.h> for __size_t considerations */
+#include <stddef.h>
+#include <sys/_types.h>
+#include <sys/_stdint.h>
+
+#if __BSD_VISIBLE
+#include <machine/endian.h>
+#include <sys/select.h>
+#  define	physadr		physadr_t
+#  define	quad		quad_t
+
+#ifndef _IN_ADDR_T_DECLARED
+typedef	__uint32_t	in_addr_t;	/* base type for internet address */
+#define	_IN_ADDR_T_DECLARED
+#endif
+
+#ifndef _IN_PORT_T_DECLARED
+typedef	__uint16_t	in_port_t;
+#define	_IN_PORT_T_DECLARED
+#endif
+#endif /* __BSD_VISIBLE */
+
+#if __MISC_VISIBLE
+#ifndef _BSDTYPES_DEFINED
+/* also defined in mingw/gmon.h and in w32api/winsock[2].h */
+#ifndef __u_char_defined
+typedef	unsigned char	u_char;
+#define __u_char_defined
+#endif
+#ifndef __u_short_defined
+typedef	unsigned short	u_short;
+#define __u_short_defined
+#endif
+#ifndef __u_int_defined
+typedef	unsigned int	u_int;
+#define __u_int_defined
+#endif
+#ifndef __u_long_defined
+typedef	unsigned long	u_long;
+#define __u_long_defined
+#endif
+#define _BSDTYPES_DEFINED
+#endif
+#endif	/*__BSD_VISIBLE || __CYGWIN__ */
+
+#if __MISC_VISIBLE
+typedef	unsigned short	ushort;		/* System V compatibility */
+typedef	unsigned int	uint;		/* System V compatibility */
+typedef	unsigned long	ulong;		/* System V compatibility */
+#endif
+
+#ifndef _BLKCNT_T_DECLARED
+typedef	__blkcnt_t	blkcnt_t;
+#define	_BLKCNT_T_DECLARED
+#endif
+
+#ifndef _BLKSIZE_T_DECLARED
+typedef	__blksize_t	blksize_t;
+#define	_BLKSIZE_T_DECLARED
+#endif
+
+#if !defined(__clock_t_defined) && !defined(_CLOCK_T_DECLARED)
+typedef	_CLOCK_T_	clock_t;
+#define	__clock_t_defined
+#define	_CLOCK_T_DECLARED
+#endif
+
+#if !defined(__time_t_defined) && !defined(_TIME_T_DECLARED)
+typedef	_TIME_T_	time_t;
+#define	__time_t_defined
+#define	_TIME_T_DECLARED
+#endif
+
+#ifndef __daddr_t_defined
+typedef	long	daddr_t;
+#define __daddr_t_defined
+#endif
+#ifndef __caddr_t_defined
+typedef	char *	caddr_t;
+#define __caddr_t_defined
+#endif
+
+#ifndef _FSBLKCNT_T_DECLARED		/* for statvfs() */
+typedef	__fsblkcnt_t	fsblkcnt_t;
+typedef	__fsfilcnt_t	fsfilcnt_t;
+#define	_FSBLKCNT_T_DECLARED
+#endif
+
+#ifndef _ID_T_DECLARED
+typedef	__id_t		id_t;		/* can hold a uid_t or pid_t */
+#define	_ID_T_DECLARED
+#endif
+
+#ifndef _INO_T_DECLARED
+typedef	__ino_t		ino_t;		/* inode number */
+#define	_INO_T_DECLARED
+#endif
+
+#if defined(__i386__) && (defined(GO32) || defined(__MSDOS__))
+typedef	char *		addr_t;
+typedef unsigned long vm_offset_t;
+typedef unsigned long vm_size_t;
+#endif /* __i386__ && (GO32 || __MSDOS__) */
+
+/*
+ * All these should be machine specific - right now they are all broken.
+ * However, for all of Cygnus' embedded targets, we want them to all be
+ * the same.  Otherwise things like sizeof (struct stat) might depend on
+ * how the file was compiled (e.g. -mint16 vs -mint32, etc.).
+ */
+
+#ifndef _OFF_T_DECLARED
+typedef	__off_t		off_t;		/* file offset */
+#define	_OFF_T_DECLARED
+#endif
+#ifndef _DEV_T_DECLARED
+typedef	__dev_t		dev_t;		/* device number or struct cdev */
+#define	_DEV_T_DECLARED
+#endif
+#ifndef _UID_T_DECLARED
+typedef	__uid_t		uid_t;		/* user id */
+#define	_UID_T_DECLARED
+#endif
+#ifndef _GID_T_DECLARED
+typedef	__gid_t		gid_t;		/* group id */
+#define	_GID_T_DECLARED
+#endif
+
+#ifndef _PID_T_DECLARED
+typedef	__pid_t		pid_t;		/* process id */
+#define	_PID_T_DECLARED
+#endif
+
+#ifndef _KEY_T_DECLARED
+typedef	__key_t		key_t;		/* IPC key */
+#define	_KEY_T_DECLARED
+#endif
+
+#ifndef _SSIZE_T_DECLARED
+typedef _ssize_t ssize_t;
+#define	_SSIZE_T_DECLARED
+#endif
+
+#ifndef _MODE_T_DECLARED
+typedef	__mode_t	mode_t;		/* permissions */
+#define	_MODE_T_DECLARED
+#endif
+
+#ifndef _NLINK_T_DECLARED
+typedef	__nlink_t	nlink_t;	/* link count */
+#define	_NLINK_T_DECLARED
+#endif
+
+#if !defined(__clockid_t_defined) && !defined(_CLOCKID_T_DECLARED)
+typedef	__clockid_t	clockid_t;
+#define	__clockid_t_defined
+#define	_CLOCKID_T_DECLARED
+#endif
+
+#if !defined(__timer_t_defined) && !defined(_TIMER_T_DECLARED)
+typedef	__timer_t	timer_t;
+#define	__timer_t_defined
+#define	_TIMER_T_DECLARED
+#endif
+
+#ifndef _USECONDS_T_DECLARED
+typedef	__useconds_t	useconds_t;	/* microseconds (unsigned) */
+#define	_USECONDS_T_DECLARED
+#endif
+
+#ifndef _SUSECONDS_T_DECLARED
+typedef	__suseconds_t	suseconds_t;
+#define	_SUSECONDS_T_DECLARED
+#endif
+
+typedef	__int64_t	sbintime_t;
+
+#include <sys/features.h>
+#include <sys/_pthreadtypes.h>
+#include <machine/types.h>
+
+#endif  /* !__need_inttypes */
+
+#undef __need_inttypes
+
+#endif	/* _SYS_TYPES_H */

src/include/sys/unistd.h

@@ -0,0 +1,599 @@
+#ifndef _SYS_UNISTD_H
+#define _SYS_UNISTD_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <_ansi.h>
+#define __need_size_t
+#define __need_ptrdiff_t
+#include <sys/cdefs.h>
+#include <sys/types.h>
+#include <sys/_types.h>
+#include <stddef.h>
+
+extern char **environ;
+
+void	_exit (int __status) _ATTRIBUTE ((__noreturn__));
+
+int	access (const char *__path, int __amode);
+unsigned  alarm (unsigned __secs);
+int     chdir (const char *__path);
+int     chmod (const char *__path, mode_t __mode);
+#if !defined(__INSIDE_CYGWIN__)
+int     chown (const char *__path, uid_t __owner, gid_t __group);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE >= 4 && __POSIX_VISIBLE < 200112)
+int     chroot (const char *__path);
+#endif
+int     close (int __fildes);
+#if __POSIX_VISIBLE >= 199209
+size_t	confstr (int __name, char *__buf, size_t __len);
+#endif
+#if __XSI_VISIBLE
+char *  crypt (const char *__key, const char *__salt);
+#endif
+#if __XSI_VISIBLE && __XSI_VISIBLE < 700
+char *  ctermid (char *__s);
+#endif
+#if __XSI_VISIBLE && __XSI_VISIBLE < 600
+char *  cuserid (char *__s);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 500)
+int	daemon (int nochdir, int noclose);
+#endif
+int     dup (int __fildes);
+int     dup2 (int __fildes, int __fildes2);
+#if __GNU_VISIBLE
+int     dup3 (int __fildes, int __fildes2, int flags);
+int	eaccess (const char *__path, int __mode);
+#endif
+#if __XSI_VISIBLE
+void	encrypt (char *__block, int __edflag);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 500)
+void	endusershell (void);
+#endif
+#if __GNU_VISIBLE
+int	euidaccess (const char *__path, int __mode);
+#endif
+int     execl (const char *__path, const char *, ...);
+int     execle (const char *__path, const char *, ...);
+int     execlp (const char *__file, const char *, ...);
+#if __MISC_VISIBLE
+int     execlpe (const char *__file, const char *, ...);
+#endif
+int     execv (const char *__path, char * const __argv[]);
+int     execve (const char *__path, char * const __argv[], char * const __envp[]);
+int     execvp (const char *__file, char * const __argv[]);
+#if __GNU_VISIBLE
+int     execvpe (const char *__file, char * const __argv[], char * const __envp[]);
+#endif
+#if __ATFILE_VISIBLE
+int	faccessat (int __dirfd, const char *__path, int __mode, int __flags);
+#endif
+#if __BSD_VISIBLE || __XSI_VISIBLE >= 4 || __POSIX_VISIBLE >= 200809
+int     fchdir (int __fildes);
+#endif
+#if __POSIX_VISIBLE >= 199309
+int     fchmod (int __fildes, mode_t __mode);
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+#if __BSD_VISIBLE || __XSI_VISIBLE >= 4 || __POSIX_VISIBLE >= 200809
+int     fchown (int __fildes, uid_t __owner, gid_t __group);
+#endif
+#endif
+#if __ATFILE_VISIBLE
+int	fchownat (int __dirfd, const char *__path, uid_t __owner, gid_t __group, int __flags);
+#endif
+#if __POSIX_VISIBLE >= 200809
+int	fexecve (int __fd, char * const __argv[], char * const __envp[]);
+#endif
+pid_t   fork (void);
+long    fpathconf (int __fd, int __name);
+int     fsync (int __fd);
+#if __POSIX_VISIBLE >= 199309
+int     fdatasync (int __fd);
+#endif
+#if __GNU_VISIBLE
+char *  get_current_dir_name (void);
+#endif
+char *  getcwd (char *__buf, size_t __size);
+#if __BSD_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 500)
+int	getdomainname  (char *__name, size_t __len);
+#endif
+#if __BSD_VISIBLE
+int     getentropy (void *, size_t);
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+gid_t   getegid (void);
+uid_t   geteuid (void);
+gid_t   getgid (void);
+#endif
+int     getgroups (int __gidsetsize, gid_t __grouplist[]);
+#if __BSD_VISIBLE || __XSI_VISIBLE >= 4
+long    gethostid (void);
+#endif
+char *  getlogin (void);
+#if defined(_POSIX_THREAD_SAFE_FUNCTIONS)
+int getlogin_r (char *name, size_t namesize) ;
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE && __POSIX_VISIBLE < 200112)
+char *  getpass (const char *__prompt);
+int	getpagesize (void);
+#endif
+#if __BSD_VISIBLE
+int    getpeereid (int, uid_t *, gid_t *);
+#endif
+#if __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE >= 4
+pid_t   getpgid (pid_t);
+#endif
+pid_t   getpgrp (void);
+pid_t   getpid (void);
+pid_t   getppid (void);
+#if __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE >= 4
+pid_t   getsid (pid_t);
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+uid_t   getuid (void);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 500)
+char *	getusershell (void);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE >= 4 && __POSIX_VISIBLE < 200809)
+char *  getwd (char *__buf);
+#endif
+#if __BSD_VISIBLE
+int	iruserok (unsigned long raddr, int superuser, const char *ruser, const char *luser);
+#endif
+int     isatty (int __fildes);
+#if __BSD_VISIBLE
+int        issetugid (void);
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+#if __BSD_VISIBLE || __XSI_VISIBLE >= 4 || __POSIX_VISIBLE >= 200809
+int     lchown (const char *__path, uid_t __owner, gid_t __group);
+#endif
+#endif
+int     link (const char *__path1, const char *__path2);
+#if __ATFILE_VISIBLE
+int     linkat (int __dirfd1, const char *__path1, int __dirfd2, const char *__path2, int __flags);
+#endif
+#if __MISC_VISIBLE || __XSI_VISIBLE
+int	nice (int __nice_value);
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+off_t   lseek (int __fildes, off_t __offset, int __whence);
+#endif
+#if __MISC_VISIBLE || __XSI_VISIBLE >= 4
+#define F_ULOCK	0
+#define F_LOCK	1
+#define F_TLOCK	2
+#define F_TEST	3
+int     lockf (int __fd, int __cmd, off_t __len);
+#endif
+long    pathconf (const char *__path, int __name);
+int     pause (void);
+#if __POSIX_VISIBLE >= 199506
+int	pthread_atfork (void (*)(void), void (*)(void), void (*)(void));
+#endif
+int     pipe (int __fildes[2]);
+#if __GNU_VISIBLE
+int     pipe2 (int __fildes[2], int flags);
+#endif
+#if __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE >= 500
+ssize_t pread (int __fd, void *__buf, size_t __nbytes, off_t __offset);
+ssize_t pwrite (int __fd, const void *__buf, size_t __nbytes, off_t __offset);
+#endif
+_READ_WRITE_RETURN_TYPE read (int __fd, void *__buf, size_t __nbyte);
+#if __BSD_VISIBLE
+int	rresvport (int *__alport);
+int	revoke (char *__path);
+#endif
+int     rmdir (const char *__path);
+#if __BSD_VISIBLE
+int	ruserok (const char *rhost, int superuser, const char *ruser, const char *luser);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE >= 4 && __POSIX_VISIBLE < 200112)
+void *  sbrk (ptrdiff_t __incr);
+#endif
+#if !defined(__INSIDE_CYGWIN__)
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200112
+int     setegid (gid_t __gid);
+int     seteuid (uid_t __uid);
+#endif
+int     setgid (gid_t __gid);
+#endif
+#if __BSD_VISIBLE
+int	setgroups (int ngroups, const gid_t *grouplist);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 500)
+int	sethostname (const char *, size_t);
+#endif
+int     setpgid (pid_t __pid, pid_t __pgid);
+#if __SVID_VISIBLE || __XSI_VISIBLE >= 500
+int     setpgrp (void);
+#endif
+#if (__BSD_VISIBLE || __XSI_VISIBLE >= 4) && !defined(__INSIDE_CYGWIN__)
+int	setregid (gid_t __rgid, gid_t __egid);
+int	setreuid (uid_t __ruid, uid_t __euid);
+#endif
+pid_t   setsid (void);
+#if !defined(__INSIDE_CYGWIN__)
+int     setuid (uid_t __uid);
+#endif
+#if __BSD_VISIBLE || (__XSI_VISIBLE && __XSI_VISIBLE < 500)
+void	setusershell (void);
+#endif
+unsigned sleep (unsigned int __seconds);
+#if __XSI_VISIBLE
+void    swab (const void *__restrict, void *__restrict, ssize_t);
+#endif
+long    sysconf (int __name);
+pid_t   tcgetpgrp (int __fildes);
+int     tcsetpgrp (int __fildes, pid_t __pgrp_id);
+char *  ttyname (int __fildes);
+int     ttyname_r (int, char *, size_t);
+int     unlink (const char *__path);
+#if __XSI_VISIBLE >= 500 && __POSIX_VISIBLE < 200809 || __BSD_VISIBLE
+int 	usleep (useconds_t __useconds);
+#endif
+#if __BSD_VISIBLE
+int     vhangup (void);
+#endif
+_READ_WRITE_RETURN_TYPE write (int __fd, const void *__buf, size_t __nbyte);
+
+#ifdef __CYGWIN__
+# define __UNISTD_GETOPT__
+# include <getopt.h>
+# undef __UNISTD_GETOPT__
+#else
+extern char *optarg;			/* getopt(3) external variables */
+extern int optind, opterr, optopt;
+int	 getopt(int, char * const [], const char *);
+extern int optreset;			/* getopt(3) external variable */
+#endif
+
+#if __BSD_VISIBLE || (__XSI_VISIBLE >= 4 && __POSIX_VISIBLE < 200809)
+pid_t   vfork (void);
+#endif
+
+#ifdef _COMPILING_NEWLIB
+/* Provide prototypes for most of the _<systemcall> names that are
+   provided in newlib for some compilers.  */
+int     _close (int __fildes);
+pid_t   _fork (void);
+pid_t   _getpid (void);
+int	_isatty (int __fildes);
+int     _link (const char *__path1, const char *__path2);
+_off_t   _lseek (int __fildes, _off_t __offset, int __whence);
+#ifdef __LARGE64_FILES
+_off64_t _lseek64 (int __filedes, _off64_t __offset, int __whence);
+#endif
+_READ_WRITE_RETURN_TYPE _read (int __fd, void *__buf, size_t __nbyte);
+void *  _sbrk (ptrdiff_t __incr);
+int     _unlink (const char *__path);
+_READ_WRITE_RETURN_TYPE _write (int __fd, const void *__buf, size_t __nbyte);
+int     _execve (const char *__path, char * const __argv[], char * const __envp[]);
+#endif
+
+#if !defined(__INSIDE_CYGWIN__)
+#if __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE >= 500
+int     ftruncate (int __fd, off_t __length);
+#endif
+#if __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE >= 500
+int     truncate (const char *, off_t __length);
+#endif
+#endif
+
+#if __BSD_VISIBLE || __POSIX_VISIBLE < 200112
+int	getdtablesize (void);
+#endif
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200809 || __XSI_VISIBLE >= 500
+useconds_t ualarm (useconds_t __useconds, useconds_t __interval);
+#endif
+
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE >= 500
+#if !(defined  (_WINSOCK_H) || defined (_WINSOCKAPI_) || defined (__USE_W32_SOCKETS))
+/* winsock[2].h defines as __stdcall, and with int as 2nd arg */
+ int	gethostname (char *__name, size_t __len);
+#endif
+#endif
+
+#if __MISC_VISIBLE
+int	setdtablesize (int);
+#endif
+
+#if __BSD_VISIBLE || __XSI_VISIBLE >= 500
+void    sync (void);
+#endif
+
+#if __BSD_VISIBLE || __POSIX_VISIBLE >= 200112 || __XSI_VISIBLE >= 4
+ssize_t readlink (const char *__restrict __path,
+                          char *__restrict __buf, size_t __buflen);
+int     symlink (const char *__name1, const char *__name2);
+#endif
+#if __ATFILE_VISIBLE
+ssize_t        readlinkat (int __dirfd1, const char *__restrict __path,
+                            char *__restrict __buf, size_t __buflen);
+int	symlinkat (const char *, int, const char *);
+int	unlinkat (int, const char *, int);
+#endif
+
+#define	F_OK	0
+#define	R_OK	4
+#define	W_OK	2
+#define	X_OK	1
+
+# define	SEEK_SET	0
+# define	SEEK_CUR	1
+# define	SEEK_END	2
+
+#include <sys/features.h>
+
+#define STDIN_FILENO    0       /* standard input file descriptor */
+#define STDOUT_FILENO   1       /* standard output file descriptor */
+#define STDERR_FILENO   2       /* standard error file descriptor */
+
+/*
+ *  sysconf values per IEEE Std 1003.1, 2008 Edition
+ */
+
+#define _SC_ARG_MAX                       0
+#define _SC_CHILD_MAX                     1
+#define _SC_CLK_TCK                       2
+#define _SC_NGROUPS_MAX                   3
+#define _SC_OPEN_MAX                      4
+#define _SC_JOB_CONTROL                   5
+#define _SC_SAVED_IDS                     6
+#define _SC_VERSION                       7
+#define _SC_PAGESIZE                      8
+#define _SC_PAGE_SIZE                     _SC_PAGESIZE
+/* These are non-POSIX values we accidentally introduced in 2000 without
+   guarding them.  Keeping them unguarded for backward compatibility. */
+#define _SC_NPROCESSORS_CONF              9
+#define _SC_NPROCESSORS_ONLN             10
+#define _SC_PHYS_PAGES                   11
+#define _SC_AVPHYS_PAGES                 12
+/* End of non-POSIX values. */
+#define _SC_MQ_OPEN_MAX                  13
+#define _SC_MQ_PRIO_MAX                  14
+#define _SC_RTSIG_MAX                    15
+#define _SC_SEM_NSEMS_MAX                16
+#define _SC_SEM_VALUE_MAX                17
+#define _SC_SIGQUEUE_MAX                 18
+#define _SC_TIMER_MAX                    19
+#define _SC_TZNAME_MAX                   20
+#define _SC_ASYNCHRONOUS_IO              21
+#define _SC_FSYNC                        22
+#define _SC_MAPPED_FILES                 23
+#define _SC_MEMLOCK                      24
+#define _SC_MEMLOCK_RANGE                25
+#define _SC_MEMORY_PROTECTION            26
+#define _SC_MESSAGE_PASSING              27
+#define _SC_PRIORITIZED_IO               28
+#define _SC_REALTIME_SIGNALS             29
+#define _SC_SEMAPHORES                   30
+#define _SC_SHARED_MEMORY_OBJECTS        31
+#define _SC_SYNCHRONIZED_IO              32
+#define _SC_TIMERS                       33
+#define _SC_AIO_LISTIO_MAX               34
+#define _SC_AIO_MAX                      35
+#define _SC_AIO_PRIO_DELTA_MAX           36
+#define _SC_DELAYTIMER_MAX               37
+#define _SC_THREAD_KEYS_MAX              38
+#define _SC_THREAD_STACK_MIN             39
+#define _SC_THREAD_THREADS_MAX           40
+#define _SC_TTY_NAME_MAX                 41
+#define _SC_THREADS                      42
+#define _SC_THREAD_ATTR_STACKADDR        43
+#define _SC_THREAD_ATTR_STACKSIZE        44
+#define _SC_THREAD_PRIORITY_SCHEDULING   45
+#define _SC_THREAD_PRIO_INHERIT          46
+/* _SC_THREAD_PRIO_PROTECT was _SC_THREAD_PRIO_CEILING in early drafts */
+#define _SC_THREAD_PRIO_PROTECT          47
+#define _SC_THREAD_PRIO_CEILING          _SC_THREAD_PRIO_PROTECT
+#define _SC_THREAD_PROCESS_SHARED        48
+#define _SC_THREAD_SAFE_FUNCTIONS        49
+#define _SC_GETGR_R_SIZE_MAX             50
+#define _SC_GETPW_R_SIZE_MAX             51
+#define _SC_LOGIN_NAME_MAX               52
+#define _SC_THREAD_DESTRUCTOR_ITERATIONS 53
+#define _SC_ADVISORY_INFO                54
+#define _SC_ATEXIT_MAX                   55
+#define _SC_BARRIERS                     56
+#define _SC_BC_BASE_MAX                  57
+#define _SC_BC_DIM_MAX                   58
+#define _SC_BC_SCALE_MAX                 59
+#define _SC_BC_STRING_MAX                60
+#define _SC_CLOCK_SELECTION              61
+#define _SC_COLL_WEIGHTS_MAX             62
+#define _SC_CPUTIME                      63
+#define _SC_EXPR_NEST_MAX                64
+#define _SC_HOST_NAME_MAX                65
+#define _SC_IOV_MAX                      66
+#define _SC_IPV6                         67
+#define _SC_LINE_MAX                     68
+#define _SC_MONOTONIC_CLOCK              69
+#define _SC_RAW_SOCKETS                  70
+#define _SC_READER_WRITER_LOCKS          71
+#define _SC_REGEXP                       72
+#define _SC_RE_DUP_MAX                   73
+#define _SC_SHELL                        74
+#define _SC_SPAWN                        75
+#define _SC_SPIN_LOCKS                   76
+#define _SC_SPORADIC_SERVER              77
+#define _SC_SS_REPL_MAX                  78
+#define _SC_SYMLOOP_MAX                  79
+#define _SC_THREAD_CPUTIME               80
+#define _SC_THREAD_SPORADIC_SERVER       81
+#define _SC_TIMEOUTS                     82
+#define _SC_TRACE                        83
+#define _SC_TRACE_EVENT_FILTER           84
+#define _SC_TRACE_EVENT_NAME_MAX         85
+#define _SC_TRACE_INHERIT                86
+#define _SC_TRACE_LOG                    87
+#define _SC_TRACE_NAME_MAX               88
+#define _SC_TRACE_SYS_MAX                89
+#define _SC_TRACE_USER_EVENT_MAX         90
+#define _SC_TYPED_MEMORY_OBJECTS         91
+#define _SC_V7_ILP32_OFF32               92
+#define _SC_V6_ILP32_OFF32               _SC_V7_ILP32_OFF32
+#define _SC_XBS5_ILP32_OFF32             _SC_V7_ILP32_OFF32
+#define _SC_V7_ILP32_OFFBIG              93
+#define _SC_V6_ILP32_OFFBIG              _SC_V7_ILP32_OFFBIG
+#define _SC_XBS5_ILP32_OFFBIG            _SC_V7_ILP32_OFFBIG
+#define _SC_V7_LP64_OFF64                94
+#define _SC_V6_LP64_OFF64                _SC_V7_LP64_OFF64
+#define _SC_XBS5_LP64_OFF64              _SC_V7_LP64_OFF64
+#define _SC_V7_LPBIG_OFFBIG              95
+#define _SC_V6_LPBIG_OFFBIG              _SC_V7_LPBIG_OFFBIG
+#define _SC_XBS5_LPBIG_OFFBIG            _SC_V7_LPBIG_OFFBIG
+#define _SC_XOPEN_CRYPT                  96
+#define _SC_XOPEN_ENH_I18N               97
+#define _SC_XOPEN_LEGACY                 98
+#define _SC_XOPEN_REALTIME               99
+#define _SC_STREAM_MAX                  100
+#define _SC_PRIORITY_SCHEDULING         101
+#define _SC_XOPEN_REALTIME_THREADS      102
+#define _SC_XOPEN_SHM                   103
+#define _SC_XOPEN_STREAMS               104
+#define _SC_XOPEN_UNIX                  105
+#define _SC_XOPEN_VERSION               106
+#define _SC_2_CHAR_TERM                 107
+#define _SC_2_C_BIND                    108
+#define _SC_2_C_DEV                     109
+#define _SC_2_FORT_DEV                  110
+#define _SC_2_FORT_RUN                  111
+#define _SC_2_LOCALEDEF                 112
+#define _SC_2_PBS                       113
+#define _SC_2_PBS_ACCOUNTING            114
+#define _SC_2_PBS_CHECKPOINT            115
+#define _SC_2_PBS_LOCATE                116
+#define _SC_2_PBS_MESSAGE               117
+#define _SC_2_PBS_TRACK                 118
+#define _SC_2_SW_DEV                    119
+#define _SC_2_UPE                       120
+#define _SC_2_VERSION                   121
+#define _SC_THREAD_ROBUST_PRIO_INHERIT  122
+#define _SC_THREAD_ROBUST_PRIO_PROTECT  123
+#define _SC_XOPEN_UUCP                  124
+#define _SC_LEVEL1_ICACHE_SIZE          125
+#define _SC_LEVEL1_ICACHE_ASSOC         126
+#define _SC_LEVEL1_ICACHE_LINESIZE      127
+#define _SC_LEVEL1_DCACHE_SIZE          128
+#define _SC_LEVEL1_DCACHE_ASSOC         129
+#define _SC_LEVEL1_DCACHE_LINESIZE      130
+#define _SC_LEVEL2_CACHE_SIZE           131
+#define _SC_LEVEL2_CACHE_ASSOC          132
+#define _SC_LEVEL2_CACHE_LINESIZE       133
+#define _SC_LEVEL3_CACHE_SIZE           134
+#define _SC_LEVEL3_CACHE_ASSOC          135
+#define _SC_LEVEL3_CACHE_LINESIZE       136
+#define _SC_LEVEL4_CACHE_SIZE           137
+#define _SC_LEVEL4_CACHE_ASSOC          138
+#define _SC_LEVEL4_CACHE_LINESIZE       139
+#define _SC_POSIX_26_VERSION            140
+
+/*
+ *  pathconf values per IEEE Std 1003.1, 2008 Edition
+ */
+
+#define _PC_LINK_MAX                      0
+#define _PC_MAX_CANON                     1
+#define _PC_MAX_INPUT                     2
+#define _PC_NAME_MAX                      3
+#define _PC_PATH_MAX                      4
+#define _PC_PIPE_BUF                      5
+#define _PC_CHOWN_RESTRICTED              6
+#define _PC_NO_TRUNC                      7
+#define _PC_VDISABLE                      8
+#define _PC_ASYNC_IO                      9
+#define _PC_PRIO_IO                      10
+#define _PC_SYNC_IO                      11
+#define _PC_FILESIZEBITS                 12
+#define _PC_2_SYMLINKS                   13
+#define _PC_SYMLINK_MAX                  14
+#define _PC_ALLOC_SIZE_MIN               15
+#define _PC_REC_INCR_XFER_SIZE           16
+#define _PC_REC_MAX_XFER_SIZE            17
+#define _PC_REC_MIN_XFER_SIZE            18
+#define _PC_REC_XFER_ALIGN               19
+#define _PC_TIMESTAMP_RESOLUTION         20
+#ifdef __CYGWIN__
+/* Ask for POSIX permission bits support. */
+#define _PC_POSIX_PERMISSIONS            90
+/* Ask for full POSIX permission support including uid/gid settings. */
+#define _PC_POSIX_SECURITY               91
+#define _PC_CASE_INSENSITIVE             92
+#endif
+
+/*
+ *  confstr values per IEEE Std 1003.1, 2004 Edition
+ */
+
+#ifdef __CYGWIN__	/* Only defined on Cygwin for now. */
+#define _CS_PATH                               0
+#define _CS_POSIX_V7_ILP32_OFF32_CFLAGS        1
+#define _CS_POSIX_V6_ILP32_OFF32_CFLAGS       _CS_POSIX_V7_ILP32_OFF32_CFLAGS
+#define _CS_XBS5_ILP32_OFF32_CFLAGS           _CS_POSIX_V7_ILP32_OFF32_CFLAGS
+#define _CS_POSIX_V7_ILP32_OFF32_LDFLAGS       2
+#define _CS_POSIX_V6_ILP32_OFF32_LDFLAGS      _CS_POSIX_V7_ILP32_OFF32_LDFLAGS
+#define _CS_XBS5_ILP32_OFF32_LDFLAGS          _CS_POSIX_V7_ILP32_OFF32_LDFLAGS
+#define _CS_POSIX_V7_ILP32_OFF32_LIBS          3
+#define _CS_POSIX_V6_ILP32_OFF32_LIBS         _CS_POSIX_V7_ILP32_OFF32_LIBS
+#define _CS_XBS5_ILP32_OFF32_LIBS             _CS_POSIX_V7_ILP32_OFF32_LIBS
+#define _CS_XBS5_ILP32_OFF32_LINTFLAGS         4
+#define _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS       5
+#define _CS_POSIX_V6_ILP32_OFFBIG_CFLAGS      _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS
+#define _CS_XBS5_ILP32_OFFBIG_CFLAGS          _CS_POSIX_V7_ILP32_OFFBIG_CFLAGS
+#define _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS      6
+#define _CS_POSIX_V6_ILP32_OFFBIG_LDFLAGS     _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS
+#define _CS_XBS5_ILP32_OFFBIG_LDFLAGS         _CS_POSIX_V7_ILP32_OFFBIG_LDFLAGS
+#define _CS_POSIX_V7_ILP32_OFFBIG_LIBS         7
+#define _CS_POSIX_V6_ILP32_OFFBIG_LIBS        _CS_POSIX_V7_ILP32_OFFBIG_LIBS
+#define _CS_XBS5_ILP32_OFFBIG_LIBS            _CS_POSIX_V7_ILP32_OFFBIG_LIBS
+#define _CS_XBS5_ILP32_OFFBIG_LINTFLAGS        8
+#define _CS_POSIX_V7_LP64_OFF64_CFLAGS         9
+#define _CS_POSIX_V6_LP64_OFF64_CFLAGS        _CS_POSIX_V7_LP64_OFF64_CFLAGS
+#define _CS_XBS5_LP64_OFF64_CFLAGS            _CS_POSIX_V7_LP64_OFF64_CFLAGS
+#define _CS_POSIX_V7_LP64_OFF64_LDFLAGS       10
+#define _CS_POSIX_V6_LP64_OFF64_LDFLAGS       _CS_POSIX_V7_LP64_OFF64_LDFLAGS
+#define _CS_XBS5_LP64_OFF64_LDFLAGS           _CS_POSIX_V7_LP64_OFF64_LDFLAGS
+#define _CS_POSIX_V7_LP64_OFF64_LIBS          11
+#define _CS_POSIX_V6_LP64_OFF64_LIBS          _CS_POSIX_V7_LP64_OFF64_LIBS
+#define _CS_XBS5_LP64_OFF64_LIBS              _CS_POSIX_V7_LP64_OFF64_LIBS
+#define _CS_XBS5_LP64_OFF64_LINTFLAGS         12
+#define _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS      13
+#define _CS_POSIX_V6_LPBIG_OFFBIG_CFLAGS      _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS
+#define _CS_XBS5_LPBIG_OFFBIG_CFLAGS          _CS_POSIX_V7_LPBIG_OFFBIG_CFLAGS
+#define _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS     14
+#define _CS_POSIX_V6_LPBIG_OFFBIG_LDFLAGS     _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS
+#define _CS_XBS5_LPBIG_OFFBIG_LDFLAGS         _CS_POSIX_V7_LPBIG_OFFBIG_LDFLAGS
+#define _CS_POSIX_V7_LPBIG_OFFBIG_LIBS        15
+#define _CS_POSIX_V6_LPBIG_OFFBIG_LIBS        _CS_POSIX_V7_LPBIG_OFFBIG_LIBS
+#define _CS_XBS5_LPBIG_OFFBIG_LIBS            _CS_POSIX_V7_LPBIG_OFFBIG_LIBS
+#define _CS_XBS5_LPBIG_OFFBIG_LINTFLAGS       16
+#define _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS    17
+#define _CS_POSIX_V6_WIDTH_RESTRICTED_ENVS    _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS
+#define _CS_XBS5_WIDTH_RESTRICTED_ENVS        _CS_POSIX_V7_WIDTH_RESTRICTED_ENVS
+#define _CS_POSIX_V7_THREADS_CFLAGS           18
+#define _CS_POSIX_V7_THREADS_LDFLAGS          19
+#define _CS_V7_ENV                            20
+#define _CS_V6_ENV                            _CS_V7_ENV
+#define _CS_LFS_CFLAGS                        21
+#define _CS_LFS_LDFLAGS                       22
+#define _CS_LFS_LIBS                          23
+#define _CS_LFS_LINTFLAGS                     24
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#if __SSP_FORTIFY_LEVEL > 0
+#include <ssp/unistd.h>
+#endif
+
+#endif /* _SYS_UNISTD_H */

src/include/unistd.h

@@ -0,0 +1,6 @@
+#ifndef _UNISTD_H_
+#define _UNISTD_H_
+
+# include <sys/unistd.h>
+
+#endif /* _UNISTD_H_ */

src/include/xlocale.h

@@ -0,0 +1,12 @@
+/* Definition of opaque POSIX-1.2008 type locale_t for userspace. */
+
+#ifndef	_XLOCALE_H
+#define _XLOCALE_H
+
+#include <newlib.h>
+#include <sys/config.h>
+
+struct __locale_t;
+typedef struct __locale_t *locale_t;
+
+#endif	/* _XLOCALE_H */

src/libboard_artiq/Cargo.toml.tpl

@@ -0,0 +1,34 @@
+[package]
+name = "libboard_artiq"
+version = "0.0.0"
+authors = ["M-Labs"]
+edition = "2018"
+
+[lib]
+name = "libboard_artiq"
+
+[features]
+target_zc706 = ["libboard_zynq/target_zc706", "libconfig/target_zc706"]
+target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
+target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
+calibrate_wrpll_skew = []
+
+[build-dependencies]
+build_zynq = { path = "../libbuild_zynq" }
+
+[dependencies]
+log = "0.4"
+log_buffer = { version = "1.2" }
+crc = { version = "1.7", default-features = false }
+core_io = { version = "0.1", features = ["collections"] }
+embedded-hal = "0.2"
+nb = "1.0"
+void = { version = "1", default-features = false }
+
+io = { path = "../libio", features = ["byteorder"] }
+libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq" }
+libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }
+libregister = { path = "@@ZYNQ_RS@@/libregister" }
+libconfig = { path = "@@ZYNQ_RS@@/libconfig", features = ["fat_lfn"] }
+libcortex_a9 = { path = "@@ZYNQ_RS@@/libcortex_a9" }
+libasync = { path = "@@ZYNQ_RS@@/libasync" }

src/libboard_artiq/build.rs

@@ -0,0 +1,5 @@
+extern crate build_zynq;
+
+fn main() {
+    build_zynq::cfg();
+}

src/libboard_artiq/src/drtio_eem.rs

@@ -0,0 +1,245 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::timer::GlobalTimer;
+use libconfig::Config;
+use libsupport_zynq::alloc::format;
+use log::{debug, error, info};
+
+use crate::pl;
+
+struct SerdesConfig {
+    pub delay: [u8; 4],
+}
+
+impl SerdesConfig {
+    pub fn as_bytes(&self) -> &[u8] {
+        unsafe {
+            core::slice::from_raw_parts(
+                (self as *const SerdesConfig) as *const u8,
+                core::mem::size_of::<SerdesConfig>(),
+            )
+        }
+    }
+}
+
+fn select_lane(lane_no: u8) {
+    unsafe {
+        pl::csr::eem_transceiver::lane_sel_write(lane_no);
+    }
+}
+
+fn apply_delay(tap: u8, timer: &mut GlobalTimer) {
+    unsafe {
+        pl::csr::eem_transceiver::dly_cnt_in_write(tap);
+        pl::csr::eem_transceiver::dly_ld_write(1);
+        timer.delay_us(1);
+        assert!(tap as u8 == pl::csr::eem_transceiver::dly_cnt_out_read());
+    }
+}
+
+fn apply_config(config: &SerdesConfig, timer: &mut GlobalTimer) {
+    for lane_no in 0..4 {
+        select_lane(lane_no as u8);
+        apply_delay(config.delay[lane_no], timer);
+    }
+}
+
+unsafe fn assign_delay(timer: &mut GlobalTimer) -> SerdesConfig {
+    // Select an appropriate delay for lane 0
+    select_lane(0);
+
+    //
+
+    let mut best_dly = None;
+
+    loop {
+        let mut prev = None;
+        for curr_dly in 0..32 {
+            //let read_align = read_align_fn(curr_dly, timer);
+            let curr_low_rate = read_align(curr_dly, timer);
+
+            if let Some(prev_low_rate) = prev {
+                // This is potentially a crossover position
+                if prev_low_rate <= curr_low_rate && curr_low_rate >= 0.5 {
+                    let prev_dev = 0.5 - prev_low_rate;
+                    let curr_dev = curr_low_rate - 0.5;
+                    let selected_idx = if prev_dev < curr_dev { curr_dly - 1 } else { curr_dly };
+
+                    // The setup setup/hold calibration timing (even with
+                    // tolerance) might be invalid in other lanes due to skew.
+                    // 5 taps is very conservative, generally it is 1 or 2
+                    if selected_idx < 5 {
+                        prev = None;
+                        continue;
+                    } else {
+                        best_dly = Some(selected_idx);
+                        break;
+                    }
+                }
+            }
+
+            // Only rising slope from <= 0.5 can result in a rising low rate
+            // crossover at 50%.
+            if curr_low_rate <= 0.5 {
+                prev = Some(curr_low_rate);
+            }
+        }
+
+        if best_dly.is_none() {
+            error!("setup/hold timing calibration failed, retry in 1s...");
+            timer.delay_us(1_000_000);
+        } else {
+            break;
+        }
+    }
+
+    let best_dly = best_dly.unwrap();
+
+    apply_delay(best_dly, timer);
+    let mut delay_list = [best_dly; 4];
+
+    // Assign delay for other lanes
+    for lane_no in 1..=3 {
+        select_lane(lane_no as u8);
+
+        let mut min_deviation = 0.5;
+        let mut min_idx = 0;
+        for dly_delta in -3..=3 {
+            let index = (best_dly as isize + dly_delta) as u8;
+            let low_rate = read_align(index, timer);
+            // abs() from f32 is not available in core library
+            let deviation = if low_rate < 0.5 { 0.5 - low_rate } else { low_rate - 0.5 };
+
+            if deviation < min_deviation {
+                min_deviation = deviation;
+                min_idx = index;
+            }
+        }
+
+        apply_delay(min_idx, timer);
+        delay_list[lane_no] = min_idx;
+    }
+
+    debug!("setup/hold timing calibration: {:?}", delay_list);
+
+    SerdesConfig { delay: delay_list }
+}
+
+fn read_align(dly: u8, timer: &mut GlobalTimer) -> f32 {
+    unsafe {
+        apply_delay(dly, timer);
+        pl::csr::eem_transceiver::counter_reset_write(1);
+
+        pl::csr::eem_transceiver::counter_enable_write(1);
+        timer.delay_us(2000);
+        pl::csr::eem_transceiver::counter_enable_write(0);
+
+        let (high, low) = (
+            pl::csr::eem_transceiver::counter_high_count_read(),
+            pl::csr::eem_transceiver::counter_low_count_read(),
+        );
+        if pl::csr::eem_transceiver::counter_overflow_read() == 1 {
+            panic!("Unexpected phase detector counter overflow");
+        }
+
+        low as f32 / (low + high) as f32
+    }
+}
+
+unsafe fn align_comma(timer: &mut GlobalTimer) {
+    loop {
+        for slip in 1..=10 {
+            // The soft transceiver has 2 8b10b decoders, which receives lane
+            // 0/1 and lane 2/3 respectively. The decoder are time-multiplexed
+            // to decode exactly 1 lane each sysclk cycle.
+            //
+            // The decoder decodes lane 0/2 data on odd sysclk cycles, buffer
+            // on even cycles, and vice versa for lane 1/3. Data/Clock latency
+            // could change timing. The extend bit flips the decoding timing,
+            // so lane 0/2 data are decoded on even cycles, and lane 1/3 data
+            // are decoded on odd cycles.
+            //
+            // This is needed because transmitting/receiving a 8b10b character
+            // takes 2 sysclk cycles. Adjusting bitslip only via ISERDES
+            // limits the range to 1 cycle. The wordslip bit extends the range
+            // to 2 sysclk cycles.
+            pl::csr::eem_transceiver::wordslip_write((slip > 5) as u8);
+
+            // Apply a double bitslip since the ISERDES is 2x oversampled.
+            // Bitslip is used for comma alignment purposes once setup/hold
+            // timing is met.
+            pl::csr::eem_transceiver::bitslip_write(1);
+            pl::csr::eem_transceiver::bitslip_write(1);
+            timer.delay_us(1);
+
+            pl::csr::eem_transceiver::comma_align_reset_write(1);
+            timer.delay_us(100);
+
+            if pl::csr::eem_transceiver::comma_read() == 1 {
+                debug!("comma alignment completed after {} bitslips", slip);
+                return;
+            }
+        }
+
+        error!("comma alignment failed, retrying in 1s...");
+        timer.delay_us(1_000_000);
+    }
+}
+
+pub unsafe fn align_wordslip(timer: &mut GlobalTimer, trx_no: u8) -> bool {
+    pl::csr::eem_transceiver::transceiver_sel_write(trx_no);
+
+    for slip in 0..=1 {
+        pl::csr::eem_transceiver::wordslip_write(slip as u8);
+        timer.delay_us(1);
+        pl::csr::eem_transceiver::comma_align_reset_write(1);
+        timer.delay_us(100);
+
+        if pl::csr::eem_transceiver::comma_read() == 1 {
+            debug!("comma alignment completed with {} wordslip", slip);
+            return true;
+        }
+    }
+
+    false
+}
+
+pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
+    for trx_no in 0..pl::csr::CONFIG_EEM_DRTIO_COUNT {
+        unsafe {
+            pl::csr::eem_transceiver::transceiver_sel_write(trx_no as u8);
+        }
+
+        let key = format!("eem_drtio_delay{}", trx_no);
+
+        let cfg_read = cfg.read(&key);
+        match cfg_read {
+            Ok(record) => {
+                info!("loading calibrated timing values from sd card");
+                unsafe {
+                    apply_config(&*(record.as_ptr() as *const SerdesConfig), timer);
+                }
+            }
+            Err(_) => {
+                info!("calibrating...");
+                let config = unsafe { assign_delay(timer) };
+
+                match cfg.write(&key, config.as_bytes().to_vec()) {
+                    Ok(()) => {
+                        info!("storing calibration timing values into sd card");
+                    }
+                    Err(e) => {
+                        error!(
+                            "calibration successful but calibration timing values cannot be stored into sd card. \
+                             Error:{}",
+                            e
+                        );
+                    }
+                };
+            }
+        }
+
+        unsafe {
+            align_comma(timer);
+        }
+    }
+}

src/libboard_artiq/src/drtio_routing.rs

@@ -0,0 +1,107 @@
+use core::fmt;
+
+use libconfig::Config;
+use log::{info, warn};
+
+#[cfg(has_drtio_routing)]
+use crate::pl::csr;
+
+#[cfg(has_drtio_routing)]
+pub const DEST_COUNT: usize = 256;
+#[cfg(not(has_drtio_routing))]
+pub const DEST_COUNT: usize = 0;
+pub const MAX_HOPS: usize = 32;
+pub const INVALID_HOP: u8 = 0xff;
+
+pub struct RoutingTable(pub [[u8; MAX_HOPS]; DEST_COUNT]);
+
+impl RoutingTable {
+    // default routing table is for star topology with no repeaters
+    pub fn default_master(default_n_links: usize) -> RoutingTable {
+        let mut ret = RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT]);
+        let n_entries = default_n_links + 1; // include local RTIO
+        for i in 0..n_entries {
+            ret.0[i][0] = i as u8;
+        }
+        for i in 1..n_entries {
+            ret.0[i][1] = 0x00;
+        }
+        ret
+    }
+
+    // use this by default on satellite, as they receive
+    // the routing table from the master
+    pub fn default_empty() -> RoutingTable {
+        RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT])
+    }
+}
+
+impl fmt::Display for RoutingTable {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        write!(f, "RoutingTable {{")?;
+        for i in 0..DEST_COUNT {
+            if self.0[i][0] != INVALID_HOP {
+                write!(f, " {}:", i)?;
+                for j in 0..MAX_HOPS {
+                    if self.0[i][j] == INVALID_HOP {
+                        break;
+                    }
+                    write!(f, " {}", self.0[i][j])?;
+                }
+                write!(f, ";")?;
+            }
+        }
+        write!(f, " }}")?;
+        Ok(())
+    }
+}
+
+pub fn config_routing_table(default_n_links: usize, cfg: &Config) -> RoutingTable {
+    let mut ret = RoutingTable::default_master(default_n_links);
+    if let Ok(data) = cfg.read("routing_table") {
+        if data.len() == DEST_COUNT * MAX_HOPS {
+            for i in 0..DEST_COUNT {
+                for j in 0..MAX_HOPS {
+                    ret.0[i][j] = data[i * MAX_HOPS + j];
+                }
+            }
+        } else {
+            warn!("length of the configured routing table is incorrect, using default");
+        }
+    } else {
+        info!("could not read routing table from configuration, using default");
+    }
+    info!("routing table: {}", ret);
+    ret
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_enable(routing_table: &RoutingTable, rank: u8, destination: u8) {
+    let hop = routing_table.0[destination as usize][rank as usize];
+    unsafe {
+        csr::routing_table::destination_write(destination);
+        csr::routing_table::hop_write(hop);
+    }
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_disable(destination: u8) {
+    unsafe {
+        csr::routing_table::destination_write(destination);
+        csr::routing_table::hop_write(INVALID_HOP);
+    }
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_enable_all(routing_table: &RoutingTable, rank: u8) {
+    for i in 0..DEST_COUNT {
+        interconnect_enable(routing_table, rank, i as u8);
+    }
+}
+
+#[cfg(has_drtio_routing)]
+pub fn interconnect_disable_all() {
+    for i in 0..DEST_COUNT {
+        interconnect_disable(i as u8);
+    }
+}

src/libboard_artiq/src/drtioaux.rs

@@ -0,0 +1,142 @@
+use core::slice;
+
+use core_io::{Error as IoError, ErrorKind as IoErrorKind};
+use crc;
+use io::{proto::{ProtoRead, ProtoWrite},
+         Cursor};
+use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
+
+pub use crate::drtioaux_proto::Packet;
+use crate::{drtioaux_proto::Error as ProtocolError, mem::mem::DRTIOAUX_MEM, pl::csr::DRTIOAUX};
+
+#[derive(Debug)]
+pub enum Error {
+    GatewareError,
+    CorruptedPacket,
+
+    LinkDown,
+    TimedOut,
+    UnexpectedReply,
+
+    RoutingError,
+
+    Protocol(ProtocolError),
+}
+
+impl From<ProtocolError> for Error {
+    fn from(value: ProtocolError) -> Error {
+        Error::Protocol(value)
+    }
+}
+
+impl From<IoError> for Error {
+    fn from(value: IoError) -> Error {
+        Error::Protocol(ProtocolError::Io(value))
+    }
+}
+
+pub fn reset(linkno: u8) {
+    let linkno = linkno as usize;
+    unsafe {
+        // clear buffer first to limit race window with buffer overflow
+        // error. We assume the CPU is fast enough so that no two packets
+        // will be received between the buffer and the error flag are cleared.
+        (DRTIOAUX[linkno].aux_rx_present_write)(1);
+        (DRTIOAUX[linkno].aux_rx_error_write)(1);
+    }
+}
+
+pub fn has_rx_error(linkno: u8) -> bool {
+    let linkno = linkno as usize;
+    unsafe {
+        let error = (DRTIOAUX[linkno].aux_rx_error_read)() != 0;
+        if error {
+            (DRTIOAUX[linkno].aux_rx_error_write)(1)
+        }
+        error
+    }
+}
+
+fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
+where F: FnOnce(&[u8]) -> Result<T, Error> {
+    let linkidx = linkno as usize;
+    unsafe {
+        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
+            let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
+            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
+            let result = f(slice::from_raw_parts(ptr as *mut u8, 0x400 as usize));
+            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
+            Ok(Some(result?))
+        } else {
+            Ok(None)
+        }
+    }
+}
+
+pub fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
+    if has_rx_error(linkno) {
+        return Err(Error::GatewareError);
+    }
+
+    receive(linkno, |buffer| {
+        if buffer.len() < 8 {
+            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into());
+        }
+
+        let mut reader = Cursor::new(buffer);
+
+        let packet = Packet::read_from(&mut reader)?;
+        let padding = (12 - (reader.position() % 8)) % 8;
+        let checksum_at = reader.position() + padding;
+        let checksum = crc::crc32::checksum_ieee(&reader.get_ref()[0..checksum_at]);
+        reader.set_position(checksum_at);
+        if reader.read_u32()? != checksum {
+            return Err(Error::CorruptedPacket);
+        }
+        Ok(packet)
+    })
+}
+
+pub fn recv_timeout(linkno: u8, timeout_ms: Option<u64>, timer: GlobalTimer) -> Result<Packet, Error> {
+    let timeout_ms = Milliseconds(timeout_ms.unwrap_or(10));
+    let limit = timer.get_time() + timeout_ms;
+    while timer.get_time() < limit {
+        match recv(linkno)? {
+            None => (),
+            Some(packet) => return Ok(packet),
+        }
+    }
+    Err(Error::TimedOut)
+}
+
+fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
+where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
+    let linkno = linkno as usize;
+    unsafe {
+        while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
+        let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
+        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
+        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
+        (DRTIOAUX[linkno].aux_tx_write)(1);
+        Ok(())
+    }
+}
+
+pub fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
+    transmit(linkno, |buffer| {
+        let mut writer = Cursor::new(buffer);
+
+        packet.write_to(&mut writer)?;
+
+        // Pad till offset 4, insert checksum there
+        let padding = (12 - (writer.position() % 8)) % 8;
+        for _ in 0..padding {
+            writer.write_u8(0)?;
+        }
+
+        let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
+        writer.write_u32(checksum)?;
+
+        Ok(writer.position())
+    })
+}

src/libboard_artiq/src/drtioaux_async.rs

@@ -0,0 +1,130 @@
+use core::slice;
+
+use core_io::{Error as IoError, ErrorKind as IoErrorKind};
+use crc;
+use io::{proto::{ProtoRead, ProtoWrite},
+         Cursor};
+use libasync::{block_async, task};
+use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
+use nb;
+use void::Void;
+
+pub use crate::drtioaux_proto::Packet;
+use crate::{drtioaux::{has_rx_error, Error},
+            mem::mem::DRTIOAUX_MEM,
+            pl::csr::DRTIOAUX};
+
+pub async fn reset(linkno: u8) {
+    let linkno = linkno as usize;
+    unsafe {
+        // clear buffer first to limit race window with buffer overflow
+        // error. We assume the CPU is fast enough so that no two packets
+        // will be received between the buffer and the error flag are cleared.
+        (DRTIOAUX[linkno].aux_rx_present_write)(1);
+        (DRTIOAUX[linkno].aux_rx_error_write)(1);
+    }
+}
+
+fn tx_ready(linkno: usize) -> nb::Result<(), Void> {
+    unsafe {
+        if (DRTIOAUX[linkno].aux_tx_read)() != 0 {
+            Err(nb::Error::WouldBlock)
+        } else {
+            Ok(())
+        }
+    }
+}
+
+async fn receive<F, T>(linkno: u8, f: F) -> Result<Option<T>, Error>
+where F: FnOnce(&[u8]) -> Result<T, Error> {
+    let linkidx = linkno as usize;
+    unsafe {
+        if (DRTIOAUX[linkidx].aux_rx_present_read)() == 1 {
+            let read_ptr = (DRTIOAUX[linkidx].aux_read_pointer_read)() as usize;
+            let ptr = (DRTIOAUX_MEM[linkidx].base + DRTIOAUX_MEM[linkidx].size / 2 + read_ptr * 0x400) as *mut u32;
+            let result = f(slice::from_raw_parts(ptr as *mut u8, 0x400 as usize));
+            (DRTIOAUX[linkidx].aux_rx_present_write)(1);
+            Ok(Some(result?))
+        } else {
+            Ok(None)
+        }
+    }
+}
+
+pub async fn recv(linkno: u8) -> Result<Option<Packet>, Error> {
+    if has_rx_error(linkno) {
+        return Err(Error::GatewareError);
+    }
+
+    receive(linkno, |buffer| {
+        if buffer.len() < 8 {
+            return Err(IoError::new(IoErrorKind::UnexpectedEof, "Unexpected end").into());
+        }
+
+        let mut reader = Cursor::new(buffer);
+
+        let packet = Packet::read_from(&mut reader)?;
+        let padding = (12 - (reader.position() % 8)) % 8;
+        let checksum_at = reader.position() + padding;
+        let checksum = crc::crc32::checksum_ieee(&reader.get_ref()[0..checksum_at]);
+        reader.set_position(checksum_at);
+        if reader.read_u32()? != checksum {
+            return Err(Error::CorruptedPacket);
+        }
+        Ok(packet)
+    })
+    .await
+}
+
+pub async fn recv_timeout(linkno: u8, timeout_ms: Option<u64>, timer: GlobalTimer) -> Result<Packet, Error> {
+    let timeout_ms = Milliseconds(timeout_ms.unwrap_or(10));
+    let limit = timer.get_time() + timeout_ms;
+    let mut would_block = false;
+    while timer.get_time() < limit {
+        // to ensure one last time recv would run one last time
+        // in case async would return after timeout
+        if would_block {
+            task::r#yield().await;
+        }
+        match recv(linkno).await? {
+            None => {
+                would_block = true;
+            }
+            Some(packet) => return Ok(packet),
+        }
+    }
+    Err(Error::TimedOut)
+}
+
+async fn transmit<F>(linkno: u8, f: F) -> Result<(), Error>
+where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
+    let linkno = linkno as usize;
+    unsafe {
+        let _ = block_async!(tx_ready(linkno)).await;
+        let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
+        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
+        (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
+        (DRTIOAUX[linkno].aux_tx_write)(1);
+        Ok(())
+    }
+}
+
+pub async fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
+    transmit(linkno, |buffer| {
+        let mut writer = Cursor::new(buffer);
+
+        packet.write_to(&mut writer)?;
+
+        // Pad till offset 4, insert checksum there
+        let padding = (12 - (writer.position() % 8)) % 8;
+        for _ in 0..padding {
+            writer.write_u8(0)?;
+        }
+
+        let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);
+        writer.write_u32(checksum)?;
+
+        Ok(writer.position())
+    })
+    .await
+}

src/libboard_artiq/src/fiq.rs

@@ -0,0 +1,22 @@
+use libboard_zynq::{println, stdio};
+use libcortex_a9::{interrupt_handler, regs::MPIDR};
+use libregister::RegisterR;
+
+#[cfg(has_si549)]
+use crate::si549;
+
+interrupt_handler!(FIQ, fiq, __irq_stack0_start, __irq_stack1_start, {
+    match MPIDR.read().cpu_id() {
+        0 => {
+            // nFIQ is driven directly and bypass GIC
+            #[cfg(has_si549)]
+            si549::wrpll::interrupt_handler();
+            return;
+        }
+        _ => {}
+    };
+
+    stdio::drop_uart();
+    println!("FIQ");
+    loop {}
+});

src/libboard_artiq/src/grabber.rs

@@ -0,0 +1,163 @@
+use log::info;
+
+use crate::pl::csr;
+
+#[derive(PartialEq, Clone, Copy)]
+enum State {
+    Reset,
+    ExitReset,
+    Lock,
+    Align,
+    Watch,
+}
+
+#[derive(Clone, Copy)]
+struct Info {
+    state: State,
+    frame_size: (u16, u16),
+}
+
+static mut INFO: [Info; csr::GRABBER_LEN] = [Info {
+    state: State::Reset,
+    frame_size: (0, 0),
+}; csr::GRABBER_LEN];
+
+fn get_pll_reset(g: usize) -> bool {
+    unsafe { (csr::GRABBER[g].pll_reset_read)() != 0 }
+}
+
+fn set_pll_reset(g: usize, reset: bool) {
+    let val = if reset { 1 } else { 0 };
+    unsafe { (csr::GRABBER[g].pll_reset_write)(val) }
+}
+
+fn pll_locked(g: usize) -> bool {
+    unsafe { (csr::GRABBER[g].pll_locked_read)() != 0 }
+}
+
+fn clock_pattern_ok(g: usize) -> bool {
+    unsafe { (csr::GRABBER[g].clk_sampled_read)() == 0b1100011 }
+}
+
+fn clock_pattern_ok_filter(g: usize) -> bool {
+    for _ in 0..128 {
+        if !clock_pattern_ok(g) {
+            return false;
+        }
+    }
+    true
+}
+
+fn phase_shift(g: usize, direction: u8) {
+    unsafe {
+        (csr::GRABBER[g].phase_shift_write)(direction);
+        while (csr::GRABBER[g].phase_shift_done_read)() == 0 {}
+    }
+}
+
+fn clock_align(g: usize) -> bool {
+    while clock_pattern_ok_filter(g) {
+        phase_shift(g, 1);
+    }
+    phase_shift(g, 1);
+
+    let mut count = 0;
+    while !clock_pattern_ok_filter(g) {
+        phase_shift(g, 1);
+        count += 1;
+        if count > 1024 {
+            return false;
+        }
+    }
+
+    let mut window = 1;
+    phase_shift(g, 1);
+    while clock_pattern_ok_filter(g) {
+        phase_shift(g, 1);
+        window += 1;
+    }
+
+    for _ in 0..window / 2 {
+        phase_shift(g, 0);
+    }
+
+    true
+}
+
+fn get_last_pixels(g: usize) -> (u16, u16) {
+    unsafe { ((csr::GRABBER[g].last_x_read)(), (csr::GRABBER[g].last_y_read)()) }
+}
+
+fn get_video_clock(g: usize) -> u32 {
+    let freq_count = unsafe { (csr::GRABBER[g].freq_count_read)() } as u32;
+    2 * freq_count * (csr::CONFIG_CLOCK_FREQUENCY / 1000) / (511 * 1000)
+}
+
+pub fn tick() {
+    for g in 0..csr::GRABBER.len() {
+        let next = match unsafe { INFO[g].state } {
+            State::Reset => {
+                set_pll_reset(g, true);
+                unsafe {
+                    INFO[g].frame_size = (0, 0);
+                }
+                State::ExitReset
+            }
+            State::ExitReset => {
+                if get_pll_reset(g) {
+                    set_pll_reset(g, false);
+                    State::Lock
+                } else {
+                    State::ExitReset
+                }
+            }
+            State::Lock => {
+                if pll_locked(g) {
+                    info!("grabber{} locked: {}MHz", g, get_video_clock(g));
+                    State::Align
+                } else {
+                    State::Lock
+                }
+            }
+            State::Align => {
+                if pll_locked(g) {
+                    if clock_align(g) {
+                        info!("grabber{} alignment success", g);
+                        State::Watch
+                    } else {
+                        info!("grabber{} alignment failure", g);
+                        State::Reset
+                    }
+                } else {
+                    info!("grabber{} lock lost", g);
+                    State::Reset
+                }
+            }
+            State::Watch => {
+                if pll_locked(g) {
+                    if clock_pattern_ok(g) {
+                        let last_xy = get_last_pixels(g);
+                        if last_xy != unsafe { INFO[g].frame_size } {
+                            // x capture is on ~LVAL which is after
+                            // the last increment on DVAL
+                            // y capture is on ~FVAL which coincides with the
+                            // last increment on ~LVAL
+                            info!("grabber{} frame size: {}x{}", g, last_xy.0, last_xy.1 + 1);
+                            unsafe { INFO[g].frame_size = last_xy }
+                        }
+                        State::Watch
+                    } else {
+                        info!("grabber{} alignment lost", g);
+                        State::Reset
+                    }
+                } else {
+                    info!("grabber{} lock lost", g);
+                    State::Reset
+                }
+            }
+        };
+        unsafe {
+            INFO[g].state = next;
+        }
+    }
+}

src/libboard_artiq/src/io_expander.rs

@@ -0,0 +1,183 @@
+use libboard_zynq::i2c;
+use log::info;
+
+#[cfg(has_virtual_leds)]
+use crate::pl::csr;
+
+// Only the bare minimum registers. Bits/IO connections equivalent between IC types.
+struct Registers {
+    // PCA9539 equivalent register names in comments
+    iodira: u8, // Configuration Port 0
+    iodirb: u8, // Configuration Port 1
+    gpioa: u8,  // Output Port 0
+    gpiob: u8,  // Output Port 1
+}
+
+//IO expanders pins
+const IODIR_OUT_SFP_TX_DISABLE: u8 = 0x02;
+const IODIR_OUT_SFP_LED: u8 = 0x40;
+#[cfg(hw_rev = "v1.0")]
+const IODIR_OUT_SFP0_LED: u8 = 0x40;
+#[cfg(hw_rev = "v1.1")]
+const IODIR_OUT_SFP0_LED: u8 = 0x80;
+#[cfg(has_si549)]
+const IODIR_CLK_SEL: u8 = 0x80; // out
+#[cfg(has_si5324)]
+const IODIR_CLK_SEL: u8 = 0x00; // in
+
+//IO expander port direction
+const IODIR0: [u8; 2] = [
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP0_LED,
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED & !IODIR_CLK_SEL,
+];
+
+const IODIR1: [u8; 2] = [
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
+    0xFF & !IODIR_OUT_SFP_TX_DISABLE & !IODIR_OUT_SFP_LED,
+];
+
+pub struct IoExpander {
+    address: u8,
+    #[cfg(has_virtual_leds)]
+    virtual_led_mapping: &'static [(u8, u8, u8)],
+    iodir: [u8; 2],
+    out_current: [u8; 2],
+    out_target: [u8; 2],
+    registers: Registers,
+}
+
+impl IoExpander {
+    pub fn new(i2c: &mut i2c::I2c, index: u8) -> Result<Self, &'static str> {
+        #[cfg(all(hw_rev = "v1.0", has_virtual_leds))]
+        const VIRTUAL_LED_MAPPING0: [(u8, u8, u8); 2] = [(0, 0, 6), (1, 1, 6)];
+        #[cfg(all(hw_rev = "v1.1", has_virtual_leds))]
+        const VIRTUAL_LED_MAPPING0: [(u8, u8, u8); 2] = [(0, 0, 7), (1, 1, 6)];
+        #[cfg(has_virtual_leds)]
+        const VIRTUAL_LED_MAPPING1: [(u8, u8, u8); 2] = [(2, 0, 6), (3, 1, 6)];
+
+        // Both expanders on SHARED I2C bus
+        let mut io_expander = match index {
+            0 => IoExpander {
+                address: 0x40,
+                #[cfg(has_virtual_leds)]
+                virtual_led_mapping: &VIRTUAL_LED_MAPPING0,
+                iodir: IODIR0,
+                out_current: [0; 2],
+                out_target: [0; 2],
+                registers: Registers {
+                    iodira: 0x00,
+                    iodirb: 0x01,
+                    gpioa: 0x12,
+                    gpiob: 0x13,
+                },
+            },
+            1 => IoExpander {
+                address: 0x42,
+                #[cfg(has_virtual_leds)]
+                virtual_led_mapping: &VIRTUAL_LED_MAPPING1,
+                iodir: IODIR1,
+                out_current: [0; 2],
+                out_target: [0; 2],
+                registers: Registers {
+                    iodira: 0x00,
+                    iodirb: 0x01,
+                    gpioa: 0x12,
+                    gpiob: 0x13,
+                },
+            },
+            _ => return Err("incorrect I/O expander index"),
+        };
+        if !io_expander.check_ack(i2c)? {
+            info!("MCP23017 io expander {} not found. Checking for PCA9539.", index);
+            io_expander.address += 0xa8; // translate to PCA9539 addresses (see schematic)
+            io_expander.registers = Registers {
+                iodira: 0x06,
+                iodirb: 0x07,
+                gpioa: 0x02,
+                gpiob: 0x03,
+            };
+            if !io_expander.check_ack(i2c)? {
+                return Err("Neither MCP23017 nor PCA9539 io expander found.");
+            };
+        }
+        Ok(io_expander)
+    }
+
+    fn select(&self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
+        i2c.pca954x_select(0x70, None)?;
+        i2c.pca954x_select(0x71, Some(3))?;
+        Ok(())
+    }
+
+    fn write(&self, i2c: &mut i2c::I2c, addr: u8, value: u8) -> Result<(), &'static str> {
+        i2c.start()?;
+        i2c.write(self.address)?;
+        i2c.write(addr)?;
+        i2c.write(value)?;
+        i2c.stop()?;
+        Ok(())
+    }
+
+    fn check_ack(&self, i2c: &mut i2c::I2c) -> Result<bool, &'static str> {
+        // Check for ack from io expander
+        self.select(i2c)?;
+        i2c.start()?;
+        let ack = i2c.write(self.address)?;
+        i2c.stop()?;
+        Ok(ack)
+    }
+
+    fn update_iodir(&self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
+        self.write(i2c, self.registers.iodira, self.iodir[0])?;
+        self.write(i2c, self.registers.iodirb, self.iodir[1])?;
+        Ok(())
+    }
+
+    pub fn init(&mut self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
+        self.select(i2c)?;
+
+        self.update_iodir(i2c)?;
+
+        self.out_current[0] = 0x00;
+        self.write(i2c, self.registers.gpioa, 0x00)?;
+        self.out_current[1] = 0x00;
+        self.write(i2c, self.registers.gpiob, 0x00)?;
+        Ok(())
+    }
+
+    pub fn set_oe(&mut self, i2c: &mut i2c::I2c, port: u8, outputs: u8) -> Result<(), &'static str> {
+        self.iodir[port as usize] &= !outputs;
+        self.update_iodir(i2c)?;
+        Ok(())
+    }
+
+    pub fn set(&mut self, port: u8, bit: u8, high: bool) {
+        if high {
+            self.out_target[port as usize] |= 1 << bit;
+        } else {
+            self.out_target[port as usize] &= !(1 << bit);
+        }
+    }
+
+    pub fn service(&mut self, i2c: &mut i2c::I2c) -> Result<(), &'static str> {
+        #[cfg(has_virtual_leds)]
+        for (led, port, bit) in self.virtual_led_mapping.iter() {
+            let level = unsafe { csr::virtual_leds::status_read() >> led & 1 };
+            self.set(*port, *bit, level != 0);
+        }
+
+        if self.out_target != self.out_current {
+            self.select(i2c)?;
+            if self.out_target[0] != self.out_current[0] {
+                self.write(i2c, self.registers.gpioa, self.out_target[0])?;
+                self.out_current[0] = self.out_target[0];
+            }
+            if self.out_target[1] != self.out_current[1] {
+                self.write(i2c, self.registers.gpiob, self.out_target[1])?;
+                self.out_current[1] = self.out_target[1];
+            }
+        }
+
+        Ok(())
+    }
+}

src/libboard_artiq/src/lib.rs

@@ -0,0 +1,56 @@
+#![no_std]
+#![feature(never_type)]
+#![feature(naked_functions)]
+#![feature(asm)]
+
+extern crate core_io;
+extern crate crc;
+extern crate embedded_hal;
+extern crate io;
+extern crate libasync;
+extern crate libboard_zynq;
+extern crate libconfig;
+extern crate libcortex_a9;
+extern crate libregister;
+extern crate log;
+extern crate log_buffer;
+
+pub mod drtio_routing;
+#[cfg(has_drtio)]
+pub mod drtioaux;
+#[cfg(has_drtio)]
+pub mod drtioaux_async;
+pub mod drtioaux_proto;
+pub mod fiq;
+#[cfg(feature = "target_kasli_soc")]
+pub mod io_expander;
+pub mod logger;
+#[cfg(has_drtio)]
+#[rustfmt::skip]
+#[path = "../../../build/mem.rs"]
+pub mod mem;
+#[rustfmt::skip]
+#[path = "../../../build/pl.rs"]
+pub mod pl;
+#[cfg(has_drtio_eem)]
+pub mod drtio_eem;
+#[cfg(has_grabber)]
+pub mod grabber;
+#[cfg(has_si5324)]
+pub mod si5324;
+#[cfg(has_si549)]
+pub mod si549;
+use core::{cmp, str};
+
+pub fn identifier_read(buf: &mut [u8]) -> &str {
+    unsafe {
+        pl::csr::identifier::address_write(0);
+        let len = pl::csr::identifier::data_read();
+        let len = cmp::min(len, buf.len() as u8);
+        for i in 0..len {
+            pl::csr::identifier::address_write(1 + i);
+            buf[i as usize] = pl::csr::identifier::data_read();
+        }
+        str::from_utf8_unchecked(&buf[..len as usize])
+    }
+}

src/libboard_artiq/src/logger.rs

@@ -0,0 +1,131 @@
+use core::{cell::Cell, fmt::Write};
+
+use libboard_zynq::{println, timer::GlobalTimer};
+use libcortex_a9::mutex::{Mutex, MutexGuard};
+use log::{LevelFilter, Log};
+use log_buffer::LogBuffer;
+
+pub struct LogBufferRef<'a> {
+    buffer: MutexGuard<'a, LogBuffer<&'static mut [u8]>>,
+    old_log_level: LevelFilter,
+}
+
+impl<'a> LogBufferRef<'a> {
+    fn new(buffer: MutexGuard<'a, LogBuffer<&'static mut [u8]>>) -> LogBufferRef<'a> {
+        let old_log_level = log::max_level();
+        log::set_max_level(LevelFilter::Off);
+        LogBufferRef { buffer, old_log_level }
+    }
+
+    pub fn is_empty(&self) -> bool {
+        self.buffer.is_empty()
+    }
+
+    pub fn clear(&mut self) {
+        self.buffer.clear()
+    }
+
+    pub fn extract(&mut self) -> &str {
+        self.buffer.extract()
+    }
+}
+
+impl<'a> Drop for LogBufferRef<'a> {
+    fn drop(&mut self) {
+        log::set_max_level(self.old_log_level)
+    }
+}
+
+pub struct BufferLogger {
+    buffer: Mutex<LogBuffer<&'static mut [u8]>>,
+    uart_filter: Cell<LevelFilter>,
+    buffer_filter: Cell<LevelFilter>,
+}
+
+static mut LOGGER: Option<BufferLogger> = None;
+
+impl BufferLogger {
+    pub fn new(buffer: &'static mut [u8]) -> BufferLogger {
+        BufferLogger {
+            buffer: Mutex::new(LogBuffer::new(buffer)),
+            uart_filter: Cell::new(LevelFilter::Info),
+            buffer_filter: Cell::new(LevelFilter::Trace),
+        }
+    }
+
+    pub fn register(self) {
+        unsafe {
+            LOGGER = Some(self);
+            log::set_logger(LOGGER.as_ref().unwrap()).expect("global logger can only be initialized once");
+        }
+    }
+
+    pub unsafe fn get_logger() -> &'static mut Option<BufferLogger> {
+        &mut LOGGER
+    }
+
+    pub fn buffer<'a>(&'a self) -> Option<LogBufferRef<'a>> {
+        self.buffer.try_lock().map(LogBufferRef::new)
+    }
+
+    pub fn uart_log_level(&self) -> LevelFilter {
+        self.uart_filter.get()
+    }
+
+    pub fn set_uart_log_level(&self, max_level: LevelFilter) {
+        self.uart_filter.set(max_level)
+    }
+
+    pub fn buffer_log_level(&self) -> LevelFilter {
+        self.buffer_filter.get()
+    }
+
+    /// this should be reserved for mgmt module
+    pub fn set_buffer_log_level(&self, max_level: LevelFilter) {
+        self.buffer_filter.set(max_level)
+    }
+}
+
+// required for impl Log
+unsafe impl Sync for BufferLogger {}
+
+impl Log for BufferLogger {
+    fn enabled(&self, _metadata: &log::Metadata) -> bool {
+        true
+    }
+
+    fn log(&self, record: &log::Record) {
+        if self.enabled(record.metadata()) {
+            let timestamp = unsafe { GlobalTimer::get() }.get_us().0;
+            let seconds = timestamp / 1_000_000;
+            let micros = timestamp % 1_000_000;
+
+            if record.level() <= self.buffer_log_level() {
+                let mut buffer = self.buffer.lock();
+                writeln!(
+                    buffer,
+                    "[{:6}.{:06}s] {:>5}({}): {}",
+                    seconds,
+                    micros,
+                    record.level(),
+                    record.target(),
+                    record.args()
+                )
+                .unwrap();
+            }
+
+            if record.level() <= self.uart_log_level() {
+                println!(
+                    "[{:6}.{:06}s] {:>5}({}): {}",
+                    seconds,
+                    micros,
+                    record.level(),
+                    record.target(),
+                    record.args()
+                );
+            }
+        }
+    }
+
+    fn flush(&self) {}
+}

src/libboard_artiq/src/si5324.rs

@@ -0,0 +1,362 @@
+use core::result;
+
+use embedded_hal::blocking::delay::DelayUs;
+use libboard_zynq::{i2c::I2c, time::Milliseconds, timer::GlobalTimer};
+use log::info;
+
+#[cfg(not(si5324_soft_reset))]
+use crate::pl::csr;
+
+type Result<T> = result::Result<T, &'static str>;
+
+const ADDRESS: u8 = 0x68;
+
+#[cfg(not(si5324_soft_reset))]
+fn hard_reset(timer: &mut GlobalTimer) {
+    unsafe {
+        csr::si5324_rst_n::out_write(0);
+    }
+    timer.delay_us(1_000);
+    unsafe {
+        csr::si5324_rst_n::out_write(1);
+    }
+    timer.delay_us(10_000);
+}
+
+// NOTE: the logical parameters DO NOT MAP to physical values written
+// into registers. They have to be mapped; see the datasheet.
+// DSPLLsim reports the logical parameters in the design summary, not
+// the physical register values.
+pub struct FrequencySettings {
+    pub n1_hs: u8,
+    pub nc1_ls: u32,
+    pub n2_hs: u8,
+    pub n2_ls: u32,
+    pub n31: u32,
+    pub n32: u32,
+    pub bwsel: u8,
+    pub crystal_as_ckin2: bool,
+}
+
+pub enum Input {
+    Ckin1,
+    Ckin2,
+}
+
+fn map_frequency_settings(settings: &FrequencySettings) -> Result<FrequencySettings> {
+    if settings.nc1_ls != 0 && (settings.nc1_ls % 2) == 1 {
+        return Err("NC1_LS must be 0 or even");
+    }
+    if settings.nc1_ls > (1 << 20) {
+        return Err("NC1_LS is too high");
+    }
+    if (settings.n2_ls % 2) == 1 {
+        return Err("N2_LS must be even");
+    }
+    if settings.n2_ls > (1 << 20) {
+        return Err("N2_LS is too high");
+    }
+    if settings.n31 > (1 << 19) {
+        return Err("N31 is too high");
+    }
+    if settings.n32 > (1 << 19) {
+        return Err("N32 is too high");
+    }
+    let r = FrequencySettings {
+        n1_hs: match settings.n1_hs {
+            4 => 0b000,
+            5 => 0b001,
+            6 => 0b010,
+            7 => 0b011,
+            8 => 0b100,
+            9 => 0b101,
+            10 => 0b110,
+            11 => 0b111,
+            _ => return Err("N1_HS has an invalid value"),
+        },
+        nc1_ls: settings.nc1_ls - 1,
+        n2_hs: match settings.n2_hs {
+            4 => 0b000,
+            5 => 0b001,
+            6 => 0b010,
+            7 => 0b011,
+            8 => 0b100,
+            9 => 0b101,
+            10 => 0b110,
+            11 => 0b111,
+            _ => return Err("N2_HS has an invalid value"),
+        },
+        n2_ls: settings.n2_ls - 1,
+        n31: settings.n31 - 1,
+        n32: settings.n32 - 1,
+        bwsel: settings.bwsel,
+        crystal_as_ckin2: settings.crystal_as_ckin2,
+    };
+    Ok(r)
+}
+
+fn write(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
+    i2c.start().unwrap();
+    if !i2c.write(ADDRESS << 1).unwrap() {
+        return Err("Si5324 failed to ack write address");
+    }
+    if !i2c.write(reg).unwrap() {
+        return Err("Si5324 failed to ack register");
+    }
+    if !i2c.write(val).unwrap() {
+        return Err("Si5324 failed to ack value");
+    }
+    i2c.stop().unwrap();
+    Ok(())
+}
+
+#[allow(dead_code)]
+fn write_no_ack_value(i2c: &mut I2c, reg: u8, val: u8) -> Result<()> {
+    i2c.start().unwrap();
+    if !i2c.write(ADDRESS << 1).unwrap() {
+        return Err("Si5324 failed to ack write address");
+    }
+    if !i2c.write(reg).unwrap() {
+        return Err("Si5324 failed to ack register");
+    }
+    i2c.write(val).unwrap();
+    i2c.stop().unwrap();
+    Ok(())
+}
+
+fn read(i2c: &mut I2c, reg: u8) -> Result<u8> {
+    i2c.start().unwrap();
+    if !i2c.write(ADDRESS << 1).unwrap() {
+        return Err("Si5324 failed to ack write address");
+    }
+    if !i2c.write(reg).unwrap() {
+        return Err("Si5324 failed to ack register");
+    }
+    i2c.restart().unwrap();
+    if !i2c.write((ADDRESS << 1) | 1).unwrap() {
+        return Err("Si5324 failed to ack read address");
+    }
+    let val = i2c.read(false).unwrap();
+    i2c.stop().unwrap();
+    Ok(val)
+}
+
+fn rmw<F>(i2c: &mut I2c, reg: u8, f: F) -> Result<()>
+where F: Fn(u8) -> u8 {
+    let value = read(i2c, reg)?;
+    write(i2c, reg, f(value))?;
+    Ok(())
+}
+
+fn ident(i2c: &mut I2c) -> Result<u16> {
+    Ok(((read(i2c, 134)? as u16) << 8) | (read(i2c, 135)? as u16))
+}
+
+#[cfg(si5324_soft_reset)]
+fn soft_reset(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
+    let val = read(i2c, 136)?;
+    write_no_ack_value(i2c, 136, val | 0x80)?;
+    timer.delay_us(10_000);
+    Ok(())
+}
+
+fn has_xtal(i2c: &mut I2c) -> Result<bool> {
+    Ok((read(i2c, 129)? & 0x01) == 0) // LOSX_INT=0
+}
+
+fn has_ckin(i2c: &mut I2c, input: Input) -> Result<bool> {
+    match input {
+        Input::Ckin1 => Ok((read(i2c, 129)? & 0x02) == 0), // LOS1_INT=0
+        Input::Ckin2 => Ok((read(i2c, 129)? & 0x04) == 0), // LOS2_INT=0
+    }
+}
+
+fn locked(i2c: &mut I2c) -> Result<bool> {
+    Ok((read(i2c, 130)? & 0x01) == 0) // LOL_INT=0
+}
+
+fn monitor_lock(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
+    info!("waiting for Si5324 lock...");
+    let timeout = timer.get_time() + Milliseconds(20_000);
+    while !locked(i2c)? {
+        // Yes, lock can be really slow.
+        if timer.get_time() > timeout {
+            return Err("Si5324 lock timeout");
+        }
+    }
+    info!("  ...locked");
+    Ok(())
+}
+
+fn init(i2c: &mut I2c, timer: &mut GlobalTimer) -> Result<()> {
+    #[cfg(not(si5324_soft_reset))]
+    hard_reset(timer);
+
+    #[cfg(feature = "target_kasli_soc")]
+    {
+        i2c.pca954x_select(0x70, None)?;
+        i2c.pca954x_select(0x71, Some(3))?;
+    }
+    #[cfg(feature = "target_zc706")]
+    {
+        i2c.pca954x_select(0x74, Some(4))?;
+    }
+
+    if ident(i2c)? != 0x0182 {
+        return Err("Si5324 does not have expected product number");
+    }
+
+    #[cfg(si5324_soft_reset)]
+    soft_reset(i2c, timer)?;
+    Ok(())
+}
+
+pub fn bypass(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
+    let cksel_reg = match input {
+        Input::Ckin1 => 0b00,
+        Input::Ckin2 => 0b01,
+    };
+    init(i2c, timer)?;
+    rmw(i2c, 21, |v| v & 0xfe)?; // CKSEL_PIN=0
+    rmw(i2c, 3, |v| (v & 0x3f) | (cksel_reg << 6))?; // CKSEL_REG
+    rmw(i2c, 4, |v| (v & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
+    rmw(i2c, 6, |v| (v & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
+    rmw(i2c, 0, |v| (v & 0xfd) | 0x02)?; // BYPASS_REG=1
+    Ok(())
+}
+
+pub fn setup(i2c: &mut I2c, settings: &FrequencySettings, input: Input, timer: &mut GlobalTimer) -> Result<()> {
+    let s = map_frequency_settings(settings)?;
+    let cksel_reg = match input {
+        Input::Ckin1 => 0b00,
+        Input::Ckin2 => 0b01,
+    };
+
+    init(i2c, timer)?;
+    if settings.crystal_as_ckin2 {
+        rmw(i2c, 0, |v| v | 0x40)?; // FREE_RUN=1
+    }
+    rmw(i2c, 2, |v| (v & 0x0f) | (s.bwsel << 4))?;
+    rmw(i2c, 21, |v| v & 0xfe)?; // CKSEL_PIN=0
+    rmw(i2c, 3, |v| (v & 0x2f) | (cksel_reg << 6) | 0x10)?; // CKSEL_REG, SQ_ICAL=1
+    rmw(i2c, 4, |v| (v & 0x3f) | (0b00 << 6))?; // AUTOSEL_REG=b00
+    rmw(i2c, 6, |v| (v & 0xc0) | 0b111111)?; // SFOUT2_REG=b111 SFOUT1_REG=b111
+    write(i2c, 25, (s.n1_hs << 5) as u8)?;
+    write(i2c, 31, (s.nc1_ls >> 16) as u8)?;
+    write(i2c, 32, (s.nc1_ls >> 8) as u8)?;
+    write(i2c, 33, (s.nc1_ls) as u8)?;
+    write(i2c, 34, (s.nc1_ls >> 16) as u8)?; // write to NC2_LS as well
+    write(i2c, 35, (s.nc1_ls >> 8) as u8)?;
+    write(i2c, 36, (s.nc1_ls) as u8)?;
+    write(i2c, 40, (s.n2_hs << 5) as u8 | (s.n2_ls >> 16) as u8)?;
+    write(i2c, 41, (s.n2_ls >> 8) as u8)?;
+    write(i2c, 42, (s.n2_ls) as u8)?;
+    write(i2c, 43, (s.n31 >> 16) as u8)?;
+    write(i2c, 44, (s.n31 >> 8) as u8)?;
+    write(i2c, 45, (s.n31) as u8)?;
+    write(i2c, 46, (s.n32 >> 16) as u8)?;
+    write(i2c, 47, (s.n32 >> 8) as u8)?;
+    write(i2c, 48, (s.n32) as u8)?;
+    rmw(i2c, 137, |v| v | 0x01)?; // FASTLOCK=1
+    rmw(i2c, 136, |v| v | 0x40)?; // ICAL=1
+
+    if !has_xtal(i2c)? {
+        return Err("Si5324 misses XA/XB signal");
+    }
+    if !has_ckin(i2c, input)? {
+        return Err("Si5324 misses clock input signal");
+    }
+
+    monitor_lock(i2c, timer)?;
+    Ok(())
+}
+
+pub fn select_input(i2c: &mut I2c, input: Input, timer: &mut GlobalTimer) -> Result<()> {
+    let cksel_reg = match input {
+        Input::Ckin1 => 0b00,
+        Input::Ckin2 => 0b01,
+    };
+    rmw(i2c, 3, |v| (v & 0x3f) | (cksel_reg << 6))?;
+    if !has_ckin(i2c, input)? {
+        return Err("Si5324 misses clock input signal");
+    }
+    monitor_lock(i2c, timer)?;
+    Ok(())
+}
+
+#[cfg(has_siphaser)]
+pub mod siphaser {
+    use super::*;
+    use crate::pl::csr;
+
+    pub fn select_recovered_clock(i2c: &mut I2c, rc: bool, timer: &mut GlobalTimer) -> Result<()> {
+        let val = read(i2c, 3)?;
+        write(i2c, 3, (val & 0xdf) | (1 << 5))?; // DHOLD=1
+        unsafe {
+            csr::siphaser::switch_clocks_write(if rc { 1 } else { 0 });
+        }
+        let val = read(i2c, 3)?;
+        write(i2c, 3, (val & 0xdf) | (0 << 5))?; // DHOLD=0
+        monitor_lock(i2c, timer)?;
+        Ok(())
+    }
+
+    fn phase_shift(direction: u8, timer: &mut GlobalTimer) {
+        unsafe {
+            csr::siphaser::phase_shift_write(direction);
+            while csr::siphaser::phase_shift_done_read() == 0 {}
+        }
+        // wait for the Si5324 loop to stabilize
+        timer.delay_us(500);
+    }
+
+    fn has_error(timer: &mut GlobalTimer) -> bool {
+        unsafe {
+            csr::siphaser::error_write(1);
+        }
+        timer.delay_us(5_000);
+        unsafe { csr::siphaser::error_read() != 0 }
+    }
+
+    fn find_edge(target: bool, timer: &mut GlobalTimer) -> Result<u32> {
+        let mut nshifts = 0;
+
+        let mut previous = has_error(timer);
+        loop {
+            phase_shift(1, timer);
+            nshifts += 1;
+            let current = has_error(timer);
+            if previous != target && current == target {
+                return Ok(nshifts);
+            }
+            if nshifts > 5000 {
+                return Err("failed to find timing error edge");
+            }
+            previous = current;
+        }
+    }
+
+    pub fn calibrate_skew(timer: &mut GlobalTimer) -> Result<()> {
+        let jitter_margin = 32;
+        let lead = find_edge(false, timer)?;
+        for _ in 0..jitter_margin {
+            phase_shift(1, timer);
+        }
+        let width = find_edge(true, timer)? + jitter_margin;
+        // width is 360 degrees (one full rotation of the phase between s/h limits) minus jitter
+        info!(
+            "calibration successful, lead: {}, width: {} ({}deg)",
+            lead,
+            width,
+            width * 360 / (56 * 8)
+        );
+
+        // Apply reverse phase shift for half the width to get into the
+        // middle of the working region.
+        for _ in 0..width / 2 {
+            phase_shift(0, timer);
+        }
+
+        Ok(())
+    }
+}

src/libboard_artiq/src/si549.rs

@@ -0,0 +1,854 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::timer::GlobalTimer;
+use log::info;
+
+use crate::pl::csr;
+
+#[cfg(feature = "target_kasli_soc")]
+const ADDRESS: u8 = 0x67;
+
+const ADPLL_MAX: i32 = (950.0 / 0.0001164) as i32;
+
+pub struct DividerConfig {
+    pub hsdiv: u16,
+    pub lsdiv: u8,
+    pub fbdiv: u64,
+}
+
+pub struct FrequencySetting {
+    pub main: DividerConfig,
+    pub helper: DividerConfig,
+}
+
+mod i2c {
+    use super::*;
+
+    #[derive(Clone, Copy)]
+    pub enum DCXO {
+        Main,
+        Helper,
+    }
+
+    fn half_period(timer: &mut GlobalTimer) {
+        timer.delay_us(1)
+    }
+
+    fn sda_i(dcxo: DCXO) -> bool {
+        match dcxo {
+            DCXO::Main => unsafe { csr::wrpll::main_dcxo_sda_in_read() == 1 },
+            DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_sda_in_read() == 1 },
+        }
+    }
+
+    fn sda_oe(dcxo: DCXO, oe: bool) {
+        let val = if oe { 1 } else { 0 };
+        match dcxo {
+            DCXO::Main => unsafe { csr::wrpll::main_dcxo_sda_oe_write(val) },
+            DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_sda_oe_write(val) },
+        };
+    }
+
+    fn sda_o(dcxo: DCXO, o: bool) {
+        let val = if o { 1 } else { 0 };
+        match dcxo {
+            DCXO::Main => unsafe { csr::wrpll::main_dcxo_sda_out_write(val) },
+            DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_sda_out_write(val) },
+        };
+    }
+
+    fn scl_oe(dcxo: DCXO, oe: bool) {
+        let val = if oe { 1 } else { 0 };
+        match dcxo {
+            DCXO::Main => unsafe { csr::wrpll::main_dcxo_scl_oe_write(val) },
+            DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_scl_oe_write(val) },
+        };
+    }
+
+    fn scl_o(dcxo: DCXO, o: bool) {
+        let val = if o { 1 } else { 0 };
+        match dcxo {
+            DCXO::Main => unsafe { csr::wrpll::main_dcxo_scl_out_write(val) },
+            DCXO::Helper => unsafe { csr::wrpll::helper_dcxo_scl_out_write(val) },
+        };
+    }
+
+    pub fn init(dcxo: DCXO, timer: &mut GlobalTimer) -> Result<(), &'static str> {
+        // Set SCL as output, and high level
+        scl_o(dcxo, true);
+        scl_oe(dcxo, true);
+        // Prepare a zero level on SDA so that sda_oe pulls it down
+        sda_o(dcxo, false);
+        // Release SDA
+        sda_oe(dcxo, false);
+
+        // Check the I2C bus is ready
+        half_period(timer);
+        half_period(timer);
+        if !sda_i(dcxo) {
+            // Try toggling SCL a few times
+            for _bit in 0..8 {
+                scl_o(dcxo, false);
+                half_period(timer);
+                scl_o(dcxo, true);
+                half_period(timer);
+            }
+        }
+
+        if !sda_i(dcxo) {
+            return Err("SDA is stuck low and doesn't get unstuck");
+        }
+        Ok(())
+    }
+
+    pub fn start(dcxo: DCXO, timer: &mut GlobalTimer) {
+        // Set SCL high then SDA low
+        scl_o(dcxo, true);
+        half_period(timer);
+        sda_oe(dcxo, true);
+        half_period(timer);
+    }
+
+    pub fn stop(dcxo: DCXO, timer: &mut GlobalTimer) {
+        // First, make sure SCL is low, so that the target releases the SDA line
+        scl_o(dcxo, false);
+        half_period(timer);
+        // Set SCL high then SDA high
+        sda_oe(dcxo, true);
+        scl_o(dcxo, true);
+        half_period(timer);
+        sda_oe(dcxo, false);
+        half_period(timer);
+    }
+
+    pub fn write(dcxo: DCXO, data: u8, timer: &mut GlobalTimer) -> bool {
+        // MSB first
+        for bit in (0..8).rev() {
+            // Set SCL low and set our bit on SDA
+            scl_o(dcxo, false);
+            sda_oe(dcxo, data & (1 << bit) == 0);
+            half_period(timer);
+            // Set SCL high ; data is shifted on the rising edge of SCL
+            scl_o(dcxo, true);
+            half_period(timer);
+        }
+        // Check ack
+        // Set SCL low, then release SDA so that the I2C target can respond
+        scl_o(dcxo, false);
+        half_period(timer);
+        sda_oe(dcxo, false);
+        // Set SCL high and check for ack
+        scl_o(dcxo, true);
+        half_period(timer);
+        // returns true if acked (I2C target pulled SDA low)
+        !sda_i(dcxo)
+    }
+
+    pub fn read(dcxo: DCXO, ack: bool, timer: &mut GlobalTimer) -> u8 {
+        // Set SCL low first, otherwise setting SDA as input may cause a transition
+        // on SDA with SCL high which will be interpreted as START/STOP condition.
+        scl_o(dcxo, false);
+        half_period(timer); // make sure SCL has settled low
+        sda_oe(dcxo, false);
+
+        let mut data: u8 = 0;
+
+        // MSB first
+        for bit in (0..8).rev() {
+            scl_o(dcxo, false);
+            half_period(timer);
+            // Set SCL high and shift data
+            scl_o(dcxo, true);
+            half_period(timer);
+            if sda_i(dcxo) {
+                data |= 1 << bit
+            }
+        }
+        // Send ack
+        // Set SCL low and pull SDA low when acking
+        scl_o(dcxo, false);
+        if ack {
+            sda_oe(dcxo, true)
+        }
+        half_period(timer);
+        // then set SCL high
+        scl_o(dcxo, true);
+        half_period(timer);
+
+        data
+    }
+}
+
+fn write(dcxo: i2c::DCXO, reg: u8, val: u8, timer: &mut GlobalTimer) -> Result<(), &'static str> {
+    i2c::start(dcxo, timer);
+    if !i2c::write(dcxo, ADDRESS << 1, timer) {
+        return Err("Si549 failed to ack write address");
+    }
+    if !i2c::write(dcxo, reg, timer) {
+        return Err("Si549 failed to ack register");
+    }
+    if !i2c::write(dcxo, val, timer) {
+        return Err("Si549 failed to ack value");
+    }
+    i2c::stop(dcxo, timer);
+    Ok(())
+}
+
+fn read(dcxo: i2c::DCXO, reg: u8, timer: &mut GlobalTimer) -> Result<u8, &'static str> {
+    i2c::start(dcxo, timer);
+    if !i2c::write(dcxo, ADDRESS << 1, timer) {
+        return Err("Si549 failed to ack write address");
+    }
+    if !i2c::write(dcxo, reg, timer) {
+        return Err("Si549 failed to ack register");
+    }
+    i2c::stop(dcxo, timer);
+
+    i2c::start(dcxo, timer);
+    if !i2c::write(dcxo, (ADDRESS << 1) | 1, timer) {
+        return Err("Si549 failed to ack read address");
+    }
+    let val = i2c::read(dcxo, false, timer);
+    i2c::stop(dcxo, timer);
+    Ok(val)
+}
+
+fn setup(dcxo: i2c::DCXO, config: &DividerConfig, timer: &mut GlobalTimer) -> Result<(), &'static str> {
+    i2c::init(dcxo, timer)?;
+
+    write(dcxo, 255, 0x00, timer)?; // PAGE
+    write(dcxo, 69, 0x00, timer)?; // Disable FCAL override.
+    write(dcxo, 17, 0x00, timer)?; // Synchronously disable output
+
+    // The Si549 has no ID register, so we check that it responds correctly
+    // by writing values to a RAM-like register and reading them back.
+    for test_value in 0..255 {
+        write(dcxo, 23, test_value, timer)?;
+        let readback = read(dcxo, 23, timer)?;
+        if readback != test_value {
+            return Err("Si549 detection failed");
+        }
+    }
+
+    write(dcxo, 23, config.hsdiv as u8, timer)?;
+    write(dcxo, 24, (config.hsdiv >> 8) as u8 | (config.lsdiv << 4), timer)?;
+    write(dcxo, 26, config.fbdiv as u8, timer)?;
+    write(dcxo, 27, (config.fbdiv >> 8) as u8, timer)?;
+    write(dcxo, 28, (config.fbdiv >> 16) as u8, timer)?;
+    write(dcxo, 29, (config.fbdiv >> 24) as u8, timer)?;
+    write(dcxo, 30, (config.fbdiv >> 32) as u8, timer)?;
+    write(dcxo, 31, (config.fbdiv >> 40) as u8, timer)?;
+
+    write(dcxo, 7, 0x08, timer)?; // Start FCAL
+    timer.delay_us(30_000); // Internal FCAL VCO calibration
+    write(dcxo, 17, 0x01, timer)?; // Synchronously enable output
+
+    Ok(())
+}
+
+pub fn main_setup(timer: &mut GlobalTimer, settings: &FrequencySetting) -> Result<(), &'static str> {
+    unsafe {
+        csr::wrpll::main_dcxo_bitbang_enable_write(1);
+        csr::wrpll::main_dcxo_i2c_address_write(ADDRESS);
+    }
+
+    setup(i2c::DCXO::Main, &settings.main, timer)?;
+
+    // Si549 maximum settling time for large frequency change.
+    timer.delay_us(40_000);
+
+    unsafe {
+        csr::wrpll::main_dcxo_bitbang_enable_write(0);
+    }
+
+    info!("Main Si549 started");
+    Ok(())
+}
+
+pub fn helper_setup(timer: &mut GlobalTimer, settings: &FrequencySetting) -> Result<(), &'static str> {
+    unsafe {
+        csr::wrpll::helper_reset_write(1);
+        csr::wrpll::helper_dcxo_bitbang_enable_write(1);
+        csr::wrpll::helper_dcxo_i2c_address_write(ADDRESS);
+    }
+
+    setup(i2c::DCXO::Helper, &settings.helper, timer)?;
+
+    // Si549 maximum settling time for large frequency change.
+    timer.delay_us(40_000);
+
+    unsafe {
+        csr::wrpll::helper_reset_write(0);
+        csr::wrpll::helper_dcxo_bitbang_enable_write(0);
+    }
+    info!("Helper Si549 started");
+    Ok(())
+}
+
+fn set_adpll(dcxo: i2c::DCXO, adpll: i32) -> Result<(), &'static str> {
+    if adpll.abs() > ADPLL_MAX {
+        return Err("adpll is too large");
+    }
+
+    match dcxo {
+        i2c::DCXO::Main => unsafe {
+            if csr::wrpll::main_dcxo_bitbang_enable_read() == 1 {
+                return Err("Main si549 bitbang mode is active when using gateware i2c");
+            }
+
+            while csr::wrpll::main_dcxo_adpll_busy_read() == 1 {}
+            if csr::wrpll::main_dcxo_nack_read() == 1 {
+                return Err("Main si549 failed to ack adpll write");
+            }
+
+            csr::wrpll::main_dcxo_i2c_address_write(ADDRESS);
+            csr::wrpll::main_dcxo_adpll_write(adpll as u32);
+
+            csr::wrpll::main_dcxo_adpll_stb_write(1);
+        },
+        i2c::DCXO::Helper => unsafe {
+            if csr::wrpll::helper_dcxo_bitbang_enable_read() == 1 {
+                return Err("Helper si549 bitbang mode is active when using gateware i2c");
+            }
+
+            while csr::wrpll::helper_dcxo_adpll_busy_read() == 1 {}
+            if csr::wrpll::helper_dcxo_nack_read() == 1 {
+                return Err("Helper si549 failed to ack adpll write");
+            }
+
+            csr::wrpll::helper_dcxo_i2c_address_write(ADDRESS);
+            csr::wrpll::helper_dcxo_adpll_write(adpll as u32);
+
+            csr::wrpll::helper_dcxo_adpll_stb_write(1);
+        },
+    };
+
+    Ok(())
+}
+
+#[cfg(has_wrpll)]
+pub mod wrpll {
+
+    use super::*;
+
+    const BEATING_PERIOD: i32 = 0x8000;
+    const BEATING_HALFPERIOD: i32 = 0x4000;
+    const COUNTER_WIDTH: u32 = 24;
+    const DIV_WIDTH: u32 = 2;
+
+    // y[n] = b0*x[n] + b1*x[n-1] + b2*x[n-2] - a1*y[n-1] - a2*y[n-2]
+    struct FilterParameters {
+        pub b0: f64,
+        pub b1: f64,
+        pub b2: f64,
+        pub a1: f64,
+        pub a2: f64,
+    }
+
+    #[cfg(rtio_frequency = "100.0")]
+    const LPF: FilterParameters = FilterParameters {
+        b0: 0.03967479060647884,
+        b1: 0.07934958121295768,
+        b2: 0.03967479060647884,
+        a1: -1.3865593741228928,
+        a2: 0.5452585365488082,
+    };
+
+    #[cfg(rtio_frequency = "125.0")]
+    const LPF: FilterParameters = FilterParameters {
+        b0: 0.07209205036273991,
+        b1: 0.14418410072547982,
+        b2: 0.07209205036273991,
+        a1: -0.6114078511562919,
+        a2: -0.10022394739274834,
+    };
+
+    static mut H_ADPLL1: i32 = 0;
+    static mut H_ADPLL2: i32 = 0;
+    static mut PERIOD_ERR1: i32 = 0;
+    static mut PERIOD_ERR2: i32 = 0;
+
+    static mut M_ADPLL1: i32 = 0;
+    static mut M_ADPLL2: i32 = 0;
+    static mut PHASE_ERR1: i32 = 0;
+    static mut PHASE_ERR2: i32 = 0;
+
+    static mut BASE_ADPLL: i32 = 0;
+
+    #[derive(Clone, Copy)]
+    pub enum ISR {
+        RefTag,
+        MainTag,
+    }
+
+    mod tag_collector {
+        use super::*;
+
+        #[cfg(wrpll_ref_clk = "GT_CDR")]
+        static mut TAG_OFFSET: u32 = 8382;
+        #[cfg(wrpll_ref_clk = "SMA_CLKIN")]
+        static mut TAG_OFFSET: u32 = 0;
+        static mut REF_TAG: u32 = 0;
+        static mut REF_TAG_READY: bool = false;
+        static mut MAIN_TAG: u32 = 0;
+        static mut MAIN_TAG_READY: bool = false;
+
+        pub fn reset() {
+            clear_phase_diff_ready();
+            unsafe {
+                REF_TAG = 0;
+                MAIN_TAG = 0;
+            }
+        }
+
+        pub fn clear_phase_diff_ready() {
+            unsafe {
+                REF_TAG_READY = false;
+                MAIN_TAG_READY = false;
+            }
+        }
+
+        pub fn collect_tags(interrupt: ISR) {
+            match interrupt {
+                ISR::RefTag => unsafe {
+                    REF_TAG = csr::wrpll::ref_tag_read();
+                    REF_TAG_READY = true;
+                },
+                ISR::MainTag => unsafe {
+                    MAIN_TAG = csr::wrpll::main_tag_read();
+                    MAIN_TAG_READY = true;
+                },
+            }
+        }
+
+        pub fn phase_diff_ready() -> bool {
+            unsafe { REF_TAG_READY && MAIN_TAG_READY }
+        }
+
+        #[cfg(feature = "calibrate_wrpll_skew")]
+        pub fn set_tag_offset(offset: u32) {
+            unsafe {
+                TAG_OFFSET = offset;
+            }
+        }
+
+        #[cfg(feature = "calibrate_wrpll_skew")]
+        pub fn get_tag_offset() -> u32 {
+            unsafe { TAG_OFFSET }
+        }
+
+        pub fn get_period_error() -> i32 {
+            // n * BEATING_PERIOD - REF_TAG(n) mod BEATING_PERIOD
+            let mut period_error = unsafe { REF_TAG.overflowing_neg().0.rem_euclid(BEATING_PERIOD as u32) as i32 };
+            // mapping tags from [0, 2π] -> [-π, π]
+            if period_error > BEATING_HALFPERIOD {
+                period_error -= BEATING_PERIOD
+            }
+            period_error
+        }
+
+        pub fn get_phase_error() -> i32 {
+            // MAIN_TAG(n) - REF_TAG(n) - TAG_OFFSET mod BEATING_PERIOD
+            let mut phase_error = unsafe {
+                MAIN_TAG
+                    .overflowing_sub(REF_TAG + TAG_OFFSET)
+                    .0
+                    .rem_euclid(BEATING_PERIOD as u32) as i32
+            };
+
+            // mapping tags from [0, 2π] -> [-π, π]
+            if phase_error > BEATING_HALFPERIOD {
+                phase_error -= BEATING_PERIOD
+            }
+            phase_error
+        }
+    }
+
+    fn set_isr(en: bool) {
+        let val = if en { 1 } else { 0 };
+        unsafe {
+            csr::wrpll::ref_tag_ev_enable_write(val);
+            csr::wrpll::main_tag_ev_enable_write(val);
+        }
+    }
+
+    fn set_base_adpll() -> Result<(), &'static str> {
+        let count2adpll =
+            |error: i32| ((error as f64 * 1e6) / (0.0001164 * (1 << (COUNTER_WIDTH - DIV_WIDTH)) as f64)) as i32;
+
+        let (ref_count, main_count) = get_freq_counts();
+        unsafe {
+            BASE_ADPLL = count2adpll(ref_count as i32 - main_count as i32);
+            set_adpll(i2c::DCXO::Main, BASE_ADPLL)?;
+            set_adpll(i2c::DCXO::Helper, BASE_ADPLL)?;
+        }
+        Ok(())
+    }
+
+    fn get_freq_counts() -> (u32, u32) {
+        unsafe {
+            csr::wrpll::frequency_counter_update_write(1);
+            while csr::wrpll::frequency_counter_busy_read() == 1 {}
+            #[cfg(wrpll_ref_clk = "GT_CDR")]
+            let ref_count = csr::wrpll::frequency_counter_counter_rtio_rx0_read();
+            #[cfg(wrpll_ref_clk = "SMA_CLKIN")]
+            let ref_count = csr::wrpll::frequency_counter_counter_ref_read();
+            let main_count = csr::wrpll::frequency_counter_counter_sys_read();
+
+            (ref_count, main_count)
+        }
+    }
+
+    fn reset_plls(timer: &mut GlobalTimer) -> Result<(), &'static str> {
+        unsafe {
+            H_ADPLL1 = 0;
+            H_ADPLL2 = 0;
+            PERIOD_ERR1 = 0;
+            PERIOD_ERR2 = 0;
+            M_ADPLL1 = 0;
+            M_ADPLL2 = 0;
+            PHASE_ERR1 = 0;
+            PHASE_ERR2 = 0;
+        }
+        set_adpll(i2c::DCXO::Main, 0)?;
+        set_adpll(i2c::DCXO::Helper, 0)?;
+        // wait for adpll to transfer and DCXO to settle
+        timer.delay_us(200);
+        Ok(())
+    }
+
+    fn clear_pending(interrupt: ISR) {
+        match interrupt {
+            ISR::RefTag => unsafe { csr::wrpll::ref_tag_ev_pending_write(1) },
+            ISR::MainTag => unsafe { csr::wrpll::main_tag_ev_pending_write(1) },
+        };
+    }
+
+    fn is_pending(interrupt: ISR) -> bool {
+        match interrupt {
+            ISR::RefTag => unsafe { csr::wrpll::ref_tag_ev_pending_read() == 1 },
+            ISR::MainTag => unsafe { csr::wrpll::main_tag_ev_pending_read() == 1 },
+        }
+    }
+
+    pub fn interrupt_handler() {
+        if is_pending(ISR::RefTag) {
+            tag_collector::collect_tags(ISR::RefTag);
+            clear_pending(ISR::RefTag);
+            helper_pll().expect("failed to run helper DCXO PLL");
+        }
+
+        if is_pending(ISR::MainTag) {
+            tag_collector::collect_tags(ISR::MainTag);
+            clear_pending(ISR::MainTag);
+        }
+
+        if tag_collector::phase_diff_ready() {
+            main_pll().expect("failed to run main DCXO PLL");
+            tag_collector::clear_phase_diff_ready();
+        }
+    }
+
+    fn helper_pll() -> Result<(), &'static str> {
+        let period_err = tag_collector::get_period_error();
+        unsafe {
+            let adpll = ((LPF.b0 * period_err as f64) + (LPF.b1 * PERIOD_ERR1 as f64) + (LPF.b2 * PERIOD_ERR2 as f64)
+                - (LPF.a1 * H_ADPLL1 as f64)
+                - (LPF.a2 * H_ADPLL2 as f64)) as i32;
+            set_adpll(i2c::DCXO::Helper, BASE_ADPLL + adpll)?;
+            H_ADPLL2 = H_ADPLL1;
+            PERIOD_ERR2 = PERIOD_ERR1;
+            H_ADPLL1 = adpll;
+            PERIOD_ERR1 = period_err;
+        };
+        Ok(())
+    }
+
+    fn main_pll() -> Result<(), &'static str> {
+        let phase_err = tag_collector::get_phase_error();
+        unsafe {
+            let adpll = ((LPF.b0 * phase_err as f64) + (LPF.b1 * PHASE_ERR1 as f64) + (LPF.b2 * PHASE_ERR2 as f64)
+                - (LPF.a1 * M_ADPLL1 as f64)
+                - (LPF.a2 * M_ADPLL2 as f64)) as i32;
+            set_adpll(i2c::DCXO::Main, BASE_ADPLL + adpll)?;
+            M_ADPLL2 = M_ADPLL1;
+            PHASE_ERR2 = PHASE_ERR1;
+            M_ADPLL1 = adpll;
+            PHASE_ERR1 = phase_err;
+        };
+        Ok(())
+    }
+
+    #[cfg(wrpll_ref_clk = "GT_CDR")]
+    fn test_skew(timer: &mut GlobalTimer) -> Result<(), &'static str> {
+        // wait for PLL to stabilize
+        timer.delay_us(20_000);
+
+        info!("testing the skew of SYS CLK...");
+        if has_timing_error(timer) {
+            return Err("the skew cannot satisfy setup/hold time constraint of RX synchronizer");
+        }
+        info!("the skew of SYS CLK met the timing constraint");
+        Ok(())
+    }
+
+    #[cfg(wrpll_ref_clk = "GT_CDR")]
+    fn has_timing_error(timer: &mut GlobalTimer) -> bool {
+        unsafe {
+            csr::wrpll_skewtester::error_write(1);
+        }
+        timer.delay_us(5_000);
+        unsafe { csr::wrpll_skewtester::error_read() == 1 }
+    }
+
+    #[cfg(feature = "calibrate_wrpll_skew")]
+    fn find_edge(target: bool, timer: &mut GlobalTimer) -> Result<u32, &'static str> {
+        const STEP: u32 = 8;
+        const STABLE_THRESHOLD: u32 = 10;
+
+        enum FSM {
+            Init,
+            WaitEdge,
+            GotEdge,
+        }
+
+        let mut state: FSM = FSM::Init;
+        let mut offset: u32 = tag_collector::get_tag_offset();
+        let mut median_edge: u32 = 0;
+        let mut stable_counter: u32 = 0;
+
+        for _ in 0..(BEATING_PERIOD as u32 / STEP) as usize {
+            tag_collector::set_tag_offset(offset);
+            offset += STEP;
+            // wait for PLL to stabilize
+            timer.delay_us(20_000);
+
+            let error = has_timing_error(timer);
+            // A median edge deglitcher
+            match state {
+                FSM::Init => {
+                    if error != target {
+                        stable_counter += 1;
+                    } else {
+                        stable_counter = 0;
+                    }
+
+                    if stable_counter >= STABLE_THRESHOLD {
+                        state = FSM::WaitEdge;
+                        stable_counter = 0;
+                    }
+                }
+                FSM::WaitEdge => {
+                    if error == target {
+                        state = FSM::GotEdge;
+                        median_edge = offset;
+                    }
+                }
+                FSM::GotEdge => {
+                    if error != target {
+                        median_edge += STEP;
+                        stable_counter = 0;
+                    } else {
+                        stable_counter += 1;
+                    }
+
+                    if stable_counter >= STABLE_THRESHOLD {
+                        return Ok(median_edge);
+                    }
+                }
+            }
+        }
+        return Err("failed to find timing error edge");
+    }
+
+    #[cfg(feature = "calibrate_wrpll_skew")]
+    fn calibrate_skew(timer: &mut GlobalTimer) -> Result<(), &'static str> {
+        info!("calibrating skew to meet timing constraint...");
+
+        // clear calibrated value
+        tag_collector::set_tag_offset(0);
+        let rising = find_edge(true, timer)? as i32;
+        let falling = find_edge(false, timer)? as i32;
+
+        let width = BEATING_PERIOD - (falling - rising);
+        let result = falling + width / 2;
+        tag_collector::set_tag_offset(result as u32);
+
+        info!(
+            "calibration successful, error zone: {} -> {}, width: {} ({}deg), middle of working region: {}",
+            rising,
+            falling,
+            width,
+            360 * width / BEATING_PERIOD,
+            result,
+        );
+
+        Ok(())
+    }
+
+    pub fn select_recovered_clock(rc: bool, timer: &mut GlobalTimer) {
+        set_isr(false);
+
+        if rc {
+            tag_collector::reset();
+            reset_plls(timer).expect("failed to reset main and helper PLL");
+
+            // get within capture range
+            set_base_adpll().expect("failed to set base adpll");
+
+            // clear gateware pending flag
+            clear_pending(ISR::RefTag);
+            clear_pending(ISR::MainTag);
+
+            // use nFIQ to avoid IRQ being disabled by mutex lock and mess up PLL
+            set_isr(true);
+            info!("WRPLL interrupt enabled");
+
+            #[cfg(feature = "calibrate_wrpll_skew")]
+            calibrate_skew(timer).expect("failed to set the correct skew");
+
+            #[cfg(wrpll_ref_clk = "GT_CDR")]
+            test_skew(timer).expect("skew test failed");
+        }
+    }
+}
+
+#[cfg(has_wrpll_refclk)]
+pub mod wrpll_refclk {
+    use super::*;
+
+    pub struct MmcmSetting {
+        pub clkout0_reg1: u16,  //0x08
+        pub clkout0_reg2: u16,  //0x09
+        pub clkfbout_reg1: u16, //0x14
+        pub clkfbout_reg2: u16, //0x15
+        pub div_reg: u16,       //0x16
+        pub lock_reg1: u16,     //0x18
+        pub lock_reg2: u16,     //0x19
+        pub lock_reg3: u16,     //0x1A
+        pub power_reg: u16,     //0x28
+        pub filt_reg1: u16,     //0x4E
+        pub filt_reg2: u16,     //0x4F
+    }
+
+    fn one_clock_cycle() {
+        unsafe {
+            csr::wrpll_refclk::mmcm_dclk_write(1);
+            csr::wrpll_refclk::mmcm_dclk_write(0);
+        }
+    }
+
+    fn set_addr(address: u8) {
+        unsafe {
+            csr::wrpll_refclk::mmcm_daddr_write(address);
+        }
+    }
+
+    fn set_data(value: u16) {
+        unsafe {
+            csr::wrpll_refclk::mmcm_din_write(value);
+        }
+    }
+
+    fn set_enable(en: bool) {
+        unsafe {
+            let val = if en { 1 } else { 0 };
+            csr::wrpll_refclk::mmcm_den_write(val);
+        }
+    }
+
+    fn set_write_enable(en: bool) {
+        unsafe {
+            let val = if en { 1 } else { 0 };
+            csr::wrpll_refclk::mmcm_dwen_write(val);
+        }
+    }
+
+    fn get_data() -> u16 {
+        unsafe { csr::wrpll_refclk::mmcm_dout_read() }
+    }
+
+    fn drp_ready() -> bool {
+        unsafe { csr::wrpll_refclk::mmcm_dready_read() == 1 }
+    }
+
+    #[allow(dead_code)]
+    fn read(address: u8) -> u16 {
+        set_addr(address);
+        set_enable(true);
+        // Set DADDR on the mmcm and assert DEN for one clock cycle
+        one_clock_cycle();
+
+        set_enable(false);
+        while !drp_ready() {
+            // keep the clock signal until data is ready
+            one_clock_cycle();
+        }
+        get_data()
+    }
+
+    fn write(address: u8, value: u16) {
+        set_addr(address);
+        set_data(value);
+        set_write_enable(true);
+        set_enable(true);
+        // Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
+        one_clock_cycle();
+
+        set_write_enable(false);
+        set_enable(false);
+        while !drp_ready() {
+            // keep the clock signal until write is finished
+            one_clock_cycle();
+        }
+    }
+
+    fn reset(rst: bool) {
+        unsafe {
+            let val = if rst { 1 } else { 0 };
+            csr::wrpll_refclk::mmcm_reset_write(val)
+        }
+    }
+
+    pub fn setup(timer: &mut GlobalTimer, settings: MmcmSetting, mmcm_bypass: bool) -> Result<(), &'static str> {
+        unsafe {
+            csr::wrpll_refclk::refclk_reset_write(1);
+        }
+
+        if mmcm_bypass {
+            info!("Bypassing mmcm");
+            unsafe {
+                csr::wrpll_refclk::mmcm_bypass_write(1);
+            }
+        } else {
+            // Based on "DRP State Machine" from XAPP888
+            // hold reset HIGH during mmcm config
+            reset(true);
+            write(0x08, settings.clkout0_reg1);
+            write(0x09, settings.clkout0_reg2);
+            write(0x14, settings.clkfbout_reg1);
+            write(0x15, settings.clkfbout_reg2);
+            write(0x16, settings.div_reg);
+            write(0x18, settings.lock_reg1);
+            write(0x19, settings.lock_reg2);
+            write(0x1A, settings.lock_reg3);
+            write(0x28, settings.power_reg);
+            write(0x4E, settings.filt_reg1);
+            write(0x4F, settings.filt_reg2);
+            reset(false);
+
+            // wait for the mmcm to lock
+            timer.delay_us(100);
+
+            let locked = unsafe { csr::wrpll_refclk::mmcm_locked_read() == 1 };
+            if !locked {
+                return Err("mmcm failed to generate 125MHz ref clock from SMA CLKIN");
+            }
+        }
+
+        unsafe {
+            csr::wrpll_refclk::refclk_reset_write(0);
+        }
+
+        Ok(())
+    }
+}