M-Labs
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artiq-zynq
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update dependencies

This commit is contained in:
Astro 2020-08-17 19:17:15 +02:00
parent 6ccd0cb389
commit 760f46a115
8 changed files with 18 additions and 18 deletions
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18
src/Cargo.lock generated
View File

@ -68,9 +68,9 @@ checksum = "0f8cb7306107e4b10e64994de6d3274bd08996a7c1322a27b86482392f96be0a"
[[package]]
name = "cstr_core"
version = "0.2.0"
version = "0.2.1"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "8758514b5f03968703f1db1f1e196e031d5268f5295ff99a5bf345008790ba85"
checksum = "edf9ff5f1182cea3b0f4269dd3edf146b5bfedc5dc8a29b95edf855f438786b7"
dependencies = [
"cty",
"memchr",
@ -201,7 +201,7 @@ dependencies = [
[[package]]
name = "libasync"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#e8ba73a8c74f79f543db6a495ac65aae68e18bab"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
dependencies = [
"embedded-hal",
"libcortex_a9",
@ -213,7 +213,7 @@ dependencies = [
[[package]]
name = "libboard_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#e8ba73a8c74f79f543db6a495ac65aae68e18bab"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
dependencies = [
"bit_field",
"embedded-hal",
@ -237,7 +237,7 @@ dependencies = [
[[package]]
name = "libcortex_a9"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#e8ba73a8c74f79f543db6a495ac65aae68e18bab"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
dependencies = [
"bit_field",
"libregister",
@ -252,7 +252,7 @@ checksum = "c7d73b3f436185384286bd8098d17ec07c9a7d2388a6599f824d8502b529702a"
[[package]]
name = "libregister"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#e8ba73a8c74f79f543db6a495ac65aae68e18bab"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
dependencies = [
"bit_field",
"vcell",
@ -262,7 +262,7 @@ dependencies = [
[[package]]
name = "libsupport_zynq"
version = "0.0.0"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#e8ba73a8c74f79f543db6a495ac65aae68e18bab"
source = "git+https://git.m-labs.hk/M-Labs/zynq-rs.git#64db9b0142a4a24349394d2082342cdecf30cf08"
dependencies = [
"compiler_builtins",
"libboard_zynq",
@ -274,9 +274,9 @@ dependencies = [
[[package]]
name = "linked_list_allocator"
version = "0.8.4"
version = "0.8.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "e70e46c13c0e8374c26cec5752e3347ca1087d9711de8f45aa513a7700efd73d"
checksum = "660b26e6156a7d00eefb19052fe1943cf5ab2f353a723a577fad6ba2f99d1f90"
[[package]]
name = "log"

2
src/runtime/src/comms.rs
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@ -319,7 +319,7 @@ pub fn main(timer: GlobalTimer, cfg: &config::Config) {
let net_addresses = net_settings::get_adresses(cfg);
info!("network addresses: {}", net_addresses);
let eth = zynq::eth::Eth::default(net_addresses.hardware_addr.0.clone());
let eth = zynq::eth::Eth::eth0(net_addresses.hardware_addr.0.clone());
const RX_LEN: usize = 8;
// Number of transmission buffers (minimum is two because with
// one, duplicate packet transmission occurs)

2
src/runtime/src/config.rs
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@ -68,7 +68,7 @@ pub struct Config {
impl Config {
pub fn new() -> Result<'static, Self> {
let sdio = sdio::SDIO::sdio0(true);
let sdio = sdio::Sdio::sdio0(true);
if !sdio.is_card_inserted() {
Err(sdio::sd_card::CardInitializationError::NoCardInserted)?;
}

6
src/runtime/src/irq.rs
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@ -19,8 +19,8 @@ static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
#[naked]
pub unsafe extern "C" fn IRQ() {
if MPIDR.read().cpu_id() == 1 {
let mpcore = mpcore::RegisterBlock::new();
let mut gic = gic::InterruptController::new(mpcore);
let mpcore = mpcore::RegisterBlock::mpcore();
let mut gic = gic::InterruptController::gic(mpcore);
let id = gic.get_interrupt_id();
if id.0 == 0 {
gic.end_interrupt(id);
@ -38,7 +38,7 @@ pub unsafe extern "C" fn IRQ() {
}
pub fn restart_core1() {
let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
CORE1_RESTART.store(true, Ordering::Relaxed);
interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
while CORE1_RESTART.load(Ordering::Relaxed) {

2
src/runtime/src/kernel/core1.rs
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@ -143,7 +143,7 @@ pub fn main_core1() {
debug!("FPU enabled on Core1");
ram::init_alloc_core1();
gic::InterruptController::new(mpcore::RegisterBlock::new()).enable_interrupts();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
let (mut core0_tx, mut core1_rx) = sync_channel!(Message, 4);
let (mut core1_tx, core0_rx) = sync_channel!(Message, 4);

2
src/runtime/src/load_pl.rs
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@ -153,7 +153,7 @@ pub fn load_bitstream<File: Read + Seek>(
}
pub fn load_bitstream_from_sd() -> Result<(), PlLoadingError> {
let sdio0 = sdio::SDIO::sdio0(true);
let sdio0 = sdio::Sdio::sdio0(true);
if sdio0.is_card_inserted() {
info!("Card inserted. Mounting file system.");
let sd = sdio::sd_card::SdCard::from_sdio(sdio0).unwrap();

2
src/runtime/src/main.rs
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@ -192,7 +192,7 @@ pub fn main_core0() {
info!("NAR3/Zynq7000 starting...");
ram::init_alloc_core0();
gic::InterruptController::new(mpcore::RegisterBlock::new()).enable_interrupts();
gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()).enable_interrupts();
init_gateware();
info!("detected gateware: {}", identifier_read(&mut [0; 64]));

2
src/szl/src/main.rs
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@ -69,7 +69,7 @@ pub fn main_core0() {
Clocks::set_cpu_freq(CPU_FREQ);
IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart(); // reinitialize UART after clocking change
let mut ddr = zynq::ddr::DdrRam::new();
let mut ddr = zynq::ddr::DdrRam::ddrram();
let payload = include_bytes!("../../../build/szl-payload.bin.lzma");
info!("decompressing payload");