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DRTIO port - gateware #140

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sb10q merged 13 commits from mwojcik/artiq-zynq:drtio_gateware into master 2021-10-08 16:12:30 +08:00
Conversation 0 Commits 13 Files Changed 3 +751 -35
mwojcik commented 2021-10-05 16:25:57 +08:00
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This is a part of few pull requests for DRTIO functionality. They have been broken up to allow easier code review overall. They're identical in contents to drtio_port branch.

This PR includes changes in gateware to accomodate DRTIO features, as well as AXI specific DRTIO aux controller.

This PR can be merged anytime as it doesn't have external dependencies.

Any feedback and suggestions are welcome.

This is a part of few pull requests for DRTIO functionality. They have been broken up to allow easier code review overall. They're identical in contents to drtio_port branch. This PR includes changes in gateware to accomodate DRTIO features, as well as AXI specific DRTIO aux controller. This PR can be merged anytime as it doesn't have external dependencies. Any feedback and suggestions are welcome.
mwojcik added 2 commits 2021-10-05 16:25:57 +08:00
sb10q reviewed 2021-10-06 13:06:55 +08:00
src/gateware/aux_controller.py Outdated
@ -0,0 +1,85 @@
"""Auxiliary controller, common to satellite and master"""
sb10q commented 2021-10-06 13:06:55 +08:00
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I would rename the file to drtio_aux_controller.py.

I would rename the file to ``drtio_aux_controller.py``.
mwojcik marked this conversation as resolved
sb10q reviewed 2021-10-06 13:08:27 +08:00
src/gateware/zc706.py Outdated
@ -67,0 +98,4 @@
Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
MultiReg(pll_locked, self.pll_locked.status)
]
sb10q commented 2021-10-06 13:08:26 +08:00
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Share with Kasli-SoC?

Share with Kasli-SoC?
sb10q commented 2021-10-06 13:08:55 +08:00
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...or even put it in artiq.gateware and share with the other boards.

...or even put it in ``artiq.gateware`` and share with the other boards.
mwojcik commented 2021-10-06 15:05:57 +08:00
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It's the same thing for artiq kasli, kc705 and sayma_rtm boards. I could separate it and save few lines everywhere, but where to put it, so it fits nicely? I'm thinking artiq.gateware.rtio.clock_multiplier? or maybe just artiq.gateware.clock_multiplier?

It's the same thing for artiq kasli, kc705 and sayma_rtm boards. I could separate it and save few lines everywhere, but where to put it, so it fits nicely? I'm thinking ``artiq.gateware.rtio.clock_multiplier``? or maybe just ``artiq.gateware.clock_multiplier``?
sb10q commented 2021-10-06 16:25:56 +08:00
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Maybe artiq.gateware.rtio.xilinx_clocking, along with the SERDES rules?

Maybe ``artiq.gateware.rtio.xilinx_clocking``, along with the SERDES rules?
mwojcik marked this conversation as resolved
sb10q reviewed 2021-10-06 13:09:01 +08:00
src/gateware/zc706.py Outdated
@ -67,0 +109,4 @@
"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
)
sb10q commented 2021-10-06 13:09:01 +08:00
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ditto

ditto
mwojcik marked this conversation as resolved
sb10q reviewed 2021-10-06 13:09:52 +08:00
src/gateware/zc706.py Outdated
@ -73,3 +148,1 @@
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
platform = prepare_zc706_platform(platform)
sb10q commented 2021-10-06 13:09:52 +08:00
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No need to return platform and reassign it. The object is mutated in-place.

No need to return ``platform`` and reassign it. The object is mutated in-place.
mwojcik marked this conversation as resolved
sb10q reviewed 2021-10-06 13:11:31 +08:00
src/gateware/zc706.py
@ -128,0 +383,4 @@
self.submodules.drtiosat = core
self.csr_devices.append("drtiosat")
# Repeaters - there would be for i != 0 - however zc706 only has one SFP
# and no other means to connect to
sb10q commented 2021-10-06 13:11:31 +08:00
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There's the link on the MGT SMAs but I doubt anyone needs this. @dhslichter ?

There's the link on the MGT SMAs but I doubt anyone needs this. @dhslichter ?
sb10q reviewed 2021-10-06 13:14:41 +08:00
src/gateware/zc706.py
@ -128,0 +265,4 @@
self.rustc_cfg["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
if use_si5324_33:
sb10q commented 2021-10-06 13:14:41 +08:00
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You can use assume it is true at all times and simplify the code accordingly. Only NIST backplanes are supported on ZC706 and they need the 3.3V signals.

You can use assume it is true at all times and simplify the code accordingly. Only NIST backplanes are supported on ZC706 and they need the 3.3V signals.
mwojcik commented 2021-10-06 14:54:42 +08:00
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So there won't be "simple" master/satellite? What about the board I've been testing it on, is it with a backplane?

So there won't be "simple" master/satellite? What about the board I've been testing it on, is it with a backplane?
sb10q commented 2021-10-06 16:29:07 +08:00
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"Simple" targets were just for testing, on the same hardware that has the backplane installed (even if they don't use the backplane).
Also fine to remove these targets, they were only there for the initial development.

"Simple" targets were just for testing, on the same hardware that has the backplane installed (even if they don't use the backplane). Also fine to remove these targets, they were only there for the initial development.
mwojcik commented 2021-10-06 17:56:39 +08:00
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Okay, makes sense, I was somewhat worried about mismatched voltages for si5324. Although I don't think this is the place to be removing the simple targets, that should be done in another PR (not only unrelated functionally to drtio, it also touches gateware, nix scripts and readme).

Okay, makes sense, I was somewhat worried about mismatched voltages for si5324. Although I don't think this is the place to be removing the simple targets, that should be done in another PR (not only unrelated functionally to drtio, it also touches gateware, nix scripts and readme).
sb10q commented 2021-10-06 19:39:27 +08:00
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Changing the IOSTANDARD here does not actually change the voltage produced by the FPGA I/O, and will not damage the Si5324. In fact it even works correctly in practice when the voltage in the CMOS/TTL IOSTANDARD is wrong.

Changing the IOSTANDARD here does not actually change the voltage produced by the FPGA I/O, and will not damage the Si5324. In fact it even works correctly in practice when the voltage in the CMOS/TTL IOSTANDARD is wrong.
👍 1
mwojcik added 1 commit 2021-10-06 14:44:53 +08:00
mwojcik added 1 commit 2021-10-06 15:08:18 +08:00
mwojcik added 2 commits 2021-10-06 17:31:45 +08:00
mwojcik added 1 commit 2021-10-06 17:39:51 +08:00
mwojcik added 1 commit 2021-10-06 17:45:51 +08:00
mwojcik added 1 commit 2021-10-06 17:52:00 +08:00
mwojcik added 1 commit 2021-10-06 17:54:11 +08:00
mwojcik added 1 commit 2021-10-07 17:44:51 +08:00
mwojcik added 1 commit 2021-10-07 17:51:40 +08:00
mwojcik added 1 commit 2021-10-07 20:48:41 +08:00
sb10q reviewed 2021-10-08 16:11:41 +08:00
src/gateware/kasli_soc.py
@ -178,0 +198,4 @@
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")
# kasli_soc has no SATA, but it has 4x SFP
# not sure yet why sfp0 is omitted in MasterMode
sb10q commented 2021-10-08 16:11:41 +08:00
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It's omitted on Kasli because it's used for Ethernet.
Kasli-SoC has a dedicated RJ45 port.

It's omitted on Kasli because it's used for Ethernet. Kasli-SoC has a dedicated RJ45 port.
sb10q merged commit ab0c205dd2 into master 2021-10-08 16:12:30 +08:00
sb10q referenced this issue from a commit 2021-10-08 16:12:33 +08:00
gateware: add DRTIO
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Reference: M-Labs/artiq-zynq#140
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