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artiq-zynq
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increase CSR bus width to 32 bits 

Before:
Minimum interval for sustained TTL output switching ... 1.554e-06

After:
Minimum interval for sustained TTL output switching ... 5.17e-07
This commit is contained in:
Sebastien Bourdeauducq 2020-07-07 17:22:07 +08:00
parent 7bfe882710
commit b13da96835
1 changed files with 1 additions and 1 deletions
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2
src/zc706.py
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@ -18,7 +18,7 @@ class ZC706(SoCCore):
platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])
SoCCore.__init__(self, platform=platform, ident=self.__class__.__name__)
SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=self.__class__.__name__)
platform.add_platform_command("create_clock -name clk_fpga_0 -period 8 [get_pins \"PS7/FCLKCLK[0]\"]")
platform.add_platform_command("set_input_jitter clk_fpga_0 0.24")