drtio: port 64-bit padding from mainline

pull/192/head
mwojcik 8 months ago
parent efc432352e
commit 57d7f01b04
  1. 9
      src/libboard_artiq/src/drtioaux.rs
  2. 9
      src/libboard_artiq/src/drtioaux_async.rs

@ -153,11 +153,10 @@ pub fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
packet.write_to(&mut writer)?;
let padding = 4 - (writer.position() % 4);
if padding != 4 {
for _ in 0..padding {
writer.write_u8(0)?;
}
// Pad till offset 4, insert checksum there
let padding = (12 - (writer.position() % 8)) % 8;
for _ in 0..padding {
writer.write_u8(0)?;
}
let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);

@ -124,11 +124,10 @@ pub async fn send(linkno: u8, packet: &Packet) -> Result<(), Error> {
packet.write_to(&mut writer)?;
let padding = 4 - (writer.position() % 4);
if padding != 4 {
for _ in 0..padding {
writer.write_u8(0)?;
}
// Pad till offset 4, insert checksum there
let padding = (12 - (writer.position() % 8)) % 8;
for _ in 0..padding {
writer.write_u8(0)?;
}
let checksum = crc::crc32::checksum_ieee(&writer.get_ref()[0..writer.position()]);

Loading…
Cancel
Save