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3f3ec597a1
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Update README.md
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2020-08-26 17:21:27 +08:00 |
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46e6ca3f70
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Add REMU instruction
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2020-08-26 17:15:27 +08:00 |
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fb91df7bb8
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Add REM instruction
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2020-08-26 17:11:03 +08:00 |
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33ace9147a
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Add DIVU instruction
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2020-08-26 17:03:49 +08:00 |
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0708f6b962
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Add DIV instruction
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2020-08-26 16:58:50 +08:00 |
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b74a0cf699
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Add MULHU instruction
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2020-08-26 16:43:21 +08:00 |
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a58842ea94
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Add MULHSU instruction
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2020-08-26 16:39:17 +08:00 |
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15580a74c6
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Add MULH instruction
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2020-08-26 16:30:54 +08:00 |
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585965ee0a
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Add MUL instruction
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2020-08-26 15:57:32 +08:00 |
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dd17606902
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Add RV32M R-Type Instruction
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2020-08-26 15:48:55 +08:00 |
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3030839c42
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Update README.md
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2020-08-25 13:38:31 +08:00 |
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d1d93a6b6a
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Update README.md
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2020-08-25 13:17:16 +08:00 |
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83e65e50c5
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Fix broken README
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2020-08-25 12:43:13 +08:00 |
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ca9e9c9ca6
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Add prototype for instruction/data bus implementation
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2020-08-25 12:41:30 +08:00 |
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ac7991ae86
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Merge instruction and data bus abstractions
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2020-08-25 10:12:02 +08:00 |
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ca135d024f
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Wire instruction and data buses (WIP) to Minerva core
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2020-08-24 14:46:52 +08:00 |
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2a4f6dd07e
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Wire interrupt signals to Minerva for verification
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2020-08-24 13:28:33 +08:00 |
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ee80bff3db
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Merge riscv_formal_parameters.py into verify.py
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2020-08-24 10:20:30 +08:00 |
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607d82f27c
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Add "Known Issues" section to README
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2020-08-21 16:58:33 +08:00 |
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dad6022572
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Replace individual instruction checks with ISA check
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2020-08-21 15:14:42 +08:00 |
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908ecf9e7e
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Add uniqueness check
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2020-08-21 13:25:52 +08:00 |
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a7b6b7a169
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Add liveness check
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2020-08-21 12:54:53 +08:00 |
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63fbc10b11
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Update README.md
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2020-08-21 11:53:20 +08:00 |
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9e530bc729
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Merge pull request 'Apply more PEP 8 guidelines, remove hacks and reduce code duplication' (#3) from refactoring into master
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2020-08-21 11:48:13 +08:00 |
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c6b9bb9a04
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Update README.md
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2020-08-21 11:46:39 +08:00 |
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d7d4f8b0ad
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Reduce code duplication in Minerva verification script
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2020-08-21 11:43:20 +08:00 |
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de3ff25da1
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Refactor insns directory
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2020-08-21 10:33:02 +08:00 |
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3e527b3727
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Refactor instructions to use NamedTuple
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2020-08-20 17:28:09 +08:00 |
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1a38b37473
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Remove copy of Minerva
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2020-08-20 15:32:10 +08:00 |
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b9e4279ffe
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Replace nMigen copy with shell.nix config file
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2020-08-20 12:52:06 +08:00 |
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a6b4891a38
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Add causal checks
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2020-08-20 12:00:31 +08:00 |
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2a9ddf0868
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Add register checks
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2020-08-20 11:10:33 +08:00 |
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2383706012
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Add PC backward checks
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2020-08-19 17:22:03 +08:00 |
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2bfd909b49
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Add PC forward checks
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2020-08-19 17:00:11 +08:00 |
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f7ddbf8cd8
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Fix broken markdown in README.md
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2020-08-19 14:58:00 +08:00 |
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c073411bd2
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Add tests for all RV32I instructions
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2020-08-19 14:56:26 +08:00 |
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0e0d4b6e42
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Add (currently failing) test case for LUI instruction
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2020-08-18 14:10:47 +08:00 |
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3faa8ed1b8
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Add build instructions for Minerva
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2020-08-17 16:46:15 +08:00 |
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7005d22e4e
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Add instruction check
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2020-08-17 16:03:20 +08:00 |
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d749b297cf
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Update README.md
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2020-08-17 12:05:39 +08:00 |
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73707afe78
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Modularize codebase
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2020-08-17 11:50:53 +08:00 |
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1982668829
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Add Minerva core, to be integrated later
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2020-08-13 17:38:04 +08:00 |
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6459c71ac5
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Merge pull request 'Restructure insns directory contents' (#2) from restructuring into master
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2020-08-13 15:20:35 +08:00 |
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f358e0679a
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Rename module names to follow PEP8
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2020-08-13 15:14:46 +08:00 |
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4d211bb24a
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Update README.md
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2020-08-13 14:28:42 +08:00 |
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40344f7841
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Add RV32I base ISA
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2020-08-13 14:23:55 +08:00 |
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28949f36f4
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Fix typo in InsnSw.py
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2020-08-13 13:46:16 +08:00 |
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9f6c634f4a
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Update README.md
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2020-08-13 12:19:40 +08:00 |
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6868e0d742
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Prepare RV32I Base ISA
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2020-08-12 17:26:39 +08:00 |
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75d1133125
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Remove redundant parameter in InsnAuipc constructor
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2020-08-12 14:23:09 +08:00 |
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