riscv-formal-nmigen

A port of riscv-formal to nMigen

Breakdown

File/Directory	Description
shell.nix	nix-shell configuration file
rvfi	RISC-V Formal Verification Framework (nMigen port)
rvfi/insns	Supported RISC-V instructions and ISAs
rvfi/checks	Checks for RISC-V compliant cores
rvfi/cores	Cores currently tested against this port of riscv-formal
rvfi/cores/minerva/verify.py	Verification tasks for the Minerva core

Running the Verification

First make sure you have Nix installed. Then cd to the root directory of this repo and run:

$ nix-shell

This should run the tests (cache, multiplier, divider) provided by Minerva itself and give you an environment with all the dependencies required for this project. Then, to run the main verification tasks for Minerva provided in this repo:

$ python -m rvfi.cores.minerva.verify

This should run in the order of a few minutes.

Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

Known Issues

• 21/08/2020: Verification passes unconditionally, even in the presence of obvious bugs. This is due to the rvfi.valid signal from the CPU being held at constant 0. Suitable instruction and data buses as well as interrupt signals have not been wired to Minerva which is likely preventing the core and verification from functioning properly
• 25/08/2020: Interrupts have been hardwired to zero and instruction/data buses attached to the Minerva core; however, running the verification completely hangs the machine. Possible culprit: huge number of Assume statements on memory values leading to overly large solution space

As of 25/08

License

See LICENSE