M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
283 Commits 1 Branch 0 Tags 683 KiB
Python 99.4%
Nix 0.6%
Go to file
Donald Sebastian Leung 0e0d4b6e42 Add (currently failing) test case for LUI instruction 2020-08-18 14:10:47 +08:00
rvfi Add (currently failing) test case for LUI instruction 2020-08-18 14:10:47 +08:00
LICENSE Fix copyright holder in license 2020-08-03 12:19:14 +08:00
README.md Add build instructions for Minerva 2020-08-17 16:46:15 +08:00

README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Dependencies

Breakdown

Directory Description
rvfi RISC-V Formal Verification Framework (nMigen port)
rvfi/insns Supported RISC-V instructions and ISAs
rvfi/cores Example cores to be integrated with riscv-formal-nmigen (WIP)
rvfi/cores/minerva The Minerva core

Build

Minerva

cd to the root directory of this project and do:

$ python -m rvfi.cores.minerva.verify

Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

License

See LICENSE