Update README.md
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@ -84,6 +84,15 @@ Below is a list of instructions currently supported by this port of the riscv-fo
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- `InsnRV32IUType`: RV32I U-Type Instruction
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- `InsnLui`: LUI instruction
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- `InsnAuipc`: AUIPC instruction
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- `InsnRV32MRType`: RV32M R-Type Instruction
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- `InsnMul`: MUL instruction
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- `InsnMulh`: MULH instruction
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- `InsnMulhsu`: MULHSU instruction
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- `InsnMulhu`: MULHU instruction
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- `InsnDiv`: DIV instruction
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- `InsnDivu`: DIVU instruction
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- `InsnRem`: REM instruction
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- `InsnRemu`: REMU instruction
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### ISAs
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@ -100,3 +109,4 @@ The following core-specific parameters are currently supported:
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| `params.csr_misa` | Support for MISA CSRs enabled | `True`, `False` |
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| `params.compressed` | Support for compressed instructions | `True`, `False` |
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| `params.aligned_mem` | Require aligned memory accesses | `True`, `False` |
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| `params.altops` | Use alternative operations for multiplication/division | `True`, `False` |
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