M-Labs
/
riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Fix broken README

master
Donald Sebastian Leung 2020-08-25 12:43:13 +08:00
parent ca9e9c9ca6
commit 83e65e50c5
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -38,8 +38,6 @@ Support for the RV32I base ISA and RV32M extension are planned and well underway
- 21/08/2020: Verification passes unconditionally, even in the presence of obvious bugs. This is due to the `rvfi.valid` signal from the CPU being held at constant 0. Suitable instruction and data buses as well as interrupt signals have not been wired to Minerva which is likely preventing the core and verification from functioning properly
- 25/08/2020: Interrupts have been hardwired to zero and instruction/data buses attached to the Minerva core; however, running the verification completely hangs the machine. Possible culprit: huge number of `Assume` statements on memory values leading to overly large solution space
As of 25/08
## License
See [LICENSE](./LICENSE)