M-Labs/riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add DIV instruction

Browse Source
This commit is contained in:
Donald Sebastian Leung 2020-08-26 16:58:50 +08:00
parent b74a0cf699
commit 0708f6b962
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
rvfi/insns/insn_div.py Normal file
View File

@ -0,0 +1,18 @@
from .insn_rv32m_r_type import *
"""
DIV instruction
"""
class InsnDiv(InsnRV32MRType):
def __init__(self, params):
super().__init__(params, 0b100)
def elaborate(self, platform):
m = super().elaborate(platform)
if self.params.altops:
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (self.rvfi_rs1_rdata - self.rvfi_rs2_rdata) ^ 0x29bbf66f7f8529ec, 0))
else:
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, Mux(self.rvfi_rs2_rdata == 0, 2 ** self.params.xlen - 1, Mux((self.rvfi_rs1_rdata == (1 << (self.params.xlen - 1))) & (self.rvfi_rs2_rdata == 2 ** self.params.xlen - 1), 1 << (self.params.xlen - 1), Value.as_signed(self.rvfi_rs1_rdata) // Value.as_signed(self.rvfi_rs2_rdata))), 0))
return m