A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
cores/minerva | ||
insns | ||
LICENSE | ||
README.md |
riscv-formal-nmigen
A port of riscv-formal to nMigen
Dependencies
Breakdown
This section is currently a work in progress.
Directory | Description |
---|---|
insns |
Supported RISC-V instructions and ISAs |
cores |
Example cores to be integrated with riscv-formal-nmigen (WIP) |
Build
This framework is not ready to be used to verify RISC-V compliant cores at the time of writing. Instructions for running the framework against such a core will be added once the framework is ready for use.
Scope
Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.
License
See LICENSE