M-Labs/riscv-formal-nmigen
6
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity
A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
289 Commits 1 Branch 0 Tags 683 KiB
Python 99.4%
Nix 0.6%
a6b4891a38
Go to file
Donald Sebastian Leung a6b4891a38 Add causal checks
2020-08-20 12:00:31 +08:00
nmigen Add tests for all RV32I instructions 2020-08-19 14:56:26 +08:00
rvfi Add causal checks 2020-08-20 12:00:31 +08:00
LICENSE Fix copyright holder in license 2020-08-03 12:19:14 +08:00
README.md Fix broken markdown in README.md 2020-08-19 14:58:00 +08:00

README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Dependencies

  • nMigen

    Note that:

    1. Even though this project includes a copy of nMigen, it is highly recommended to remove the copy and install the latest version of nMigen on your system for building this repo
    2. The nMigen package that comes with the Nix package manager may not contain the latest changes and therefore may not work with this repo
    3. If you do choose to keep the copy of nMigen provided in this repo anyway, you may need to separately install its dependencies for the build to work:

  • Yosys

  • SymbiYosys

Breakdown

Directory Description
nmigen nMigen
rvfi RISC-V Formal Verification Framework (nMigen port)
rvfi/insns Supported RISC-V instructions and ISAs
rvfi/cores Example cores for verification with riscv-formal-nmigen
rvfi/cores/minerva The Minerva core

Build

Minerva

cd to the root directory of this project and do:

$ python -m rvfi.cores.minerva.verify

You may see some warning messages about unused Elaboratables and deprecated use of Simulation which can be safely ignored.

Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

License

See LICENSE