A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

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README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Breakdown

Directory	Description
`shell.nix`	nix-shell configuration file
`rvfi`	RISC-V Formal Verification Framework (nMigen port)
`rvfi/insns`	Supported RISC-V instructions and ISAs
`rvfi/cores`	Example cores for verification with riscv-formal-nmigen
`rvfi/cores/minerva`	The Minerva core

Running the Verification

First make sure you have Nix installed. Then cd to the root directory of this repo and run:

$ nix-shell

This should give you an environment with all the dependencies required for this project. Then, to run the verification:

$ python -m rvfi.cores.minerva.verify

You may see some warnings on unused Elaboratables and deprecated use of Simulator emitted which can be safely ignored.

Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

License

See LICENSE