Reduce code duplication in Minerva verification script
This commit is contained in:
parent
de3ff25da1
commit
d7d4f8b0ad
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@ -15,6 +15,7 @@ class CausalCheck(Elaboratable):
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self.rvfi_order = Signal(64)
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self.rvfi_rs1_addr = Signal(5)
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self.rvfi_rs2_addr = Signal(5)
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def ports(self):
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input_ports = [
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self.reset,
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@ -26,6 +27,7 @@ class CausalCheck(Elaboratable):
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self.rvfi_rs2_addr
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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@ -6,13 +6,9 @@ Instruction Check
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"""
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class InsnCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED, RISCV_FORMAL_ALIGNED_MEM, insn_model, rvformal_addr_valid):
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# Core-specific constants
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self.RISCV_FORMAL_ILEN = RISCV_FORMAL_ILEN
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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self.RISCV_FORMAL_CSR_MISA = RISCV_FORMAL_CSR_MISA
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self.RISCV_FORMAL_COMPRESSED = RISCV_FORMAL_COMPRESSED
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self.RISCV_FORMAL_ALIGNED_MEM = RISCV_FORMAL_ALIGNED_MEM
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def __init__(self, params, insn_model, rvformal_addr_valid):
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# Core-specific parameters
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self.params = params
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# Instruction under test
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self.insn_model = insn_model
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@ -26,7 +22,7 @@ class InsnCheck(Elaboratable):
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_insn = Signal(self.RISCV_FORMAL_ILEN)
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self.rvfi_insn = Signal(self.params.ilen)
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self.rvfi_trap = Signal(1)
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self.rvfi_halt = Signal(1)
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self.rvfi_intr = Signal(1)
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@ -34,22 +30,23 @@ class InsnCheck(Elaboratable):
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self.rvfi_ixl = Signal(2)
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self.rvfi_rs1_addr = Signal(5)
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self.rvfi_rs2_addr = Signal(5)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.params.xlen)
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self.rvfi_rs2_rdata = Signal(self.params.xlen)
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self.rvfi_rd_addr = Signal(5)
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self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.rvfi_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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self.rvfi_mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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if self.RISCV_FORMAL_CSR_MISA:
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self.rvfi_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_csr_misa_wmask = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_csr_misa_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rd_wdata = Signal(self.params.xlen)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_pc_wdata = Signal(self.params.xlen)
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self.rvfi_mem_addr = Signal(self.params.xlen)
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self.rvfi_mem_rmask = Signal(int(self.params.xlen // 8))
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self.rvfi_mem_wmask = Signal(int(self.params.xlen // 8))
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self.rvfi_mem_rdata = Signal(self.params.xlen)
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self.rvfi_mem_wdata = Signal(self.params.xlen)
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if self.params.csr_misa:
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self.rvfi_csr_misa_rmask = Signal(self.params.xlen)
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self.rvfi_csr_misa_wmask = Signal(self.params.xlen)
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self.rvfi_csr_misa_rdata = Signal(self.params.xlen)
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self.rvfi_csr_misa_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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@ -76,7 +73,7 @@ class InsnCheck(Elaboratable):
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self.rvfi_mem_rdata,
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self.rvfi_mem_wdata
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]
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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input_ports.extend([
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self.rvfi_csr_misa_rmask,
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self.rvfi_csr_misa_wmask,
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@ -84,78 +81,54 @@ class InsnCheck(Elaboratable):
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self.rvfi_csr_misa_wdata
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])
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return input_ports
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def elaborate(self, platform):
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m = Module()
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valid = Signal(1)
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m.d.comb += valid.eq((~self.reset) & self.rvfi_valid)
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insn = Signal(self.RISCV_FORMAL_ILEN)
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m.d.comb += insn.eq(self.rvfi_insn)
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trap = Signal(1)
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m.d.comb += trap.eq(self.rvfi_trap)
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halt = Signal(1)
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m.d.comb += halt.eq(self.rvfi_halt)
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intr = Signal(1)
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m.d.comb += intr.eq(self.rvfi_intr)
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rs1_addr = Signal(5)
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m.d.comb += rs1_addr.eq(self.rvfi_rs1_addr)
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rs2_addr = Signal(5)
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m.d.comb += rs2_addr.eq(self.rvfi_rs2_addr)
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rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += rs1_rdata.eq(self.rvfi_rs1_rdata)
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rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += rs2_rdata.eq(self.rvfi_rs2_rdata)
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rd_addr = Signal(5)
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m.d.comb += rd_addr.eq(self.rvfi_rd_addr)
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rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += rd_wdata.eq(self.rvfi_rd_wdata)
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pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata)
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pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata)
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insn = self.rvfi_insn
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trap = self.rvfi_trap
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halt = self.rvfi_halt
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intr = self.rvfi_intr
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rs1_addr = self.rvfi_rs1_addr
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rs2_addr = self.rvfi_rs2_addr
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rs1_rdata = self.rvfi_rs1_rdata
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rs2_rdata = self.rvfi_rs2_rdata
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rd_addr = self.rvfi_rd_addr
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rd_wdata = self.rvfi_rd_wdata
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pc_rdata = self.rvfi_pc_rdata
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pc_wdata = self.rvfi_pc_wdata
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mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += mem_addr.eq(self.rvfi_mem_addr)
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mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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m.d.comb += mem_rmask.eq(self.rvfi_mem_rmask)
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mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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m.d.comb += mem_wmask.eq(self.rvfi_mem_wmask)
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mem_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += mem_rdata.eq(self.rvfi_mem_rdata)
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mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += mem_wdata.eq(self.rvfi_mem_wdata)
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mem_addr = self.rvfi_mem_addr
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mem_rmask = self.rvfi_mem_rmask
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mem_wmask = self.rvfi_mem_wmask
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mem_rdata = self.rvfi_mem_rdata
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mem_wdata = self.rvfi_mem_wdata
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if self.RISCV_FORMAL_CSR_MISA:
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csr_misa_rdata = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += csr_misa_rdata.eq(self.rvfi_csr_misa_rdata)
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csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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m.d.comb += csr_misa_rmask.eq(self.rvfi_csr_misa_rmask)
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spec_csr_misa_rmask = Signal(self.RISCV_FORMAL_XLEN)
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if self.params.csr_misa:
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csr_misa_rdata = self.rvfi_csr_misa_rdata
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csr_misa_rmask = self.rvfi_csr_misa_rmask
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spec_csr_misa_rmask = Signal(self.params.xlen)
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spec_valid = Signal(1)
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spec_trap = Signal(1)
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spec_rs1_addr = Signal(5)
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spec_rs2_addr = Signal(5)
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spec_rd_addr = Signal(5)
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spec_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_mem_addr = Signal(self.RISCV_FORMAL_XLEN)
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spec_mem_rmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_mem_wmask = Signal(int(self.RISCV_FORMAL_XLEN // 8))
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spec_mem_wdata = Signal(self.RISCV_FORMAL_XLEN)
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spec_rd_wdata = Signal(self.params.xlen)
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spec_pc_wdata = Signal(self.params.xlen)
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spec_mem_addr = Signal(self.params.xlen)
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spec_mem_rmask = Signal(int(self.params.xlen // 8))
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spec_mem_wmask = Signal(int(self.params.xlen // 8))
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spec_mem_wdata = Signal(self.params.xlen)
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rs1_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN)
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rs1_rdata_or_zero = Signal(self.params.xlen)
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m.d.comb += rs1_rdata_or_zero.eq(Mux(spec_rs1_addr != 0, rs1_rdata, 0))
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rs2_rdata_or_zero = Signal(self.RISCV_FORMAL_XLEN)
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rs2_rdata_or_zero = Signal(self.params.xlen)
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m.d.comb += rs2_rdata_or_zero.eq(Mux(spec_rs2_addr != 0, rs2_rdata, 0))
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try:
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m.submodules.insn_spec = insn_spec = self.insn_model(RISCV_FORMAL_ILEN=self.RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN=self.RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA=self.RISCV_FORMAL_CSR_MISA)
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except:
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try:
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m.submodules.insn_spec = insn_spec = self.insn_model(RISCV_FORMAL_ILEN=self.RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN=self.RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA=self.RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_COMPRESSED=self.RISCV_FORMAL_COMPRESSED)
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except:
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m.submodules.insn_spec = insn_spec = self.insn_model(RISCV_FORMAL_ILEN=self.RISCV_FORMAL_ILEN, RISCV_FORMAL_XLEN=self.RISCV_FORMAL_XLEN, RISCV_FORMAL_CSR_MISA=self.RISCV_FORMAL_CSR_MISA, RISCV_FORMAL_ALIGNED_MEM=self.RISCV_FORMAL_ALIGNED_MEM)
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m.submodules.insn_spec = insn_spec = self.insn_model(self.params)
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m.d.comb += insn_spec.rvfi_valid.eq(valid)
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m.d.comb += insn_spec.rvfi_insn.eq(insn)
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@ -164,7 +137,7 @@ class InsnCheck(Elaboratable):
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m.d.comb += insn_spec.rvfi_rs2_rdata.eq(rs2_rdata_or_zero)
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m.d.comb += insn_spec.rvfi_mem_rdata.eq(mem_rdata)
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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m.d.comb += insn_spec.rvfi_csr_misa_rdata.eq(csr_misa_rdata)
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m.d.comb += spec_csr_misa_rmask.eq(insn_spec.spec_csr_misa_rmask)
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@ -208,7 +181,7 @@ class InsnCheck(Elaboratable):
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m.d.comb += Assert(rd_wdata == 0)
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m.d.comb += Assert(mem_wmask == 0)
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with m.Else():
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if self.RISCV_FORMAL_CSR_MISA:
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if self.params.csr_misa:
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m.d.comb += Assert((spec_csr_misa_rmask & csr_misa_rmask) == spec_csr_misa_rmask)
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with m.If(rs1_addr == 0):
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@ -231,7 +204,7 @@ class InsnCheck(Elaboratable):
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with m.If(spec_mem_wmask | spec_mem_rmask):
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m.d.comb += Assert(self.rvformal_addr_eq(spec_mem_addr, mem_addr))
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for i in range(int(self.RISCV_FORMAL_XLEN // 8)):
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for i in range(int(self.params.xlen // 8)):
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with m.If(spec_mem_wmask[i]):
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m.d.comb += Assert(mem_wmask[i])
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m.d.comb += Assert(spec_mem_wdata[i*8:i*8+8] == mem_wdata[i*8:i*8+8])
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@ -6,9 +6,9 @@ PC Backward Check
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"""
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class PcBwdCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_XLEN, rvformal_addr_valid):
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# Core-specific constants
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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def __init__(self, params, rvformal_addr_valid):
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# Core-specific parameters
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self.params = params
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# Address validity and equality
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self.rvformal_addr_valid = rvformal_addr_valid
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@ -19,8 +19,9 @@ class PcBwdCheck(Elaboratable):
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_pc_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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@ -31,14 +32,15 @@ class PcBwdCheck(Elaboratable):
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self.rvfi_pc_wdata
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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insn_order = AnyConst(64)
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expect_pc = Signal(self.RISCV_FORMAL_XLEN)
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expect_pc = Signal(self.params.xlen)
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expect_pc_valid = Signal(1, reset=0)
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pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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pc_wdata = Signal(self.params.xlen)
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m.d.comb += pc_wdata.eq(self.rvfi_pc_wdata)
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with m.If(self.reset):
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@ -6,9 +6,9 @@ PC Forward Check
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"""
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class PcFwdCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_XLEN, rvformal_addr_valid):
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# Core-specific constants
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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def __init__(self, params, rvformal_addr_valid):
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# Core-specific parameters
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self.params = params
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# Address validity and equality
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self.rvformal_addr_valid = rvformal_addr_valid
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@ -19,8 +19,9 @@ class PcFwdCheck(Elaboratable):
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self.check = Signal(1)
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_pc_rdata = Signal(self.params.xlen)
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self.rvfi_pc_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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@ -31,14 +32,15 @@ class PcFwdCheck(Elaboratable):
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self.rvfi_pc_wdata
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]
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return input_ports
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def elaborate(self, platform):
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m = Module()
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insn_order = AnyConst(64)
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expect_pc = Signal(self.RISCV_FORMAL_XLEN)
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expect_pc = Signal(self.params.xlen)
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expect_pc_valid = Signal(1, reset=0)
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pc_rdata = Signal(self.RISCV_FORMAL_XLEN)
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pc_rdata = Signal(self.params.xlen)
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m.d.comb += pc_rdata.eq(self.rvfi_pc_rdata)
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with m.If(self.reset):
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@ -6,9 +6,9 @@ Register Check
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"""
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class RegCheck(Elaboratable):
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def __init__(self, RISCV_FORMAL_XLEN):
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# Core-specific constants
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self.RISCV_FORMAL_XLEN = RISCV_FORMAL_XLEN
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def __init__(self, params):
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# Core-specific parameters
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self.params = params
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# Input ports
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self.reset = Signal(1)
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@ -16,11 +16,12 @@ class RegCheck(Elaboratable):
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self.rvfi_valid = Signal(1)
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self.rvfi_order = Signal(64)
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self.rvfi_rs1_addr = Signal(5)
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self.rvfi_rs1_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs1_rdata = Signal(self.params.xlen)
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self.rvfi_rs2_addr = Signal(5)
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self.rvfi_rs2_rdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rs2_rdata = Signal(self.params.xlen)
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self.rvfi_rd_addr = Signal(5)
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self.rvfi_rd_wdata = Signal(self.RISCV_FORMAL_XLEN)
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self.rvfi_rd_wdata = Signal(self.params.xlen)
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def ports(self):
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input_ports = [
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self.reset,
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@ -35,12 +36,13 @@ class RegCheck(Elaboratable):
|
|||
self.rvfi_rd_wdata
|
||||
]
|
||||
return input_ports
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
insn_order = AnyConst(64)
|
||||
register_index = AnyConst(5)
|
||||
register_shadow = Signal(self.RISCV_FORMAL_XLEN, reset=0)
|
||||
register_shadow = Signal(self.params.xlen, reset=0)
|
||||
register_written = Signal(1, reset=0)
|
||||
|
||||
with m.If(self.reset):
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -93,10 +93,10 @@ Below is a list of instructions currently supported by this port of the riscv-fo
|
|||
|
||||
The following core-specific parameters are currently supported:
|
||||
|
||||
| Constant | Description | Valid value(s) |
|
||||
| Parameter | Description | Valid value(s) |
|
||||
| --- | --- | --- |
|
||||
| `RISCV_FORMAL_ILEN` | Max length of instruction retired by core | `32` |
|
||||
| `RISCV_FORMAL_XLEN` | Width of integer registers | `32` |
|
||||
| `RISCV_FORMAL_CSR_MISA` | Support for MISA CSRs enabled | `True`, `False` |
|
||||
| `RISCV_FORMAL_COMPRESSED` | Support for compressed instructions | `True`, `False` |
|
||||
| `RISCV_FORMAL_ALIGNED_MEM` | Require aligned memory accesses | `True`, `False` |
|
||||
| `params.ilen` | Max length of instruction retired by core | `32` |
|
||||
| `params.xlen` | Width of integer registers | `32` |
|
||||
| `params.csr_misa` | Support for MISA CSRs enabled | `True`, `False` |
|
||||
| `params.compressed` | Support for compressed instructions | `True`, `False` |
|
||||
| `params.aligned_mem` | Require aligned memory accesses | `True`, `False` |
|
||||
|
|
|
@ -11,6 +11,6 @@ class InsnSll(InsnRV32IRType):
|
|||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata << Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
|
||||
return m
|
||||
|
|
|
@ -11,6 +11,6 @@ class InsnSra(InsnRV32IRType):
|
|||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) # https://stackoverflow.com/a/25207042
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5])) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.params.xlen - Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]))), 0)) # https://stackoverflow.com/a/25207042
|
||||
|
||||
return m
|
||||
|
|
|
@ -11,6 +11,6 @@ class InsnSrai(InsnRV32IITypeShift):
|
|||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> self.insn_shamt) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.RISCV_FORMAL_XLEN - self.insn_shamt)), 0))
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, (Value.as_signed(self.rvfi_rs1_rdata) >> self.insn_shamt) | (-(Value.as_signed(self.rvfi_rs1_rdata) < 0) << (self.params.xlen - self.insn_shamt)), 0))
|
||||
|
||||
return m
|
||||
|
|
|
@ -11,6 +11,6 @@ class InsnSrl(InsnRV32IRType):
|
|||
def elaborate(self, platform):
|
||||
m = super().elaborate(platform)
|
||||
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.RISCV_FORMAL_XLEN == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
m.d.comb += self.spec_rd_wdata.eq(Mux(self.spec_rd_addr, self.rvfi_rs1_rdata >> Mux(self.params.xlen == 64, self.rvfi_rs2_rdata[:6], self.rvfi_rs2_rdata[:5]), 0))
|
||||
|
||||
return m
|
||||
|
|
Loading…
Reference in New Issue