riscv-formal-nmigen

A port of riscv-formal to nMigen

Breakdown

File/Directory	Description
shell.nix	nix-shell configuration file
rvfi	RISC-V Formal Verification Framework (nMigen port)
rvfi/insns	Supported RISC-V instructions and ISAs
rvfi/checks	Checks for RISC-V compliant cores
rvfi/cores	Cores currently tested against this port of riscv-formal
rvfi/cores/minerva/verify.py	Verification tasks for the Minerva core

Running the Verification

First make sure you have Nix installed. Then cd to the root directory of this repo and run:

$ nix-shell

This should run the tests (cache, multiplier, divider) provided by Minerva itself and give you an environment with all the dependencies required for this project. Then, to run the main verification tasks for Minerva provided in this repo:

$ python -m rvfi.cores.minerva.verify

This should run in the order of a few minutes.

Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

Known Issues

As of 21/08/2020, the verification passes unconditionally, even when obvious, deliberate bugs are introduced to the Minerva core and/or its components thereof (such as replacing subtraction with addition in the adder). This is caused by the Minerva core having its rvfi.valid signal de-asserted all of the time. The cause of this issue is very likely due to the absence of proper interrupt signals and instruction + data buses, which must be connected to the core for it to function properly. Perhaps the issue could be solved by constructing abstract instruction + data buses with suitable assumed properties and connecting those abstract interfaces to the Minerva core (but then, what would those properties be?).

License

See LICENSE