A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen

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README.md

riscv-formal-nmigen

A port of riscv-formal to nMigen

Breakdown

Directory	Description
`shell.nix`	nix-shell configuration file
`rvfi`	RISC-V Formal Verification Framework (nMigen port)
`rvfi/insns`	Supported RISC-V instructions and ISAs
`rvfi/checks`	Checks for RISC-V compliant cores
`rvfi/cores`	Cores currently tested against this port of riscv-formal
`rvfi/cores/minerva`	Tests for the Minerva core

Running the Verification

First make sure you have Nix installed. Then cd to the root directory of this repo and run:

$ nix-shell

This should run the tests (cache, multiplier, divider) provided by Minerva itself and give you an environment with all the dependencies required for this project. Then, to run the main verification tasks for Minerva provided in this repo:

$ python -m rvfi.cores.minerva.verify

This should run in an order of a few minutes.

Scope

Support for the RV32I base ISA and RV32M extension are planned and well underway. Support for other ISAs in the original riscv-formal such as RV32C and their 64-bit counterparts may also be added in the future as time permits.

License

See LICENSE