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DRTIO: RTIO/SYS clock merge, KC705
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parent
17efc28dbe
commit
3838dfc1d1
@ -63,40 +63,12 @@ fn get_rtio_clock_cfg() -> RtioClock {
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#[cfg(has_rtio_crg)]
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pub mod crg {
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#[cfg(has_rtio_clock_switch)]
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use super::RtioClock;
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use board_misoc::{clock, csr};
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pub fn check() -> bool {
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unsafe { csr::rtio_crg::pll_locked_read() != 0 }
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}
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#[cfg(has_rtio_clock_switch)]
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pub fn init(clk: RtioClock) -> bool {
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let clk_sel: u8 = match clk {
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RtioClock::Ext0_Bypass => {
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info!("Using external clock");
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1
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},
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RtioClock::Int_125 => {
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info!("Using internal RTIO clock");
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0
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},
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_ => {
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warn!("rtio_clock setting '{:?}' is not supported. Using default internal RTIO clock instead", clk);
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0
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}
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};
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unsafe {
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csr::rtio_crg::pll_reset_write(1);
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csr::rtio_crg::clock_sel_write(clk_sel);
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csr::rtio_crg::pll_reset_write(0);
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}
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clock::spin_us(150);
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return check()
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}
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#[cfg(not(has_rtio_clock_switch))]
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pub fn init() -> bool {
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info!("Using internal RTIO clock");
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unsafe {
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@ -223,7 +195,7 @@ fn setup_si5324(clock_cfg: RtioClock) {
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#[cfg(soc_platform = "metlino")]
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let si5324_ext_input = si5324::Input::Ckin2;
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#[cfg(soc_platform = "kc705")]
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let si5324_ext_input = si5324::Input::Ckin2;
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let si5324_ext_input = si5324::Input::Ckin1;
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match clock_cfg {
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RtioClock::Ext0_Bypass => {
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info!("using external RTIO clock with PLL bypass");
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@ -277,9 +249,6 @@ pub fn init() {
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#[cfg(has_rtio_crg)]
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{
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#[cfg(has_rtio_clock_switch)]
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let result = crg::init(clock_cfg);
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#[cfg(not(has_rtio_clock_switch))]
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let result = crg::init();
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if !result {
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error!("RTIO clock failed");
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@ -426,19 +426,6 @@ fn hardware_tick(ts: &mut u64) {
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}
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}
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#[cfg(all(has_si5324, rtio_frequency = "150.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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n1_hs : 6,
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nc1_ls : 6,
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n2_hs : 10,
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n2_ls : 270,
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n31 : 75,
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n32 : 75,
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bwsel : 4,
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crystal_ref: true
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};
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#[cfg(all(has_si5324, rtio_frequency = "125.0"))]
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const SI5324_SETTINGS: si5324::FrequencySettings
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= si5324::FrequencySettings {
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@ -1,5 +1,6 @@
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.genlib.cdc import MultiReg
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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@ -16,13 +17,12 @@ class GTX_20X(Module):
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# * GTX PLL frequency @ 2.5GHz
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# * GTX line rate (TX & RX) @ 2.5Gb/s
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# * GTX TX/RX USRCLK @ 125MHz == coarse RTIO frequency
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def __init__(self, refclk, pads, sys_clk_freq, rtio_clk_freq=125e6, tx_mode="single", rx_mode="single"):
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def __init__(self, refclk, pads, clk_freq=125e6, tx_mode="single", rx_mode="single"):
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assert tx_mode in ["single", "master", "slave"]
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assert rx_mode in ["single", "master", "slave"]
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self.txenable = Signal()
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self.submodules.encoder = ClockDomainsRenamer("rtio_tx")(
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Encoder(2, True))
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self.submodules.encoder = Encoder(2, True)
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self.submodules.decoders = [ClockDomainsRenamer("rtio_rx")(
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(Decoder(True))) for _ in range(2)]
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self.rx_ready = Signal()
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@ -36,11 +36,11 @@ class GTX_20X(Module):
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cpllreset = Signal()
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cplllock = Signal()
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# TX generates RTIO clock, init must be in system domain
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self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode)
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# RX receives restart commands from RTIO domain
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self.submodules.rx_init = rx_init = ClockDomainsRenamer("rtio_tx")(
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GTXInit(rtio_clk_freq, True, mode=rx_mode))
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# TX generates SYS clock, init must be in bootstrap domain
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self.submodules.tx_init = tx_init = ClockDomainsRenamer("bootstrap")(
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GTXInit(clk_freq, False, mode=tx_mode))
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# RX receives restart commands from SYS domain
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self.submodules.rx_init = rx_init = GTXInit(clk_freq, True, mode=rx_mode)
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self.comb += [
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cpllreset.eq(tx_init.cpllreset),
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tx_init.cplllock.eq(cplllock),
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@ -113,8 +113,8 @@ class GTX_20X(Module):
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i_TXCHARDISPMODE=Cat(txdata[9], txdata[19]),
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i_TXCHARDISPVAL=Cat(txdata[8], txdata[18]),
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i_TXDATA=Cat(txdata[:8], txdata[10:18]),
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i_TXUSRCLK=ClockSignal("rtio_tx"),
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i_TXUSRCLK2=ClockSignal("rtio_tx"),
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i_TXUSRCLK=ClockSignal("sys"),
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i_TXUSRCLK2=ClockSignal("sys"),
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# TX electrical
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i_TXBUFDIFFCTRL=0b100,
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@ -247,19 +247,10 @@ class GTX_20X(Module):
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p_ES_EYE_SCAN_EN="TRUE", # Must be TRUE for GTX
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)
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# TX clocking
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tx_reset_deglitched = Signal()
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tx_reset_deglitched.attr.add("no_retiming")
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.clock_domains.cd_rtio_tx = ClockDomain()
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if tx_mode == "single" or tx_mode == "master":
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self.specials += Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk)
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self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)
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# RX clocking
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rx_reset_deglitched = Signal()
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rx_reset_deglitched.attr.add("no_retiming")
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self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
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self.sync += rx_reset_deglitched.eq(~rx_init.done)
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self.clock_domains.cd_rtio_rx = ClockDomain()
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if rx_mode == "single" or rx_mode == "master":
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self.specials += Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx.clk),
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@ -271,7 +262,7 @@ class GTX_20X(Module):
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self.decoders[1].input.eq(rxdata[10:])
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]
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clock_aligner = BruteforceClockAligner(0b0101111100, rtio_clk_freq)
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clock_aligner = BruteforceClockAligner(0b0101111100, clk_freq)
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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@ -282,17 +273,18 @@ class GTX_20X(Module):
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class GTX(Module, TransceiverInterface):
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def __init__(self, clock_pads, pads, sys_clk_freq, rtio_clk_freq=125e6, master=0):
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def __init__(self, clock_pads, pads, clk_freq=125e6, master=0):
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self.nchannels = nchannels = len(pads)
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self.gtxs = []
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self.rtio_clk_freq = rtio_clk_freq
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self.rtio_clk_freq = clk_freq
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# # #
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refclk = Signal()
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stable_clkin_n = Signal()
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clk_enable = Signal()
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self.specials += Instance("IBUFDS_GTE2",
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i_CEB=stable_clkin_n,
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i_CEB=~clk_enable,
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i_I=clock_pads.p,
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i_IB=clock_pads.n,
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o_O=refclk,
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@ -301,7 +293,6 @@ class GTX(Module, TransceiverInterface):
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p_CLKSWING_CFG="0b11"
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)
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rtio_tx_clk = Signal()
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channel_interfaces = []
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for i in range(nchannels):
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if nchannels == 1:
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@ -309,12 +300,7 @@ class GTX(Module, TransceiverInterface):
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else:
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mode = "master" if i == master else "slave"
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# Note: RX phase alignment is to be done on individual lanes, not multi-lane.
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gtx = GTX_20X(refclk, pads[i], sys_clk_freq, rtio_clk_freq=rtio_clk_freq, tx_mode=mode, rx_mode="single")
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# Fan-out (to slave) / Fan-in (from master) of the TXUSRCLK
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if mode == "slave":
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self.comb += gtx.cd_rtio_tx.clk.eq(rtio_tx_clk)
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else:
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self.comb += rtio_tx_clk.eq(gtx.cd_rtio_tx.clk)
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gtx = GTX_20X(refclk, pads[i], clk_freq, tx_mode=mode, rx_mode="single")
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self.gtxs.append(gtx)
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setattr(self.submodules, "gtx"+str(i), gtx)
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channel_interface = ChannelInterface(gtx.encoder, gtx.decoders)
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@ -326,15 +312,16 @@ class GTX(Module, TransceiverInterface):
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TransceiverInterface.__init__(self, channel_interfaces)
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for n, gtx in enumerate(self.gtxs):
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self.comb += [
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stable_clkin_n.eq(~self.stable_clkin.storage),
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gtx.txenable.eq(self.txenable.storage[n])
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gtx.txenable.eq(self.txenable.storage[n]),
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gtx.tx_init.stable_clkin.eq(clk_enable)
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]
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# rx_init is in SYS domain, rather than bootstrap
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self.specials += MultiReg(clk_enable, gtx.rx_init.stable_clkin)
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# stable_clkin resets after reboot since it's in SYS domain
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# still need to keep clk_enable high after this
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self.sync.bootstrap += clk_enable.eq(self.stable_clkin.storage | self.gtxs[0].tx_init.done)
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# Connect master's `rtio_tx` clock to `rtio` clock
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self.comb += [
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self.cd_rtio.clk.eq(self.gtxs[master].cd_rtio_tx.clk),
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self.cd_rtio.rst.eq(reduce(or_, [gtx.cd_rtio_tx.rst for gtx in self.gtxs]))
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]
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# Connect slave i's `rtio_rx` clock to `rtio_rxi` clock
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for i in range(nchannels):
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self.comb += [
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@ -11,11 +11,13 @@ class GTXInit(Module):
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# Choose between Auto Mode and Manual Mode for TX/RX phase alignment with buffer bypassed:
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# * Auto Mode: When only single lane is involved, as suggested by Xilinx (AR59612)
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# * Manual Mode: When only multi-lane is involved, as suggested by Xilinx (AR59612)
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def __init__(self, sys_clk_freq, rx, mode="single"):
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def __init__(self, clk_freq, rx, mode="single"):
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assert isinstance(rx, bool)
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assert mode in ["single", "master", "slave"]
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self.mode = mode
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self.stable_clkin = Signal()
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self.done = Signal()
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self.restart = Signal()
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@ -83,13 +85,13 @@ class GTXInit(Module):
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# After configuration, transceiver resets have to stay low for
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# at least 500ns (see AR43482)
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startup_cycles = ceil(500*sys_clk_freq/1000000000)
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startup_cycles = ceil(500*clk_freq/1000000000)
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startup_timer = WaitTimer(startup_cycles)
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self.submodules += startup_timer
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# PLL reset should be 1 period of refclk
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# (i.e. 1/(125MHz) for the case of RTIO @ 125MHz)
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pll_reset_cycles = ceil(sys_clk_freq/125e6)
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pll_reset_cycles = ceil(clk_freq/125e6)
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pll_reset_timer = WaitTimer(pll_reset_cycles)
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self.submodules += pll_reset_timer
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@ -108,7 +110,7 @@ class GTXInit(Module):
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startup_fsm.act("INITIAL",
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startup_timer.wait.eq(1),
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If(startup_timer.done, NextState("RESET_ALL"))
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If(startup_timer.done & self.stable_clkin, NextState("RESET_ALL"))
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)
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startup_fsm.act("RESET_ALL",
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gtXxreset.eq(1),
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@ -24,65 +24,20 @@ from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer
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from artiq.gateware.drtio import *
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from artiq.build_soc import *
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class _RTIOCRG(Module, AutoCSR):
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def __init__(self, platform, rtio_internal_clk, use_sma=True):
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self._clock_sel = CSRStorage()
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self._pll_reset = CSRStorage(reset=1)
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self._pll_locked = CSRStatus()
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self.clock_domains.cd_rtio = ClockDomain()
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self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
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# 100 MHz when using 125MHz input
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self.clock_domains.cd_ext_clkout = ClockDomain(reset_less=True)
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platform.add_period_constraint(self.cd_ext_clkout.clk, 5.0)
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if use_sma:
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ext_clkout = platform.request("user_sma_gpio_p_33")
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self.sync.ext_clkout += ext_clkout.eq(~ext_clkout)
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rtio_external_clk = Signal()
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if use_sma:
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user_sma_clock = platform.request("user_sma_clock")
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platform.add_period_constraint(user_sma_clock.p, 8.0)
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self.specials += Instance("IBUFDS",
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i_I=user_sma_clock.p, i_IB=user_sma_clock.n,
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o_O=rtio_external_clk)
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pll_locked = Signal()
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rtio_clk = Signal()
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rtiox4_clk = Signal()
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ext_clkout_clk = Signal()
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class SMAClkinForward(Module):
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def __init__(self, platform):
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sma_clkin = platform.request("user_sma_clock")
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sma_clkin_se = Signal()
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sma_clkin_buffered = Signal()
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cdr_clk_se = Signal()
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cdr_clk = platform.request("si5324_clkin_33")
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self.specials += [
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Instance("PLLE2_ADV",
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p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
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p_REF_JITTER1=0.01,
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p_CLKIN1_PERIOD=8.0, p_CLKIN2_PERIOD=8.0,
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i_CLKIN1=rtio_internal_clk, i_CLKIN2=rtio_external_clk,
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# Warning: CLKINSEL=0 means CLKIN2 is selected
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i_CLKINSEL=~self._clock_sel.storage,
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# VCO @ 1GHz when using 125MHz input
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p_CLKFBOUT_MULT=8, p_DIVCLK_DIVIDE=1,
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i_CLKFBIN=self.cd_rtio.clk,
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i_RST=self._pll_reset.storage,
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o_CLKFBOUT=rtio_clk,
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p_CLKOUT0_DIVIDE=2, p_CLKOUT0_PHASE=0.0,
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o_CLKOUT0=rtiox4_clk,
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p_CLKOUT1_DIVIDE=5, p_CLKOUT1_PHASE=0.0,
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o_CLKOUT1=ext_clkout_clk),
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Instance("BUFG", i_I=rtio_clk, o_O=self.cd_rtio.clk),
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Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
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Instance("BUFG", i_I=ext_clkout_clk, o_O=self.cd_ext_clkout.clk),
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AsyncResetSynchronizer(self.cd_rtio, ~pll_locked),
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MultiReg(pll_locked, self._pll_locked.status)
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Instance("IBUFDS", i_I=sma_clkin.p, i_IB=sma_clkin.n, o_O=sma_clkin_se),
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Instance("BUFG", i_I=sma_clkin_se, o_O=sma_clkin_buffered),
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Instance("ODDR", i_C=sma_clkin_buffered, i_CE=1, i_D1=0, i_D2=1, o_Q=cdr_clk_se),
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Instance("OBUFDS", i_I=cdr_clk_se, o_O=cdr_clk.p, o_OB=cdr_clk.n)
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]
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# The default voltage for these signals on KC705 is 2.5V, and the Migen platform
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# follows this default. But since the SMAs are on the same bank as the DDS,
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# which is set to 3.3V by reprogramming the KC705 power ICs, we need to
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@ -138,6 +93,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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integrated_sram_size=8192,
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ethmac_nrxslots=4,
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ethmac_ntxslots=4,
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rtio_sys_merge=True,
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**kwargs)
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AMPSoC.__init__(self)
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add_identifier(self, gateware_identifier_str=gateware_identifier_str)
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@ -149,6 +105,31 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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if isinstance(self.platform.toolchain, XilinxISEToolchain):
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self.platform.toolchain.bitgen_opt += " -g compress"
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self.platform.add_extension(_reprogrammed3v3_io)
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cdr_clk_out = self.platform.request("si5324_clkout")
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cdr_clk = Signal()
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cdr_clk_buf = Signal()
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self.config["HAS_SI5324"] = None
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n)
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self.csr_devices.append("si5324_rst_n")
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self.specials += [
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Instance("IBUFDS_GTE2",
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i_CEB=0,
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i_I=cdr_clk_out.p, i_IB=cdr_clk_out.n,
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o_O=cdr_clk,
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p_CLKCM_CFG=1,
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p_CLKRCV_TRST=1,
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p_CLKSWING_CFG="2'b11"),
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Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
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]
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self.crg.configure(cdr_clk_buf)
|
||||
|
||||
self.submodules += SMAClkinForward(self.platform)
|
||||
|
||||
self.submodules.timer1 = timer.Timer()
|
||||
self.csr_devices.append("timer1")
|
||||
self.interrupt_devices.append("timer1")
|
||||
@ -158,7 +139,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
|
||||
self.platform.request("user_led", 1)))
|
||||
self.csr_devices.append("leds")
|
||||
|
||||
self.platform.add_extension(_reprogrammed3v3_io)
|
||||
self.platform.add_extension(_ams101_dac)
|
||||
|
||||
i2c = self.platform.request("i2c")
|
||||
@ -169,9 +149,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
|
||||
self.config["HAS_DDS"] = None
|
||||
|
||||
def add_rtio(self, rtio_channels):
|
||||
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
self.config["HAS_RTIO_CLOCK_SWITCH"] = None
|
||||
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
||||
self.submodules.rtio_core = rtio.Core(self.rtio_tsc, rtio_channels)
|
||||
self.csr_devices.append("rtio_core")
|
||||
@ -187,11 +164,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
|
||||
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
|
||||
self.csr_devices.append("rtio_moninj")
|
||||
|
||||
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)
|
||||
self.platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
self.rtio_crg.cd_rtio.clk)
|
||||
|
||||
self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.rtio_core.cri,
|
||||
self.get_native_sdram_if(), cpu_dw=self.cpu_dw)
|
||||
self.csr_devices.append("rtio_analyzer")
|
||||
@ -208,6 +180,7 @@ class _MasterBase(MiniSoC, AMPSoC):
|
||||
mem_map.update(MiniSoC.mem_map)
|
||||
|
||||
def __init__(self, gateware_identifier_str=None, drtio_100mhz=False, **kwargs):
|
||||
clk_freq = 100e6 if drtio_100mhz else 125e6
|
||||
MiniSoC.__init__(self,
|
||||
cpu_type="vexriscv",
|
||||
cpu_bus_width=64,
|
||||
@ -216,6 +189,8 @@ class _MasterBase(MiniSoC, AMPSoC):
|
||||
integrated_sram_size=8192,
|
||||
ethmac_nrxslots=4,
|
||||
ethmac_ntxslots=4,
|
||||
clk_freq=clk_freq,
|
||||
rtio_sys_merge=True,
|
||||
**kwargs)
|
||||
AMPSoC.__init__(self)
|
||||
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
|
||||
@ -236,14 +211,11 @@ class _MasterBase(MiniSoC, AMPSoC):
|
||||
platform.request("sfp"), platform.request("user_sma_mgt")
|
||||
]
|
||||
|
||||
rtio_clk_freq = 100e6 if drtio_100mhz else 125e6
|
||||
|
||||
# 1000BASE_BX10 Ethernet compatible, 100/125MHz RTIO clock
|
||||
self.submodules.drtio_transceiver = gtx_7series.GTX(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
pads=data_pads,
|
||||
sys_clk_freq=self.clk_freq,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
clk_freq=self.clk_freq)
|
||||
self.csr_devices.append("drtio_transceiver")
|
||||
|
||||
self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3)
|
||||
@ -292,29 +264,31 @@ class _MasterBase(MiniSoC, AMPSoC):
|
||||
self.config["HAS_SI5324"] = None
|
||||
self.config["SI5324_AS_SYNTHESIZER"] = None
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
|
||||
]
|
||||
|
||||
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
|
||||
# Constrain TX & RX timing for the first transceiver channel
|
||||
# (First channel acts as master for phase alignment for all channels' TX)
|
||||
gtx0 = self.drtio_transceiver.gtxs[0]
|
||||
|
||||
txout_buf = Signal()
|
||||
self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
|
||||
self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(gtx0.txoutclk)
|
||||
]
|
||||
|
||||
platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
gtx0.txoutclk, gtx0.rxoutclk)
|
||||
self.crg.cd_sys.clk, gtx0.rxoutclk)
|
||||
# Constrain RX timing for the each transceiver channel
|
||||
# (Each channel performs single-lane phase alignment for RX)
|
||||
for gtx in self.drtio_transceiver.gtxs[1:]:
|
||||
platform.add_period_constraint(gtx.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, gtx0.txoutclk, gtx.rxoutclk)
|
||||
self.crg.cd_sys.clk, gtx.rxoutclk)
|
||||
|
||||
self.submodules.rtio_crg = RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
fix_serdes_timing_path(platform)
|
||||
|
||||
def add_rtio(self, rtio_channels):
|
||||
@ -345,12 +319,15 @@ class _SatelliteBase(BaseSoC):
|
||||
mem_map.update(BaseSoC.mem_map)
|
||||
|
||||
def __init__(self, gateware_identifier_str=None, sma_as_sat=False, drtio_100mhz=False, **kwargs):
|
||||
clk_freq = 100e6 if drtio_100mhz else 125e6
|
||||
BaseSoC.__init__(self,
|
||||
cpu_type="vexriscv",
|
||||
cpu_bus_width=64,
|
||||
sdram_controller_type="minicon",
|
||||
l2_size=128*1024,
|
||||
integrated_sram_size=8192,
|
||||
clk_freq=clk_freq,
|
||||
rtio_sys_merge=True,
|
||||
**kwargs)
|
||||
add_identifier(self, gateware_identifier_str=gateware_identifier_str)
|
||||
|
||||
@ -372,14 +349,13 @@ class _SatelliteBase(BaseSoC):
|
||||
if sma_as_sat:
|
||||
data_pads = data_pads[::-1]
|
||||
|
||||
rtio_clk_freq = 100e6 if drtio_100mhz else 125e6
|
||||
rtio_clk_freq = clk_freq
|
||||
|
||||
# 1000BASE_BX10 Ethernet compatible, 100/125MHz RTIO clock
|
||||
self.submodules.drtio_transceiver = gtx_7series.GTX(
|
||||
clock_pads=platform.request("si5324_clkout"),
|
||||
pads=data_pads,
|
||||
sys_clk_freq=self.clk_freq,
|
||||
rtio_clk_freq=rtio_clk_freq)
|
||||
clk_freq=self.clk_freq)
|
||||
self.csr_devices.append("drtio_transceiver")
|
||||
|
||||
self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3)
|
||||
@ -432,6 +408,7 @@ class _SatelliteBase(BaseSoC):
|
||||
self.submodules.siphaser = SiPhaser7Series(
|
||||
si5324_clkin=platform.request("si5324_clkin_33"),
|
||||
rx_synchronizer=self.rx_synchronizer,
|
||||
ref_clk=ClockSignal("bootstrap"),
|
||||
ultrascale=False,
|
||||
rtio_clk_freq=self.drtio_transceiver.rtio_clk_freq)
|
||||
platform.add_false_path_constraints(
|
||||
@ -445,20 +422,22 @@ class _SatelliteBase(BaseSoC):
|
||||
self.config["I2C_BUS_COUNT"] = 1
|
||||
self.config["HAS_SI5324"] = None
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
|
||||
]
|
||||
|
||||
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
|
||||
# Constrain TX & RX timing for the first transceiver channel
|
||||
# (First channel acts as master for phase alignment for all channels' TX)
|
||||
gtx0 = self.drtio_transceiver.gtxs[0]
|
||||
|
||||
txout_buf = Signal()
|
||||
self.specials += Instance("BUFG", i_I=gtx0.txoutclk, o_O=txout_buf)
|
||||
self.crg.configure(txout_buf, clk_sw=gtx0.tx_init.done)
|
||||
|
||||
self.comb += [
|
||||
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
|
||||
platform.request("user_sma_clock_n").eq(gtx0.txoutclk)
|
||||
]
|
||||
|
||||
platform.add_period_constraint(gtx0.txoutclk, rtio_clk_period)
|
||||
platform.add_period_constraint(gtx0.rxoutclk, rtio_clk_period)
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk,
|
||||
gtx0.txoutclk, gtx0.rxoutclk)
|
||||
# Constrain RX timing for the each transceiver channel
|
||||
# (Each channel performs single-lane phase alignment for RX)
|
||||
for gtx in self.drtio_transceiver.gtxs[1:]:
|
||||
@ -466,8 +445,6 @@ class _SatelliteBase(BaseSoC):
|
||||
platform.add_false_path_constraints(
|
||||
self.crg.cd_sys.clk, gtx.rxoutclk)
|
||||
|
||||
self.submodules.rtio_crg = RTIOClockMultiplier(self.drtio_transceiver.rtio_clk_freq)
|
||||
self.csr_devices.append("rtio_crg")
|
||||
fix_serdes_timing_path(platform)
|
||||
|
||||
def add_rtio(self, rtio_channels):
|
||||
|
||||
Loading…
Reference in New Issue
Block a user