M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-28 20:53:35 +08:00
Code Issues Projects Releases Wiki Activity

fix dt computation

Browse Source
This commit is contained in:
Robert Jördens 2022-09-06 14:32:57 +00:00
parent c26fa5eb90
commit 27e3c044ed
2 changed files with 8 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
artiq/coredevice/phaser.py
View File

@ -1469,13 +1469,13 @@ class Miqro:
data[0] = window
word = 0
idx = 10
for i in range(len(profiles)):
if profiles[i] > 0x1f:
for profile in profiles:
if profile > 0x1f:
raise ValueError("profile out of bounds")
if idx >= 30:
word += 1
idx = 0
data[word] |= (profiles[i] & 0x1f) << idx
data[word] |= profile << idx
idx += 5
return word

9
artiq/gateware/rtio/phy/phaser.py
View File

@ -99,6 +99,7 @@ class MiqroChannel(Module):
self.ack = Signal()
regs = [Signal(30, reset_less=True) for _ in range(3)]
dt = Signal(7, reset_less=True)
dt_frame = Signal(6, reset_less=True)
stb = Signal()
pulse = Cat(stb, dt, regs)
assert len(self.pulse) >= len(pulse)
@ -107,18 +108,18 @@ class MiqroChannel(Module):
self.rtlink.o.busy.eq(stb & ~self.ack),
]
self.sync.rtio += [
dt.eq(dt + 2),
dt_frame.eq(dt_frame + 1),
If(self.ack,
dt[1:].eq(0),
stb.eq(0),
dt_frame.eq(0),
If(stb,
[r.eq(0) for r in regs],
),
stb.eq(0),
),
If(self.rtlink.o.stb,
Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),
If(self.rtlink.o.address == 0,
dt[0].eq(self.rtlink.o.fine_ts),
dt.eq(Cat(self.rtlink.o.fine_ts, dt_frame)),
stb.eq(1),
),
),