simplify dt reset

2022-09-08 08:39:48 +02:00 · 2022-09-08 08:39:48 +02:00 · af28bf3550
parent 4df880faf6
commit af28bf3550
1 changed files with 2 additions and 2 deletions
--- a/artiq/gateware/rtio/phy/phaser.py
+++ b/artiq/gateware/rtio/phy/phaser.py
@ -111,11 +111,11 @@ class MiqroChannel(Module):
                dt.eq(dt + 2),
            ),
            If(self.ack,
-                dt.eq(0),
+                dt[1:].eq(0),
+                stb.eq(0),
                If(stb,
                    [r.eq(0) for r in regs],
                ),
-                stb.eq(0),
            ),
            If(self.rtlink.o.stb,
                Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),