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kc705: do not reset si5324 during clock switch

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mwojcik 2023-01-09 18:15:58 +08:00 committed by Sébastien Bourdeauducq
parent 63f1a6d197
commit eb3742fb08
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/targets/kc705.py
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@ -113,7 +113,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n)
self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n, reset_out=1)
self.csr_devices.append("si5324_rst_n")
self.specials += [
Instance("IBUFDS_GTE2",
@ -255,7 +255,7 @@ class _MasterBase(MiniSoC, AMPSoC):
self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
self.config["RTIO_FREQUENCY"] = str(self.drtio_transceiver.rtio_clk_freq/1e6)
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
@ -414,7 +414,7 @@ class _SatelliteBase(BaseSoC):
platform.add_false_path_constraints(
self.crg.cd_sys.clk, self.siphaser.mmcm_freerun_output)
self.csr_devices.append("siphaser")
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n)
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324_33").rst_n, reset_out=1)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")
self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])