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fix type, clean clear
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@ -1351,6 +1351,7 @@ class Miqro:
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idx = 0
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data[word] |= (profiles[i] & 0x1f) << idx
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idx += 5
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delay_mu(-8*word)
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while word >= 0:
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rtio_output(self.base_addr + word, data[word])
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delay_mu(8)
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@ -111,6 +111,9 @@ class MiqroChannel(Module):
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If(self.ack,
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dt[1:].eq(0),
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stb.eq(0),
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If(stb,
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[r.eq(0) for r in regs],
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),
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),
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If(self.rtlink.o.stb,
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Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data),
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@ -159,7 +162,7 @@ class Miqro(Module):
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re_dly = Signal(3) # stage, send, respond
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self.sync.rtio += [
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header.type.eq(1), # body type is miqro pulse data
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header.type.eq(3), # body type is miqro pulse data
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If(self.serializer.stb,
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header.we.eq(0),
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re_dly.eq(re_dly[1:]),
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