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echo test: add two more yields

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mwojcik 2023-01-10 17:17:39 +08:00 committed by Sébastien Bourdeauducq
parent cd860beda2
commit 9042426872
1 changed files with 1 additions and 1 deletions
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artiq/gateware/test/drtio/test_full_stack.py
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@ -303,7 +303,7 @@ class TestFullStack(unittest.TestCase):
yield
yield dut.master.rt_packet.echo_stb.eq(0)
for i in range(15):
for i in range(17):
yield
self.assertEqual((yield dut.master.rt_packet.packet_cnt_tx), 1)