echo test: add two more yields

2023-01-10 17:17:39 +08:00 · 2023-01-10 17:17:39 +08:00 · 9042426872
parent cd860beda2
commit 9042426872
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/test/drtio/test_full_stack.py
+++ b/artiq/gateware/test/drtio/test_full_stack.py
@ -303,7 +303,7 @@ class TestFullStack(unittest.TestCase):
                yield
            yield dut.master.rt_packet.echo_stb.eq(0)

-            for i in range(15):
+            for i in range(17):
                yield

            self.assertEqual((yield dut.master.rt_packet.packet_cnt_tx), 1)