mirror of
https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
dma test: no more rsys or rtio domains
This commit is contained in:
parent
458bd8a927
commit
f8eb695c0f
@ -203,11 +203,11 @@ class TestDMA(unittest.TestCase):
|
||||
run_simulation(tb[32], {"sys": [
|
||||
do_dma(tb[32].dut, 0), monitor(32),
|
||||
(None for _ in range(70)),
|
||||
]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8})
|
||||
]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8})
|
||||
run_simulation(tb[64], {"sys": [
|
||||
do_dma(tb[64].dut, 0), monitor(64),
|
||||
(None for _ in range(70)),
|
||||
]}, {"sys": 8, "rsys": 8, "rtio": 8, "rio": 8, "rio_phy": 8})
|
||||
]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8})
|
||||
|
||||
correct_changes = [(timestamp + 11, channel)
|
||||
for channel, timestamp, _, _ in test_writes_full_stack]
|
||||
|
Loading…
Reference in New Issue
Block a user