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https://github.com/m-labs/artiq.git
synced 2024-12-25 11:18:27 +08:00
rtio: remove rtio clock, use sys instead
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1eb87164be
commit
a6856a5e4a
@ -15,7 +15,7 @@ class GrayCodeTransfer(Module):
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# convert to Gray code
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value_gray_rtio = Signal(width, reset_less=True)
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self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
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self.sync += value_gray_rtio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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value_gray_rtio.attr.add("no_retiming")
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@ -24,7 +24,7 @@ class Core(Module, AutoCSR):
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self.sequence_error_channel = CSRStatus(16)
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# Clocking/Reset
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# Create rsys, rio and rio_phy domains based on sys and rtio
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# Create rio and rio_phy domains based on sys
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# with reset controlled by CSR.
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#
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# The `rio` CD contains logic that is reset with `core.reset()`.
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@ -40,20 +40,15 @@ class Core(Module, AutoCSR):
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cmd_reset.eq(self.reset.re),
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cmd_reset_phy.eq(self.reset_phy.re)
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]
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cmd_reset.attr.add("no_retiming")
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cmd_reset_phy.attr.add("no_retiming")
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(cmd_reset),
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self.cd_rio.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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self.cd_rio.clk.eq(ClockSignal()),
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self.cd_rio.rst.eq(cmd_reset),
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self.cd_rio_phy.clk.eq(ClockSignal()),
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self.cd_rio_phy.rst.eq(cmd_reset_phy)
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]
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self.specials += AsyncResetSynchronizer(self.cd_rio, cmd_reset)
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self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
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# TSC
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chan_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
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@ -65,7 +60,7 @@ class Core(Module, AutoCSR):
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# Outputs/Inputs
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quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]
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outputs = SED(channels, tsc.glbl_fine_ts_width, "async",
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outputs = SED(channels, tsc.glbl_fine_ts_width, "sync",
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quash_channels=quash_channels,
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lane_count=lane_count, fifo_depth=fifo_depth,
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interface=self.cri)
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@ -73,14 +68,14 @@ class Core(Module, AutoCSR):
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self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
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self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts_sys + 16)
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inputs = InputCollector(tsc, channels, "async",
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inputs = InputCollector(tsc, channels, "sync",
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quash_channels=quash_channels,
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interface=self.cri)
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self.submodules += inputs
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# Asychronous output errors
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o_collision_sync = BlindTransfer("rio", "rsys", data_width=16)
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o_busy_sync = BlindTransfer("rio", "rsys", data_width=16)
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o_collision_sync = BlindTransfer("rio", "sys", data_width=16)
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o_busy_sync = BlindTransfer("rio", "sys", data_width=16)
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self.submodules += o_collision_sync, o_busy_sync
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o_collision = Signal()
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o_busy = Signal()
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@ -155,10 +155,8 @@ class CRIDecoder(Module):
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if enable_routing:
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self.specials.routing_table = Memory(slave_bits, 256)
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if mode == "async":
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if mode == "async" or mode == "sync":
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rtp_decoder = self.routing_table.get_port()
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elif mode == "sync":
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rtp_decoder = self.routing_table.get_port(clock_domain="rtio")
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else:
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raise ValueError
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self.specials += rtp_decoder
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@ -199,12 +197,8 @@ class CRISwitch(Module, AutoCSR):
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# # #
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if mode == "async":
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if mode == "async" or mode == "sync":
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selected = self.selected.storage
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elif mode == "sync":
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self.selected.storage.attr.add("no_retiming")
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selected = Signal.like(self.selected.storage)
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self.specials += MultiReg(self.selected.storage, selected, "rtio")
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else:
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raise ValueError
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@ -36,9 +36,9 @@ class InputCollector(Module):
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sync_io = self.sync
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sync_cri = self.sync
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elif mode == "async":
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fifo_factory = lambda *args: ClockDomainsRenamer({"write": "rio", "read": "rsys"})(AsyncFIFO(*args))
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fifo_factory = lambda *args: ClockDomainsRenamer({"write": "rio", "read": "sys"})(AsyncFIFO(*args))
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sync_io = self.sync.rio
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sync_cri = self.sync.rsys
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sync_cri = self.sync.sys
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else:
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raise ValueError
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@ -85,7 +85,7 @@ class InputCollector(Module):
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if mode == "sync":
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overflow_trigger = overflow_io
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elif mode == "async":
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overflow_transfer = BlindTransfer("rio", "rsys")
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overflow_transfer = BlindTransfer("rio", "sys")
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self.submodules += overflow_transfer
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self.comb += overflow_transfer.i.eq(overflow_io)
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overflow_trigger = overflow_transfer.o
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@ -120,7 +120,7 @@ class Fastino(Module):
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),
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]
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self.sync.rtio += [
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self.sync += [
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self.rtlink.i.stb.eq(self.rtlink.o.stb &
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self.rtlink.o.address[-1]),
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self.rtlink.i.data.eq(
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@ -21,14 +21,12 @@ class Synchronizer(Module):
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# # #
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for count in counts_in:
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count.attr.add("no_retiming")
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self.specials += [MultiReg(i, o, "rtio") for i, o in zip(counts_in, self.counts)]
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self.comb += [o.eq(i) for i, o in zip(counts_in, self.counts)]
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ps = PulseSynchronizer("cl", "rtio")
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ps = PulseSynchronizer("cl", "sys")
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self.submodules += ps
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self.comb += ps.i.eq(roi_engines[0].out.update)
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self.sync.rtio += self.update.eq(ps.o)
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self.sync += self.update.eq(ps.o)
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class Serializer(Module):
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@ -85,7 +83,7 @@ class Grabber(Module):
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roi_engine.cfg.x1, roi_engine.cfg.y1]):
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roi_boundary = Signal.like(target)
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roi_boundary.attr.add("no_retiming")
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self.sync.rtio += If(self.config.o.stb & (self.config.o.address == 4*n+offset),
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self.sync += If(self.config.o.stb & (self.config.o.address == 4*n+offset),
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roi_boundary.eq(self.config.o.data))
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self.specials += MultiReg(roi_boundary, target, "cl")
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@ -10,7 +10,7 @@ class Phy(Module):
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self.rtlink = rtlink.Interface(
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rtlink.OInterface(data_width=32, address_width=4,
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enable_replace=True))
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self.sync.rtio += [
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self.sync += [
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If(self.rtlink.o.stb,
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Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data)
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)
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@ -70,7 +70,7 @@ class Base(Module):
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self.comb += self.serializer.payload.eq(Cat(header.raw_bits(), body))
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re_dly = Signal(3) # stage, send, respond
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self.sync.rtio += [
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self.sync += [
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header.type.eq(1), # body type is baseband data
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If(self.serializer.stb,
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self.ch0.dds.stb.eq(1), # synchronize
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@ -19,7 +19,7 @@ class _OSERDESE2_8X(Module):
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p_INIT_OQ=0b11111111 if invert else 0b00000000,
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o_OQ=self.ser_out, o_TQ=self.t_out,
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i_RST=ResetSignal("rio_phy"),
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i_CLK=ClockSignal("rtiox4"),
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i_CLK=ClockSignal("sys4x"),
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i_CLKDIV=ClockSignal("rio_phy"),
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i_D1=o[0] ^ invert, i_D2=o[1] ^ invert, i_D3=o[2] ^ invert, i_D4=o[3] ^ invert,
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i_D5=o[4] ^ invert, i_D6=o[5] ^ invert, i_D7=o[6] ^ invert, i_D8=o[7] ^ invert,
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@ -43,8 +43,8 @@ class _ISERDESE2_8X(Module):
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o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
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o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
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i_D=self.ser_in,
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i_CLK=ClockSignal("rtiox4"),
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i_CLKB=~ClockSignal("rtiox4"),
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i_CLK=ClockSignal("sys4x"),
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i_CLKB=~ClockSignal("sys4x"),
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i_CE1=1,
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i_RST=ResetSignal("rio_phy"),
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i_CLKDIV=ClockSignal("rio_phy"))
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@ -18,8 +18,8 @@ class _OSERDESE3(Module):
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p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
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o_OQ=self.ser_out, o_T_OUT=self.t_out,
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i_RST=ResetSignal("rtio"),
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i_CLK=ClockSignal("rtiox"), i_CLKDIV=ClockSignal("rtio"),
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i_RST=ResetSignal("sys"),
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i_CLK=ClockSignal("rtiox"), i_CLKDIV=ClockSignal("sys"),
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i_D=self.o, i_T=self.t_in)
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@ -39,11 +39,11 @@ class _ISERDESE3(Module):
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p_DATA_WIDTH=dw,
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i_D=self.ser_in,
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i_RST=ResetSignal("rtio"),
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i_RST=ResetSignal("sys"),
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i_FIFO_RD_EN=0,
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i_CLK=ClockSignal("rtiox"),
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i_CLK_B=ClockSignal("rtiox"), # locally inverted
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i_CLKDIV=ClockSignal("rtio"),
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i_CLKDIV=ClockSignal("sys"),
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o_Q=Cat(*[self.i[i] for i in reversed(range(dw))]))
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@ -20,8 +20,8 @@ class SED(Module):
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gates_cdr = lambda x: x
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output_driver_cdr = lambda x: x
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elif mode == "async":
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lane_dist_cdr = ClockDomainsRenamer("rsys")
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fifos_cdr = ClockDomainsRenamer({"write": "rsys", "read": "rio"})
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lane_dist_cdr = ClockDomainsRenamer("sys")
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fifos_cdr = ClockDomainsRenamer({"write": "sys", "read": "rio"})
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gates_cdr = ClockDomainsRenamer("rio")
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output_driver_cdr = ClockDomainsRenamer("rio")
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else:
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@ -30,7 +30,7 @@ class TSC(Module):
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# # #
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self.sync.rtio += If(self.load,
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self.sync += If(self.load,
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self.coarse_ts.eq(self.load_value)
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).Else(
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self.coarse_ts.eq(self.coarse_ts + 1)
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@ -17,7 +17,7 @@ class RTIOClockMultiplier(Module, AutoCSR):
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self.specials += [
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Instance("MMCME2_BASE",
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p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
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i_CLKIN1=ClockSignal("rtio"),
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i_CLKIN1=ClockSignal("sys"),
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i_RST=self.pll_reset.storage,
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o_LOCKED=pll_locked,
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