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rtio: remove rtio clock, use sys instead

pull/2045/head
mwojcik 2022-10-28 16:50:10 +08:00 committed by Sébastien Bourdeauducq
parent 1eb87164be
commit a6856a5e4a
12 changed files with 33 additions and 46 deletions
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2
artiq/gateware/rtio/cdc.py
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@ -15,7 +15,7 @@ class GrayCodeTransfer(Module):
# convert to Gray code
value_gray_rtio = Signal(width, reset_less=True)
self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
self.sync += value_gray_rtio.eq(self.i ^ self.i[1:])
# transfer to system clock domain
value_gray_sys = Signal(width)
value_gray_rtio.attr.add("no_retiming")

23
artiq/gateware/rtio/core.py
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@ -24,7 +24,7 @@ class Core(Module, AutoCSR):
self.sequence_error_channel = CSRStatus(16)
# Clocking/Reset
# Create rsys, rio and rio_phy domains based on sys and rtio
# Create rio and rio_phy domains based on sys
# with reset controlled by CSR.
#
# The `rio` CD contains logic that is reset with `core.reset()`.
@ -40,20 +40,15 @@ class Core(Module, AutoCSR):
cmd_reset.eq(self.reset.re),
cmd_reset_phy.eq(self.reset_phy.re)
]
cmd_reset.attr.add("no_retiming")
cmd_reset_phy.attr.add("no_retiming")
self.clock_domains.cd_rsys = ClockDomain()
self.clock_domains.cd_rio = ClockDomain()
self.clock_domains.cd_rio_phy = ClockDomain()
self.comb += [
self.cd_rsys.clk.eq(ClockSignal()),
self.cd_rsys.rst.eq(cmd_reset),
self.cd_rio.clk.eq(ClockSignal("rtio")),
self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
self.cd_rio.clk.eq(ClockSignal()),
self.cd_rio.rst.eq(cmd_reset),
self.cd_rio_phy.clk.eq(ClockSignal()),
self.cd_rio_phy.rst.eq(cmd_reset_phy)
]
self.specials += AsyncResetSynchronizer(self.cd_rio, cmd_reset)
self.specials += AsyncResetSynchronizer(self.cd_rio_phy, cmd_reset_phy)
# TSC
chan_fine_ts_width = max(max(rtlink.get_fine_ts_width(channel.interface.o)
@ -65,7 +60,7 @@ class Core(Module, AutoCSR):
# Outputs/Inputs
quash_channels = [n for n, c in enumerate(channels) if isinstance(c, LogChannel)]
outputs = SED(channels, tsc.glbl_fine_ts_width, "async",
outputs = SED(channels, tsc.glbl_fine_ts_width, "sync",
quash_channels=quash_channels,
lane_count=lane_count, fifo_depth=fifo_depth,
interface=self.cri)
@ -73,14 +68,14 @@ class Core(Module, AutoCSR):
self.comb += outputs.coarse_timestamp.eq(tsc.coarse_ts)
self.sync += outputs.minimum_coarse_timestamp.eq(tsc.coarse_ts_sys + 16)
inputs = InputCollector(tsc, channels, "async",
inputs = InputCollector(tsc, channels, "sync",
quash_channels=quash_channels,
interface=self.cri)
self.submodules += inputs
# Asychronous output errors
o_collision_sync = BlindTransfer("rio", "rsys", data_width=16)
o_busy_sync = BlindTransfer("rio", "rsys", data_width=16)
o_collision_sync = BlindTransfer("rio", "sys", data_width=16)
o_busy_sync = BlindTransfer("rio", "sys", data_width=16)
self.submodules += o_collision_sync, o_busy_sync
o_collision = Signal()
o_busy = Signal()

10
artiq/gateware/rtio/cri.py
View File

@ -155,10 +155,8 @@ class CRIDecoder(Module):
if enable_routing:
self.specials.routing_table = Memory(slave_bits, 256)
if mode == "async":
if mode == "async" or mode == "sync":
rtp_decoder = self.routing_table.get_port()
elif mode == "sync":
rtp_decoder = self.routing_table.get_port(clock_domain="rtio")
else:
raise ValueError
self.specials += rtp_decoder
@ -199,12 +197,8 @@ class CRISwitch(Module, AutoCSR):
# # #
if mode == "async":
if mode == "async" or mode == "sync":
selected = self.selected.storage
elif mode == "sync":
self.selected.storage.attr.add("no_retiming")
selected = Signal.like(self.selected.storage)
self.specials += MultiReg(self.selected.storage, selected, "rtio")
else:
raise ValueError

6
artiq/gateware/rtio/input_collector.py
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@ -36,9 +36,9 @@ class InputCollector(Module):
sync_io = self.sync
sync_cri = self.sync
elif mode == "async":
fifo_factory = lambda *args: ClockDomainsRenamer({"write": "rio", "read": "rsys"})(AsyncFIFO(*args))
fifo_factory = lambda *args: ClockDomainsRenamer({"write": "rio", "read": "sys"})(AsyncFIFO(*args))
sync_io = self.sync.rio
sync_cri = self.sync.rsys
sync_cri = self.sync.sys
else:
raise ValueError
@ -85,7 +85,7 @@ class InputCollector(Module):
if mode == "sync":
overflow_trigger = overflow_io
elif mode == "async":
overflow_transfer = BlindTransfer("rio", "rsys")
overflow_transfer = BlindTransfer("rio", "sys")
self.submodules += overflow_transfer
self.comb += overflow_transfer.i.eq(overflow_io)
overflow_trigger = overflow_transfer.o

2
artiq/gateware/rtio/phy/fastino.py
View File

@ -120,7 +120,7 @@ class Fastino(Module):
),
]
self.sync.rtio += [
self.sync += [
self.rtlink.i.stb.eq(self.rtlink.o.stb &
self.rtlink.o.address[-1]),
self.rtlink.i.data.eq(

10
artiq/gateware/rtio/phy/grabber.py
View File

@ -21,14 +21,12 @@ class Synchronizer(Module):
# # #
for count in counts_in:
count.attr.add("no_retiming")
self.specials += [MultiReg(i, o, "rtio") for i, o in zip(counts_in, self.counts)]
self.comb += [o.eq(i) for i, o in zip(counts_in, self.counts)]
ps = PulseSynchronizer("cl", "rtio")
ps = PulseSynchronizer("cl", "sys")
self.submodules += ps
self.comb += ps.i.eq(roi_engines[0].out.update)
self.sync.rtio += self.update.eq(ps.o)
self.sync += self.update.eq(ps.o)
class Serializer(Module):
@ -85,7 +83,7 @@ class Grabber(Module):
roi_engine.cfg.x1, roi_engine.cfg.y1]):
roi_boundary = Signal.like(target)
roi_boundary.attr.add("no_retiming")
self.sync.rtio += If(self.config.o.stb & (self.config.o.address == 4*n+offset),
self.sync += If(self.config.o.stb & (self.config.o.address == 4*n+offset),
roi_boundary.eq(self.config.o.data))
self.specials += MultiReg(roi_boundary, target, "cl")

4
artiq/gateware/rtio/phy/phaser.py
View File

@ -10,7 +10,7 @@ class Phy(Module):
self.rtlink = rtlink.Interface(
rtlink.OInterface(data_width=32, address_width=4,
enable_replace=True))
self.sync.rtio += [
self.sync += [
If(self.rtlink.o.stb,
Array(regs)[self.rtlink.o.address].eq(self.rtlink.o.data)
)
@ -70,7 +70,7 @@ class Base(Module):
self.comb += self.serializer.payload.eq(Cat(header.raw_bits(), body))
re_dly = Signal(3) # stage, send, respond
self.sync.rtio += [
self.sync += [
header.type.eq(1), # body type is baseband data
If(self.serializer.stb,
self.ch0.dds.stb.eq(1), # synchronize

6
artiq/gateware/rtio/phy/ttl_serdes_7series.py
View File

@ -19,7 +19,7 @@ class _OSERDESE2_8X(Module):
p_INIT_OQ=0b11111111 if invert else 0b00000000,
o_OQ=self.ser_out, o_TQ=self.t_out,
i_RST=ResetSignal("rio_phy"),
i_CLK=ClockSignal("rtiox4"),
i_CLK=ClockSignal("sys4x"),
i_CLKDIV=ClockSignal("rio_phy"),
i_D1=o[0] ^ invert, i_D2=o[1] ^ invert, i_D3=o[2] ^ invert, i_D4=o[3] ^ invert,
i_D5=o[4] ^ invert, i_D6=o[5] ^ invert, i_D7=o[6] ^ invert, i_D8=o[7] ^ invert,
@ -43,8 +43,8 @@ class _ISERDESE2_8X(Module):
o_Q1=i[7], o_Q2=i[6], o_Q3=i[5], o_Q4=i[4],
o_Q5=i[3], o_Q6=i[2], o_Q7=i[1], o_Q8=i[0],
i_D=self.ser_in,
i_CLK=ClockSignal("rtiox4"),
i_CLKB=~ClockSignal("rtiox4"),
i_CLK=ClockSignal("sys4x"),
i_CLKB=~ClockSignal("sys4x"),
i_CE1=1,
i_RST=ResetSignal("rio_phy"),
i_CLKDIV=ClockSignal("rio_phy"))

8
artiq/gateware/rtio/phy/ttl_serdes_ultrascale.py
View File

@ -18,8 +18,8 @@ class _OSERDESE3(Module):
p_IS_CLK_INVERTED=0, p_IS_CLKDIV_INVERTED=0, p_IS_RST_INVERTED=0,
o_OQ=self.ser_out, o_T_OUT=self.t_out,
i_RST=ResetSignal("rtio"),
i_CLK=ClockSignal("rtiox"), i_CLKDIV=ClockSignal("rtio"),
i_RST=ResetSignal("sys"),
i_CLK=ClockSignal("rtiox"), i_CLKDIV=ClockSignal("sys"),
i_D=self.o, i_T=self.t_in)
@ -39,11 +39,11 @@ class _ISERDESE3(Module):
p_DATA_WIDTH=dw,
i_D=self.ser_in,
i_RST=ResetSignal("rtio"),
i_RST=ResetSignal("sys"),
i_FIFO_RD_EN=0,
i_CLK=ClockSignal("rtiox"),
i_CLK_B=ClockSignal("rtiox"), # locally inverted
i_CLKDIV=ClockSignal("rtio"),
i_CLKDIV=ClockSignal("sys"),
o_Q=Cat(*[self.i[i] for i in reversed(range(dw))]))

4
artiq/gateware/rtio/sed/core.py
View File

@ -20,8 +20,8 @@ class SED(Module):
gates_cdr = lambda x: x
output_driver_cdr = lambda x: x
elif mode == "async":
lane_dist_cdr = ClockDomainsRenamer("rsys")
fifos_cdr = ClockDomainsRenamer({"write": "rsys", "read": "rio"})
lane_dist_cdr = ClockDomainsRenamer("sys")
fifos_cdr = ClockDomainsRenamer({"write": "sys", "read": "rio"})
gates_cdr = ClockDomainsRenamer("rio")
output_driver_cdr = ClockDomainsRenamer("rio")
else:

2
artiq/gateware/rtio/tsc.py
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@ -30,7 +30,7 @@ class TSC(Module):
# # #
self.sync.rtio += If(self.load,
self.sync += If(self.load,
self.coarse_ts.eq(self.load_value)
).Else(
self.coarse_ts.eq(self.coarse_ts + 1)

2
artiq/gateware/rtio/xilinx_clocking.py
View File

@ -17,7 +17,7 @@ class RTIOClockMultiplier(Module, AutoCSR):
self.specials += [
Instance("MMCME2_BASE",
p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
i_CLKIN1=ClockSignal("rtio"),
i_CLKIN1=ClockSignal("sys"),
i_RST=self.pll_reset.storage,
o_LOCKED=pll_locked,