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test_write_underflow: decrease underflow delay

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mwojcik 2023-01-11 11:56:21 +08:00 committed by Sébastien Bourdeauducq
parent 9042426872
commit 70edc9c5c6
2 changed files with 4 additions and 4 deletions
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2
artiq/gateware/drtio/core.py
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@ -77,7 +77,7 @@ class DRTIOSatellite(Module):
self.reset = CSRStorage(reset=1)
self.reset_phy = CSRStorage(reset=1)
self.tsc_loaded = CSR()
# master interface in the rtio domain
# master interface in the sys domain
self.cri = cri.Interface()
self.async_errors = Record(async_errors_layout)

6
artiq/gateware/test/drtio/test_full_stack.py
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@ -227,16 +227,16 @@ class TestFullStack(unittest.TestCase):
errors = yield from saterr.protocol_error.read()
self.assertEqual(errors, 0)
yield from csrs.underflow_margin.write(0)
tb.delay(100)
tb.delay(80)
yield from tb.write(42, 1)
for i in range(12):
for i in range(21):
yield
errors = yield from saterr.protocol_error.read()
underflow_channel = yield from saterr.underflow_channel.read()
underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read()
self.assertEqual(errors, 8) # write underflow
self.assertEqual(underflow_channel, 42)
self.assertEqual(underflow_timestamp_event, 100)
self.assertEqual(underflow_timestamp_event, 80)
yield from saterr.protocol_error.write(errors)
yield
errors = yield from saterr.protocol_error.read()