M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

kasli_generic: remove rtio clockdomain reference

This commit is contained in:
mwojcik 2022-10-28 16:51:41 +08:00 committed by Sébastien Bourdeauducq
parent a6856a5e4a
commit 458bd8a927
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/targets/kasli_generic.py
View File

@ -64,7 +64,7 @@ class GenericStandalone(StandaloneBase):
self.add_csr_group("grabber", self.grabber_csr_group)
for grabber in self.grabber_csr_group:
self.platform.add_false_path_constraints(
self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
self.crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
class GenericMaster(MasterBase):