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kasli_generic: remove rtio clockdomain reference
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@ -64,7 +64,7 @@ class GenericStandalone(StandaloneBase):
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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self.rtio_crg.cd_rtio.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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self.crg.cd_sys.clk, getattr(self, grabber).deserializer.cd_cl.clk)
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class GenericMaster(MasterBase):
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