Commit Graph

437 Commits

Author SHA1 Message Date
8c2c0a2027 clippy: allow missing safety doc (rtfm) 2019-11-24 15:04:29 +01:00
bda0ca26fb i2c/eeprom: lint 2019-11-24 14:55:20 +01:00
bors[bot]
d2f8b60c27
Merge #65
65: Tim2 late enable r=jordens a=jordens

does this work for you @cjbe?

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-24 13:33:50 +00:00
1140b4fb76 board: enable TIM2 late
This was triggered by moving log_init and adding i2c_init on top of
the existing ethernet setup/init after the timer setup and enable.
Thanks @cjbe for debugging.

Also move the RCC peripheral enable calls out of i2c and eth setup.

close #55
supersedes #62
2019-11-24 14:26:27 +01:00
bors[bot]
3cf4f2690c
Merge #64
64: boards.rs: dos2unix r=jordens a=jordens

bors r+

@cjbe heads up

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-24 13:25:08 +00:00
8e84e61ff3 boards.rs: dos2unix 2019-11-24 14:15:11 +01:00
bf65b5f14a default to k_p=1 on boot 2019-11-24 13:10:01 +00:00
ab1735950b fix memory safety issue in ethernet interface (closes #33)
The CPU is allowed to access normal memory writes out-of-order. Here
the write to the OWN flag in the DMA descriptor (normal memory) was
placed after the DMA tail pointer advance (in device memory, so not
reorderable). This meant the ethernet DMA engine stalled as it saw
a descriptor it did not own, and only restarted and sent the packet
when the next packet was released.

This fix will work as long as the CPU data cache is disabled. If we
want to enable the cache, the simplest method would be to mark SRAM3
as uncacheable via the MPU.
2019-11-16 03:25:42 +00:00
d7f46c1f12 factor CPU and board-specific initialisation out of main (NFC) 2019-11-13 22:13:04 +00:00
David Nadlinger
2297286360 Fix TCP command interface rx buffer wrapping
Previously, if a message spanned the end of the
receive ring buffer, the last byte in the buffer
would be missing from the to-be-decoded message,
leading to a parse error or panic.

With this commit, >3M commands were exchanged
over one socket without further issues.
2019-11-13 01:50:18 +00:00
bors[bot]
39cb1afcfd
Merge #48
48: remove unused code, deny warnings r=jordens a=jordens

bors r+

Co-authored-by: Robert Jördens <rj@quartiq.de>
2019-11-11 11:20:53 +00:00
0b4f7c9201 remove unused code, deny warnings 2019-11-11 12:04:50 +01:00
65cf0c1594 rcc: pac 0.9 renames 2019-11-11 11:46:07 +01:00
17012621dd use stable rust (1.38.0) 2019-10-22 13:43:49 +00:00
80052f089b fix Unix permissions 2019-09-13 13:52:24 +08:00
1f1e588744 fix system time counter
The CYCCNT module used to calculate the system
time counts every processor clock cycle =
400 MHz.
2019-09-12 00:35:00 +01:00
bors[bot]
7f295285da
Merge #28 #30
28: Read MAC address from EEPROM r=jordens a=cjbe

Try and read the unique MAC address from EEPROM.
If the EEPROM can not be read (e.g. on the unpatched hardware version 1.0 where the EEPROM is unpowered) a hardcoded default of 10:E2:D5:00:03:00 is used.

The MAC address found / used is logged. At the moment the only way of accessing this log is via semihosting.

Closes #23 

30: build(deps): bump serde from 1.0.99 to 1.0.100 r=jordens a=dependabot-preview[bot]

Bumps [serde](https://github.com/serde-rs/serde) from 1.0.99 to 1.0.100.
<details>
<summary>Release notes</summary>

*Sourced from [serde's releases](https://github.com/serde-rs/serde/releases).*

> ## v1.0.100
> - Provide `serde::ser::StdError` and `serde:🇩🇪:StdError` which are either a re-export of `std::error::Error` (if Serde's "std" feature is enabled) or a new identical trait (otherwise).
> 
>     ```rust
>     #[cfg(feature = "std")]
>     pub use std::error::Error as StdError;
> 
>     #[cfg(not(feature = "std"))]
>     pub trait StdError: Debug + Display {
>         fn source(&self) -> Option<&(StdError + 'static)> { None }
>     }
>     ```
> 
>     Serde's error traits `serde::ser::Error` and `serde:🇩🇪:Error` require `std::error::Error` as a supertrait, but only when Serde is built with "std" enabled. Data formats that don't care about no\_std support should generally provide their error types with a `std::error::Error` impl directly:
> 
>     ```rust
>     #[derive(Debug)]
>     struct MySerError {...}
> 
>     impl serde::ser::Error for MySerError {...}
> 
>     impl std::fmt::Display for MySerError {...}
> 
>     // We don't support no_std!
>     impl std::error::Error for MySerError {}
>     ```
> 
>     Data formats that *do* support no\_std may either have a "std" feature of their own as has been required in the past:
> 
>     ```toml
>     [features]
>     std = ["serde/std"]
>     ```
> 
>     ```rust
>     #[cfg(feature = "std")]
>     impl std::error::Error for MySerError {}
>     ```
> 
>     ... or else now may provide the std Error impl unconditionally via Serde's re-export:
> 
>     ```rust
>     impl serde::ser::StdError for MySerError {}
>     ```
</details>
<details>
<summary>Commits</summary>

- [`b6a77c4`](b6a77c4413) Release 1.0.100
- [`3343885`](33438850a6) Merge pull request [#1620](https://github-redirect.dependabot.com/serde-rs/serde/issues/1620) from dtolnay/error
- [`c083cfd`](c083cfd65e) Export std error type so downstream doesn't need "std" feature
- [`4cea81f`](4cea81f93f) Merge pull request [#1615](https://github-redirect.dependabot.com/serde-rs/serde/issues/1615) from jamesmunns/patch-1
- [`2d36be7`](2d36be753a) Add Postcard to the list of Serde Data Formats
- [`738d29e`](738d29eaa9) Update serde_derive_internals to syn 1.0
- [`b536fb6`](b536fb67a4) Merge pull request [#1604](https://github-redirect.dependabot.com/serde-rs/serde/issues/1604) from UnHumbleBen/patch-1
- [`b10c23a`](b10c23a950) Fixed a typo
- [`85a5cf7`](85a5cf7cb1) Document serde_derive minimum rustc
- See full diff in [compare view](https://github.com/serde-rs/serde/compare/v1.0.99...v1.0.100)
</details>
<br />

[![Dependabot compatibility score](https://api.dependabot.com/badges/compatibility_score?dependency-name=serde&package-manager=cargo&previous-version=1.0.99&new-version=1.0.100)](https://dependabot.com/compatibility-score.html?dependency-name=serde&package-manager=cargo&previous-version=1.0.99&new-version=1.0.100)

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Co-authored-by: Chris Ballance <chris.ballance@physics.ox.ac.uk>
Co-authored-by: dependabot-preview[bot] <27856297+dependabot-preview[bot]@users.noreply.github.com>
2019-09-11 14:18:18 +00:00
fc93de432d enable cycle counter
c.f. japaric/cortex-m-rtfm#184

Signed-off-by: Robert Jördens <rj@quartiq.de>
2019-09-11 15:35:06 +02:00
30faa5b703 read MAC address from EEPROM 2019-09-08 16:02:09 +01:00
12b06a0fa9 add I2C and 24xx EEPROM driver 2019-09-05 12:45:57 +01:00
ba5634fb31 smoltcp: bump 2019-08-27 13:19:03 +00:00
1405e62682 rtfm: 0.5 beta 2019-08-27 13:19:03 +00:00
61250a3e90 cargo: bump stm32h7, misc 2019-07-29 08:34:46 +00:00
dd981ed850 panic: abort, not halt 2019-06-10 00:29:20 +02:00
9b6ef68eac fix panic handler 2019-06-07 14:28:22 +00:00
8ee0950005 panic: turn red leds on 2019-06-07 11:26:24 +02:00
5204a3169b gpio: use odr variants 2019-06-04 09:26:28 +00:00
a8e1740759 parametrize poll return 2019-06-03 17:08:21 +00:00
ee15c27dd9 make json poll generic 2019-06-03 15:54:35 +00:00
6c973038b4 rtfm: command port 2019-06-03 15:06:11 +00:00
2b9a02d98e rtfm: status port 2019-05-30 21:52:01 +00:00
b646c44c1c rtfm: move ethernet into idle 2019-05-30 20:57:41 +00:00
6be0ccfc6a rtfm: continue work 2019-05-30 16:18:59 +00:00
7501ea1963 use rtfm [wip] 2019-05-30 16:03:48 +00:00
9dff71a0c4 Merge branch 'master' into new-pac
* master:
  refactor server
  cleanup, robustify
  iir: remove old setting
  frontend: cleanup
  cargo: use published serde-json-core
  cargo: drop lexical
2019-05-28 11:02:26 +00:00
b0921f67eb refactor server 2019-05-28 10:59:26 +00:00
1cff400d00 cleanup, robustify 2019-05-28 10:15:20 +00:00
a15b490b42 iir: remove old setting 2019-05-28 09:49:17 +00:00
d6b37e6c0e Merge branch 'master' into new-pac
* master:
  python configuration tool
  json command interface
  use serde-json-core [wip]
  README: try SVG again
  add Nix build files
  png
  README: diagram and photo
2019-05-27 18:49:51 +00:00
8e4fbaf80e json command interface
close #3
2019-05-27 18:44:52 +00:00
2746c2fe00 use serde-json-core [wip] 2019-05-23 16:57:08 +00:00
ef18eb38ca ethernet peripheral ownership, cs 2019-05-06 18:10:42 +00:00
bdb6955aa1 pac: rcc 2019-05-06 18:10:42 +00:00
f1c43c6492 pac updates (~0.8) 2019-05-06 17:09:49 +00:00
86dbdf98e2 stm32h7 svd and pac changes 2019-05-06 08:48:22 +00:00
23e262304b stm32h7 changes round 1 2019-05-06 08:47:49 +00:00
1494761f35 use atomics 2019-04-30 11:42:05 +00:00
0ebcd685c3 eth: remove counter 2019-04-29 20:00:53 +02:00
cd284d2c07 eth: mtu clarification 2019-04-29 17:55:24 +00:00
9863ba3a33 cleanup 2019-04-29 11:03:39 +00:00
0efd14aec8 ethernet: tweak 2019-04-28 14:06:56 +00:00
0fafd7aa42 eth: sketch
eth: rework

ethernet: wip

eth: simplify

cargo: bump stm32h7

ethmac: rework

ethmac: fixup

cargo: semihosting version bump

ethmac: fixup

eth: tweak

eth: cleanup

eth: tweaks

eth: more debug

eth: tweak

memory: rename for clarity

eth: tweak

eth: pings

eth: cleanup

eth: cleanup, use interrupts, tighten filter
2019-04-27 16:17:28 +00:00
8ff8a4ce31 main: work around spi stall erratum and debug 2019-04-17 14:04:05 +00:00
00a758ed12 iir: more tweaking 2019-04-16 14:55:26 +00:00
94a928200e iir: tweak 2019-04-16 11:27:11 +00:00
fac82b22ff cleanup 2019-04-15 15:14:02 +00:00
39214c8a26 dma: tim->dma->spi adc start 2019-04-15 13:29:46 +00:00
6b8473daad use unwrap() for simplicity 2019-04-12 16:13:18 +00:00
01ddb2bc77 cleanup, edition 2018 2019-04-12 15:44:09 +00:00
5369b928c1 add get_x_offset 2019-03-31 11:33:18 +00:00
293520e26e iir: tweak, add offset 2019-03-29 18:33:32 +00:00
3b895ead4b set afe1 gain 2019-03-29 08:37:40 +00:00
74f10a7ac4 cleanup iir 2019-03-28 15:10:04 +00:00
dc2e0f8b07 dual channel 2019-03-28 12:13:47 +00:00
7f378a3f3d clean dcache 2019-03-28 10:47:15 +00:00
9350f17ca3 calculate pi coefficients 2019-03-28 10:09:50 +00:00
ed663b536e add prelim iir 2019-03-27 21:45:43 +00:00
eff2dc6c4e led off 2019-03-27 18:24:58 +00:00
31264452a6 irq bypass for dma 2019-03-27 18:19:32 +00:00
2eeb00bb58 use tim2,dma1 to trigger cr1 2019-03-27 13:50:25 +00:00
f9e52928fd use irq 2019-03-25 09:08:27 +00:00
aa3feeb14e back to tsize=1 adc 2019-03-20 19:28:23 +00:00
a2265ab2d1 experiment with duplex adc xfers
problematic because:

* in tsize=1 there needs to be a cstart
* in tsize=0 there is no mssi
2019-03-20 19:08:31 +00:00
984cef6a4c readme, license 2019-03-20 18:33:35 +00:00
208980d94d refactor into functions 2019-03-20 18:06:13 +00:00
52a3f8c4b7 rxdr: 16 bit 2019-03-20 13:48:28 +00:00
263784ff13 no midi 2019-03-20 13:31:48 +00:00
d3d2d4e4f8 enable i/o compensation cell 2019-03-20 10:29:13 +00:00
cbd9bcd302 dac: use inifinite xfers 2019-03-20 09:51:06 +00:00
772b1b4101 dac tx: different work around 2019-03-19 22:02:16 +00:00
4ee7ccb762 fix afe gain 2019-03-19 21:52:55 +00:00
bbe79e3484 speed up pclk again 2019-03-19 21:52:48 +00:00
8fbb1c751b work around erratum 2.10.2 2019-03-19 15:39:01 +00:00
4b49f29b17 dac 2019-03-19 15:27:22 +00:00
b9f27791ab adc 2019-03-18 19:10:36 +00:00
a20e0fa3e5 speed up 2019-03-18 16:57:00 +00:00
155aa5c032 start 2019-03-18 12:56:26 +01:00