work around erratum 2.10.2
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parent
4b49f29b17
commit
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10
src/main.rs
10
src/main.rs
@ -141,8 +141,8 @@ fn main() -> ! {
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rcc.cr.modify(|_, w| w.pll2on().set_bit());
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while rcc.cr.read().pll2rdy().bit_is_clear() {}
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// hclk 200 MHz, pclk 100 MHz
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let dapb = 0b100;
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// hclk 200 MHz, pclk 50 MHz
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let dapb = 0b101;
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rcc.d1cfgr.write(|w| unsafe {
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w.d1cpre().bits(0) // sys_ck not divided
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.hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2
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@ -268,7 +268,7 @@ fn main() -> ! {
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let spi1 = dp.SPI1;
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spi1.cfg1.modify(|_, w| unsafe {
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// w.mbr().bits(0) // clk/2
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w.mbr().bits(1) // FIXME
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w.mbr().bits(0) // FIXME
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.dsize().bits(16 - 1)
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.fthvl().bits(1 - 1) // one data
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});
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@ -356,7 +356,7 @@ fn main() -> ! {
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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loop {
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// cortex_m::interrupt::free(|_cs| { });
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// cortex_m::interrupt::free(|_cs| { });
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// spi1.cr1.write(|w| w.cstart().set_bit());
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spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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while spi1.sr.read().eot().bit_is_clear() {}
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@ -368,7 +368,7 @@ fn main() -> ! {
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// while spi2.sr.read().txp().bit_is_clear() {}
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// spi2.txdr.write(|w| unsafe { w.bits(d as u32) });
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unsafe { ptr::write_volatile(&spi2.txdr as *const _ as *mut u16, d) };
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// write(|w| unsafe { w.bits(d as u32) });
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// write(|w| unsafe { w.bits(d as u32) });
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// while spi2.sr.read().txc().bit_is_clear() {}
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// while spi2.sr.read().eot().bit_is_clear() {}
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// spi2.ifcr.write(|w| w.eotc().set_bit());
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