master
Robert Jördens 2019-03-18 12:56:26 +01:00
parent e26b92e15f
commit 155aa5c032
10 changed files with 791 additions and 0 deletions

8
.cargo/config Normal file
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[target.thumbv7em-none-eabihf]
runner = "arm-none-eabi-gdb"
rustflags = [
"-C", "link-arg=-Tlink.x",
]
[build]
target = "thumbv7em-none-eabihf"

20
.gdbinit Normal file
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target remote :3333
set print asm-demangle on
monitor arm semihosting enable
# if using ITM with itmdump
# monitor tpiu config internal itm.fifo uart off 168000000
# or uart
# monitor tpiu config external uart off 168000000 2000000
# monitor itm port 0 on
load
# tbreak cortex_m_rt::reset_handler
monitor reset halt
# cycle counter delta tool, place two bkpts around the section
define qq
print *0xe0001004-$t0
set var $t0=*0xe0001004
continue
end
set var $t0=0xe0001004
continue

2
.gitignore vendored Normal file
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/target
.gdb_history

480
Cargo.lock generated Normal file
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46
Cargo.toml Normal file
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[package]
name = "stabilizer"
version = "0.1.0"
authors = ["Robert Jördens <rj@quartiq.de>"]
categories = ["embedded", "no-std"]
license = "Apache-2.0"
keywords = ["ethernet", "eth", "stm32", "adc", "dac", "tcp"]
repository = "https://github.com/quartiq/stabilizer"
#documentation = "https://docs.rs/stabilizer/"
edition = "2018"
[badges]
travis-ci = { repository = "jordens/stabilizer", branch = "master" }
maintenance = { status = "experimental" }
[package.metadata.docs.rs]
features = []
default-target = "thumbv7em-none-eabihf"
[dependencies]
cortex-m = { version = "0.5" }
cortex-m-rt = { version = "0.6", features = ["device"] }
cortex-m-log = { version = "0.4", features = ["log-integration"] }
stm32h7 = { version = "0.6", features = ["stm32h7x3", "rt"] }
embedded-hal = "0.2"
log = "0.4"
panic-abort = "0.3"
panic-semihosting = { version = "0.5", optional = true }
smoltcp = { version = "0.5.0", default-features = false, features = ["proto-ipv4", "socket-tcp", "log"] }
[features]
semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
[build-dependencies]
built = "0.3"
[profile.dev]
codegen-units = 1
incremental = false
[profile.release]
debug = true
lto = true
codegen-units = 1
incremental = false
opt-level = "s"

19
build.rs Normal file
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extern crate built;
use std::env;
use std::fs::File;
use std::io::Write;
use std::path::PathBuf;
fn main() {
// Gather build information
built::write_built_file().expect("Failed to acquire build-time information");
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
File::create(out.join("memory.x"))
.unwrap()
.write_all(include_bytes!("memory.x"))
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
}

5
memory.x Normal file
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MEMORY
{
FLASH : ORIGIN = 0x08000000, LENGTH = 512K
RAM : ORIGIN = 0x20000000, LENGTH = 112K /* of 112K + 16K */
}

89
src/main.rs Normal file
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#![no_std]
#![no_main]
#![feature(asm)]
// Enable returning `!`
#![feature(never_type)]
#[allow(unused_extern_crates)]
#[cfg(not(feature = "semihosting"))]
extern crate panic_abort;
#[cfg(feature = "semihosting")]
extern crate panic_semihosting;
extern crate cortex_m;
extern crate cortex_m_rt;
extern crate stm32h7;
#[macro_use]
extern crate log;
use cortex_m_rt::{entry, exception};
// use core::fmt::Write;
use stm32h7::{stm32h7x3 as stm32};
#[cfg(not(feature = "semihosting"))]
fn init_log() {}
#[cfg(feature = "semihosting")]
fn init_log() {
use log::LevelFilter;
use cortex_m_log::log::{Logger, init};
use cortex_m_log::printer::semihosting::{InterruptOk, hio::HStdout};
static mut LOGGER: Option<Logger<InterruptOk<HStdout>>> = None;
let logger = Logger {
inner: InterruptOk::<_>::stdout().expect("semihosting stdout"),
level: LevelFilter::Info,
};
let logger = unsafe {
LOGGER.get_or_insert(logger)
};
init(logger).expect("set logger");
}
// Pull in build information (from `built` crate)
mod build_info {
#![allow(dead_code)]
include!(concat!(env!("OUT_DIR"), "/built.rs"));
}
#[entry]
fn main() -> ! {
init_log();
info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
info!("Built on {}", build_info::BUILT_TIME_UTC);
let mut cp = cortex_m::Peripherals::take().unwrap();
cp.SCB.enable_icache();
cp.SCB.enable_dcache(&mut cp.CPUID);
cp.DWT.enable_cycle_counter();
let mut dp = stm32::Peripherals::take().unwrap();
/*
let clocks = dp.RCC.constrain()
.cfgr
.sysclk(84.mhz())
.hclk(84.mhz())
.pclk1(16.mhz())
.pclk2(32.mhz())
.freeze();
let gpiod = dp.GPIOD.split();
let mut led_fp0 = gpiod.pd5.into_push_pull_output();
*/
cortex_m::interrupt::free(|_cs| {
});
loop {
cortex_m::asm::wfi();
}
}
#[exception]
fn HardFault(ef: &cortex_m_rt::ExceptionFrame) -> ! {
panic!("HardFault at {:#?}", ef);
}
#[exception]
fn DefaultHandler(irqn: i16) {
panic!("Unhandled exception (IRQn = {})", irqn);
}

10
stabilizer.cfg Normal file
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source [find interface/stlink.cfg]
transport select hla_swd
source [find stm32h7x.cfg]
# STM32H7xxxI 2Mo have a dual bank flash.
# Add the second flash bank.
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME
reset_config srst_only

112
stm32h7.cfg Normal file
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# script for stm32h7x family
#
# stm32h7 devices support both JTAG and SWD transports.
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32h7x
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# By default use 64kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x10000
}
#jtag scan chain
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
set _CPUTAPID 0x6ba00477
} {
set _CPUTAPID 0x6ba02477
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
swj_newdap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
# Clock after reset is HSI at 64 MHz, no need of PLL
adapter_khz 1800
adapter_nsrst_delay 100
if {[using_jtag]} {
jtag_ntrst_delay 100
}
# use hardware reset
#
# The STM32H7 does not support connect_assert_srst mode because the AXI is
# unavailable while SRST is asserted, and that is used to access the DBGMCU
# component at 0x5C001000 in the examine-end event handler.
#
# It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
# of the default AP0, and that works with SRST asserted; however, nonzero AP
# usage does not work with HLA, so is not done by default. That change could be
# made in a local configuration file if connect_assert_srst mode is needed for
# a specific application and a non-HLA adapter is in use.
reset_config srst_only srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
# makes the data access cacheable. This allows reading and writing data in the
# CPU cache from the debugger, which is far more useful than going straight to
# RAM when operating on typical variables, and is generally no worse when
# operating on special memory locations.
$_CHIPNAME.dap apcsw 0x08000000 0x08000000
}
$_TARGETNAME configure -event examine-end {
# Enable D3 and D1 DBG clocks
# DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
mmw 0x5C001004 0x00600000 0
# Enable debug during low power modes (uses more power)
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
mmw 0x5C001004 0x00000187 0
# Stop watchdog counters during halt
# DBGMCU_APB3FZ1 |= WWDG1
mmw 0x5C001034 0x00000040 0
# DBGMCU_APB4FZ1 |= WDGLSD1
mmw 0x5C001054 0x00040000 0
}
$_TARGETNAME configure -event trace-config {
# Set TRACECLKEN; TRACE_MODE is set to async; when using sync
# change this value accordingly to configure trace pins
# assignment
mmw 0x5C001004 0x00100000 0
}
$_TARGETNAME configure -event reset-init {
# Clock after reset is HSI at 64 MHz, no need of PLL
adapter_khz 4000
}