dma: tim->dma->spi adc start
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cfb538d596
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45
src/main.rs
45
src/main.rs
@ -446,20 +446,18 @@ fn spi4_setup(spi4: &stm32::SPI4) {
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fn tim2_setup(tim2: &stm32::TIM2) {
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tim2.psc.write(|w| unsafe { w.psc().bits(200 - 1) }); // from 200 MHz
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tim2.arr.write(|w| unsafe { w.bits(2 - 1) }); // µs
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tim2.dier.write(|w| w.ude().set_bit().uie().set_bit()); // FIXME
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tim2.dier.write(|w| w.ude().set_bit());
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tim2.egr.write(|w| w.ug().set_bit());
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tim2.cr1.modify(|_, w|
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w.dir().clear_bit() // up
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.cen().set_bit()); // enable
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}
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fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa: usize) {
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// info!("{:#x} {:#x}", pa, unsafe { *(pa as *const u32) });
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fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usize, pa1: usize) {
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dma1.s0cr.modify(|_, w| w.en().clear_bit());
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while dma1.s0cr.read().en().bit_is_set() {}
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dma1.s0par.write(|w| unsafe { w.pa().bits(pa as u32) });
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dma1.s0par.write(|w| unsafe { w.pa().bits(pa0 as u32) });
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dma1.s0m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) });
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dma1.s0ndtr.write(|w| unsafe { w.ndt().bits(1) });
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dmamux1.dmamux1_c0cr.modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up
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@ -478,6 +476,30 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa: usize
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});
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dma1.s0fcr.modify(|_, w| w.dmdis().clear_bit());
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dma1.s0cr.modify(|_, w| w.en().set_bit());
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dma1.s1cr.modify(|_, w| w.en().clear_bit());
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while dma1.s1cr.read().en().bit_is_set() {}
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dma1.s1par.write(|w| unsafe { w.pa().bits(pa1 as u32) });
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dma1.s1m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) });
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dma1.s1ndtr.write(|w| unsafe { w.ndt().bits(1) });
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dmamux1.dmamux1_c1cr.modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up
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dma1.s1cr.modify(|_, w| unsafe {
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w.pl().bits(0b11) // very high
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.circ().set_bit() // reload ndtr
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.msize().bits(0b10) // 32
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.minc().clear_bit()
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.mburst().bits(0b00)
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.psize().bits(0b10) // 32
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.pinc().clear_bit()
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.pburst().bits(0b00)
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.dbm().clear_bit()
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.dir().bits(0b01) // memory_to_peripheral
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.pfctrl().clear_bit() // dma is FC
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});
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dma1.s1fcr.modify(|_, w| w.dmdis().clear_bit());
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dma1.s1cr.modify(|_, w| w.en().set_bit());
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}
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static SPIP: Mutex<RefCell<Option<(
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@ -544,9 +566,9 @@ fn main() -> ! {
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let dat_addr = unsafe { &DAT as *const _ } as usize;
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cp.SCB.clean_dcache_by_address(dat_addr, 4);
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// TODO: also SPI4/ADC0
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dma1_setup(&dp.DMA1, &dp.DMAMUX1, dat_addr,
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&spi1.cr1 as *const _ as usize);
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&spi1.cr1 as *const _ as usize,
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&spi5.cr1 as *const _ as usize);
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rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit());
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tim2_setup(&dp.TIM2);
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@ -563,7 +585,6 @@ fn main() -> ! {
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cortex_m::interrupt::free(|cs| {
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cp.NVIC.enable(stm32::Interrupt::SPI1);
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cp.NVIC.enable(stm32::Interrupt::TIM2); // FIXME
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SPIP.borrow(cs).replace(Some((spi1, spi2, spi4, spi5)));
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});
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@ -575,14 +596,6 @@ fn main() -> ! {
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}
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}
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#[interrupt]
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fn TIM2() { // FIXME
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let dp = unsafe { Peripherals::steal() };
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dp.TIM2.sr.write(|w| w.uif().clear_bit()); // rc_w0
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dp.SPI1.cr1.write(|w| unsafe { w.bits(0x201) }); // ADC0
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dp.SPI5.cr1.write(|w| unsafe { w.bits(0x201) }); // ADC1
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}
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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static mut IIR_STATE: [IIRState; 2] = [[0.; 5]; 2];
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static mut IIR_CH: [IIR; 2] = [
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