speed up pclk again
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8fbb1c751b
commit
bbe79e3484
@ -30,6 +30,7 @@ smoltcp = { version = "0.5.0", default-features = false, features = ["proto-ipv4
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[features]
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semihosting = ["panic-semihosting", "cortex-m-log/semihosting"]
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bkpt = [ ]
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[build-dependencies]
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built = "0.3"
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50
src/main.rs
50
src/main.rs
@ -141,8 +141,8 @@ fn main() -> ! {
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rcc.cr.modify(|_, w| w.pll2on().set_bit());
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while rcc.cr.read().pll2rdy().bit_is_clear() {}
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// hclk 200 MHz, pclk 50 MHz
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let dapb = 0b101;
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// hclk 200 MHz, pclk 100 MHz
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let dapb = 0b100;
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rcc.d1cfgr.write(|w| unsafe {
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w.d1cpre().bits(0) // sys_ck not divided
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.hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2
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@ -267,8 +267,7 @@ fn main() -> ! {
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let spi1 = dp.SPI1;
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spi1.cfg1.modify(|_, w| unsafe {
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// w.mbr().bits(0) // clk/2
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w.mbr().bits(0) // FIXME
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w.mbr().bits(0) // clk/2
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.dsize().bits(16 - 1)
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.fthvl().bits(1 - 1) // one data
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});
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@ -327,7 +326,7 @@ fn main() -> ! {
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rcc.apb1lrstr.write(|w| w.spi2rst().set_bit());
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rcc.apb1lrstr.write(|w| w.spi2rst().clear_bit());
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rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit());
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spi2.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(0) // clk/2
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.dsize().bits(16 - 1)
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@ -350,34 +349,37 @@ fn main() -> ! {
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.mssi().bits(0) // master SS idle
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});
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spi2.cr2.modify(|_, w| unsafe {
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w.tsize().bits(0)
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w.tsize().bits(0) // infinite
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});
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spi2.cr1.write(|w| w.spe().set_bit());
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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loop {
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// cortex_m::interrupt::free(|_cs| { });
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// spi1.cr1.write(|w| w.cstart().set_bit());
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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// at least one SCK between EOT and CSTART
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spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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while spi1.sr.read().eot().bit_is_clear() {}
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spi1.ifcr.write(|w| w.eotc().set_bit());
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while spi1.sr.read().rxp().bit_is_set() {
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let a = spi1.rxdr.read().rxdr().bits() as i16;
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let d = (a as u16) ^ 0x8000;
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while spi1.sr.read().rxp().bit_is_clear() {}
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let a = spi1.rxdr.read().rxdr().bits() as i16;
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let d = (a as u16) ^ 0x8000;
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// while spi2.sr.read().txp().bit_is_clear() {}
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// spi2.txdr.write(|w| unsafe { w.bits(d as u32) });
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unsafe { ptr::write_volatile(&spi2.txdr as *const _ as *mut u16, d) };
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// write(|w| unsafe { w.bits(d as u32) });
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// while spi2.sr.read().txc().bit_is_clear() {}
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// while spi2.sr.read().eot().bit_is_clear() {}
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// spi2.ifcr.write(|w| w.eotc().set_bit());
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info!("dac adc {:#x} cr1 {:#x} sr {:#x} cfg1 {:#x} cr2 {:#x}",
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a,
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spi2.cr1.read().bits(), spi2.sr.read().bits(),
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spi2.cfg1.read().bits(), spi2.cr2.read().bits(),
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);
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}
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while spi2.sr.read().txp().bit_is_clear() {}
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let txdr = &spi2.txdr as *const _ as *mut u16;
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unsafe { ptr::write_volatile(txdr, d) };
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while spi2.sr.read().txc().bit_is_clear() {}
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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info!("dac adc {:#x} cr1 {:#x} sr {:#x} cfg1 {:#x} cr2 {:#x}",
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a,
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spi2.cr1.read().bits(), spi2.sr.read().bits(),
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spi2.cfg1.read().bits(), spi2.cr2.read().bits(),
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);
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// cortex_m::asm::wfi();
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}
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}
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