dual channel
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7f378a3f3d
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dc2e0f8b07
@ -48,7 +48,7 @@ impl IIR {
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pub fn update(&self, xy: &mut IIRState, x0: f32) -> f32 {
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xy.rotate_right(1);
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xy[0] = x0 - self.x_offset;
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xy[0] = x0 + self.x_offset;
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let y0 = macc(self.y_offset, xy, &self.ba)
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.min(self.scale).max(-self.scale);
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xy[xy.len()/2] = y0;
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165
src/main.rs
165
src/main.rs
@ -197,7 +197,7 @@ fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
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}
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fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
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gpioe: &stm32::GPIOE, gpiog: &stm32::GPIOG) {
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gpioe: &stm32::GPIOE, gpiof: &stm32::GPIOF, gpiog: &stm32::GPIOG) {
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// FP_LED0
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gpiod.otyper.modify(|_, w| w.ot5().push_pull());
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gpiod.moder.modify(|_, w| w.moder5().output());
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@ -232,6 +232,7 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
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.odr3().clear_bit()
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);
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// ADC0
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// SCK: PG11
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gpiog.moder.modify(|_, w| w.moder11().alternate());
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gpiog.otyper.modify(|_, w| w.ot11().push_pull());
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@ -247,6 +248,7 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
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gpiog.ospeedr.modify(|_, w| w.ospeedr10().very_high_speed());
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gpiog.afrh.modify(|_, w| w.afr10().af5());
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// DAC0
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// SCK: PB10
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gpiob.moder.modify(|_, w| w.moder10().alternate());
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gpiob.otyper.modify(|_, w| w.ot10().push_pull());
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@ -268,12 +270,53 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
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gpioe.moder.modify(|_, w| w.moder11().output());
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gpioe.otyper.modify(|_, w| w.ot11().push_pull());
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gpioe.odr.modify(|_, w| w.odr11().clear_bit());
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// DAC_CLR: PE12
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gpioe.moder.modify(|_, w| w.moder12().output());
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gpioe.otyper.modify(|_, w| w.ot12().push_pull());
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gpioe.odr.modify(|_, w| w.odr12().set_bit());
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// ADC1
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// SCK: PF6
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gpiof.moder.modify(|_, w| w.moder7().alternate());
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gpiof.otyper.modify(|_, w| w.ot7().push_pull());
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gpiof.ospeedr.modify(|_, w| w.ospeedr7().very_high_speed());
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gpiof.afrl.modify(|_, w| w.afr7().af5());
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// MOSI: PF9
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// MISO: PF7
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gpiof.moder.modify(|_, w| w.moder8().alternate());
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gpiof.afrh.modify(|_, w| w.afr8().af5());
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// NSS: PF8
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gpiof.moder.modify(|_, w| w.moder6().alternate());
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gpiof.otyper.modify(|_, w| w.ot6().push_pull());
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gpiof.ospeedr.modify(|_, w| w.ospeedr6().very_high_speed());
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gpiof.afrl.modify(|_, w| w.afr6().af5());
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// DAC1
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// SCK: PE2
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gpioe.moder.modify(|_, w| w.moder2().alternate());
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gpioe.otyper.modify(|_, w| w.ot2().push_pull());
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gpioe.ospeedr.modify(|_, w| w.ospeedr2().very_high_speed());
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gpioe.afrl.modify(|_, w| w.afr2().af5());
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// MOSI: PE6
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gpioe.moder.modify(|_, w| w.moder6().alternate());
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gpioe.otyper.modify(|_, w| w.ot6().push_pull());
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gpioe.ospeedr.modify(|_, w| w.ospeedr6().very_high_speed());
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gpioe.afrl.modify(|_, w| w.afr6().af5());
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// MISO: PE5
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// NSS: PE4
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gpioe.moder.modify(|_, w| w.moder4().alternate());
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gpioe.otyper.modify(|_, w| w.ot4().push_pull());
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gpioe.ospeedr.modify(|_, w| w.ospeedr4().very_high_speed());
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gpioe.afrl.modify(|_, w| w.afr4().af5());
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// DAC1_LDAC: PE15
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gpioe.moder.modify(|_, w| w.moder15().output());
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gpioe.otyper.modify(|_, w| w.ot15().push_pull());
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gpioe.odr.modify(|_, w| w.odr15().clear_bit());
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}
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// ADC0
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fn spi1_setup(spi1: &stm32::SPI1) {
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spi1.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(1) // clk/4
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@ -302,6 +345,36 @@ fn spi1_setup(spi1: &stm32::SPI1) {
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spi1.cr1.write(|w| w.spe().set_bit());
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}
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// ADC1
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fn spi5_setup(spi5: &stm32::SPI5) {
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spi5.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(1) // clk/4
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.dsize().bits(16 - 1)
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.fthvl().bits(1 - 1) // one data
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});
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spi5.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().set_bit()
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.cpha().set_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b10) // simplex receiver
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.ioswp().clear_bit()
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.midi().bits(0) // master inter data idle
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.mssi().bits(6) // master SS idle
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});
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spi5.cr2.modify(|_, w| unsafe {
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w.tsize().bits(1)
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});
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spi5.cr1.write(|w| w.spe().set_bit());
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}
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// DAC0
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fn spi2_setup(spi2: &stm32::SPI2) {
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spi2.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(0) // clk/2
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@ -328,6 +401,37 @@ fn spi2_setup(spi2: &stm32::SPI2) {
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w.tsize().bits(0)
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});
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spi2.cr1.write(|w| w.spe().set_bit());
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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}
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// DAC1
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fn spi4_setup(spi4: &stm32::SPI4) {
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spi4.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(0) // clk/2
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.dsize().bits(16 - 1)
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.fthvl().bits(1 - 1) // one data
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});
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spi4.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().clear_bit()
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.cpha().clear_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b01) // simplex transmitter
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.ioswp().clear_bit()
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.midi().bits(0) // master inter data idle
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.mssi().bits(0) // master SS idle
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});
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spi4.cr2.modify(|_, w| unsafe {
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w.tsize().bits(0)
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});
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spi4.cr1.write(|w| w.spe().set_bit());
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spi4.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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}
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fn tim2_setup(tim2: &stm32::TIM2) {
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@ -367,9 +471,8 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa: usize
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dma1.s0cr.modify(|_, w| w.en().set_bit());
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}
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static SPI1P: Mutex<RefCell<Option<stm32::SPI1>>> =
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Mutex::new(RefCell::new(None));
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static SPI2P: Mutex<RefCell<Option<stm32::SPI2>>> =
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static SPIP: Mutex<RefCell<Option<(
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stm32::SPI1, stm32::SPI2, stm32::SPI4, stm32::SPI5)>>> =
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Mutex::new(RefCell::new(None));
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#[link_section = ".sram1"]
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@ -402,19 +505,28 @@ fn main() -> ! {
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.gpioben().set_bit()
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.gpioden().set_bit()
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.gpioeen().set_bit()
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.gpiofen().set_bit()
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.gpiogen().set_bit()
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);
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gpio_setup(&dp.GPIOA, &dp.GPIOB, &dp.GPIOD, &dp.GPIOE, &dp.GPIOG);
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gpio_setup(&dp.GPIOA, &dp.GPIOB, &dp.GPIOD, &dp.GPIOE, &dp.GPIOF, &dp.GPIOG);
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rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit());
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let spi2 = dp.SPI2;
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spi2_setup(&spi2);
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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rcc.apb2enr.modify(|_, w| w.spi4en().set_bit());
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let spi4 = dp.SPI4;
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spi4_setup(&spi4);
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rcc.apb2enr.modify(|_, w| w.spi1en().set_bit());
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let spi1 = dp.SPI1;
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spi1_setup(&spi1);
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spi1.ier.write(|w| w.rxpie().set_bit());
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spi1.ier.write(|w| w.eotie().set_bit());
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rcc.apb2enr.modify(|_, w| w.spi5en().set_bit());
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let spi5 = dp.SPI5;
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spi5_setup(&spi5);
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// spi5.ier.write(|w| w.eotie().set_bit());
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rcc.ahb2enr.modify(|_, w| w.sram1en().set_bit());
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rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit());
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@ -423,25 +535,27 @@ fn main() -> ! {
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let dat_addr = unsafe { &DAT as *const _ } as usize;
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cp.SCB.clean_dcache_by_address(dat_addr, 4);
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// TODO: also SPI4/ADC0
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dma1_setup(&dp.DMA1, &dp.DMAMUX1, dat_addr,
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&spi1.cr1 as *const _ as usize);
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rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit());
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tim2_setup(&dp.TIM2);
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unsafe { IIR_CH[0].pi(-0.01, 10.*2e-6/2., 0.).expect("bad coefficients"); }
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unsafe { IIR_CH[0].pi(-0.1, 10.*2e-6/2., 0.).expect("bad coefficients"); }
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unsafe { IIR_CH[1].pi(0.1, 10.*2e-6/2., 0.).expect("bad coefficients"); }
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cortex_m::interrupt::free(|cs| {
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cp.NVIC.enable(stm32::Interrupt::SPI1);
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cp.NVIC.enable(stm32::Interrupt::TIM2); // FIXME
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SPI1P.borrow(cs).replace(Some(spi1));
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SPI2P.borrow(cs).replace(Some(spi2));
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SPIP.borrow(cs).replace(Some((spi1, spi2, spi4, spi5)));
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});
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loop {
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for _ in 0..1000000 { cortex_m::asm::wfi(); }
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let (x0, y0) = unsafe { (IIR_STATE[0][0], IIR_STATE[0][2]) };
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info!("x0={} y0={}", x0, y0);
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let (x0, y0, x1, y1) = unsafe {
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(IIR_STATE[0][0], IIR_STATE[0][2], IIR_STATE[1][0], IIR_STATE[1][2]) };
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info!("x0={} y0={} x1={} y1={}", x0, y0, x1, y1);
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}
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}
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@ -449,7 +563,8 @@ fn main() -> ! {
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fn TIM2() { // FIXME
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let dp = unsafe { Peripherals::steal() };
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dp.TIM2.sr.write(|w| w.uif().clear_bit()); // rc_w0
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dp.SPI1.cr1.write(|w| unsafe { w.bits(0x201) });
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dp.SPI1.cr1.write(|w| unsafe { w.bits(0x201) }); // ADC0
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dp.SPI5.cr1.write(|w| unsafe { w.bits(0x201) }); // ADC1
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}
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const SCALE: f32 = ((1 << 15) - 1) as f32;
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@ -463,26 +578,38 @@ fn SPI1() {
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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cortex_m::interrupt::free(|cs| {
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let spi1p = SPI1P.borrow(cs).borrow();
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let spi1 = spi1p.as_ref().unwrap();
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let spip = SPIP.borrow(cs).borrow();
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let (spi1, spi2, spi4, spi5) = spip.as_ref().unwrap();
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let sr = spi1.sr.read();
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if sr.eot().bit_is_set() {
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spi1.ifcr.write(|w| w.eotc().set_bit());
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}
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if sr.rxp().bit_is_set() {
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// needs to be a half word read
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let rxdr1 = &spi1.rxdr as *const _ as *const u16;
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let a = unsafe { ptr::read_volatile(rxdr1) };
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let x0 = a as i16 as f32;
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let y0 = unsafe { IIR_CH[0].update(&mut IIR_STATE[0], x0) };
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let d = y0 as i16 as u16 ^ 0x8000;
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let spi2p = SPI2P.borrow(cs).borrow();
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let spi2 = spi2p.as_ref().unwrap();
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// needs to be a half word write
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let txdr2 = &spi2.txdr as *const _ as *mut u16;
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unsafe { ptr::write_volatile(txdr2, d) };
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}
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let sr = spi5.sr.read();
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if sr.eot().bit_is_set() {
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spi5.ifcr.write(|w| w.eotc().set_bit());
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}
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if sr.rxp().bit_is_set() {
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let rxdr1 = &spi5.rxdr as *const _ as *const u16;
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let a = unsafe { ptr::read_volatile(rxdr1) };
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let x0 = a as i16 as f32;
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let y0 = unsafe { IIR_CH[1].update(&mut IIR_STATE[1], x0) };
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let d = y0 as i16 as u16 ^ 0x8000;
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let txdr2 = &spi4.txdr as *const _ as *mut u16;
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unsafe { ptr::write_volatile(txdr2, d) };
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}
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});
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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