refactor into functions
parent
52a3f8c4b7
commit
208980d94d
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@ -43,5 +43,3 @@ incremental = false
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debug = true
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lto = true
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codegen-units = 1
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incremental = false
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opt-level = 2
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221
src/main.rs
221
src/main.rs
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@ -48,13 +48,7 @@ mod build_info {
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include!(concat!(env!("OUT_DIR"), "/built.rs"));
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}
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#[entry]
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fn main() -> ! {
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = stm32::Peripherals::take().unwrap();
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// go to VOS1 voltage scale high perf
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let pwr = dp.PWR;
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fn pwr_setup(pwr: &stm32::PWR) {
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pwr.pwr_cr3.write(|w|
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w.sden().set_bit()
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.ldoen().set_bit()
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@ -63,9 +57,9 @@ fn main() -> ! {
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while pwr.pwr_csr1.read().actvosrdy().bit_is_clear() {}
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pwr.pwr_d3cr.write(|w| unsafe { w.vos().bits(0b11) }); // vos1
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while pwr.pwr_d3cr.read().vosrdy().bit_is_clear() {}
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}
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let rcc = dp.RCC;
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fn rcc_reset(rcc: &stm32::RCC) {
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// Reset all peripherals
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rcc.ahb1rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb1rstr.write(|w| unsafe { w.bits(0)});
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@ -89,7 +83,9 @@ fn main() -> ! {
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rcc.ahb4rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb4rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb4rstr.write(|w| unsafe { w.bits(0)});
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}
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fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
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// Ensure HSI is on and stable
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rcc.cr.modify(|_, w| w.hsion().set_bit());
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while rcc.cr.read().hsirdy().bit_is_clear() {}
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@ -157,7 +153,6 @@ fn main() -> ! {
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w.d3ppre().bits(dapb) // rcc_pclk4 = rcc_hclk3 / 2
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});
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let flash = dp.FLASH;
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// 2 wait states, 0b10 programming delay
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// 185-210 MHz
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flash.acr.write(|w| unsafe {
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@ -166,56 +161,13 @@ fn main() -> ! {
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});
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while flash.acr.read().latency().bits() != 2 {}
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// Set system clock to pll1_p
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p
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while rcc.cfgr.read().sws().bits() != 0b011 {}
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// CSI for I/O compensationc ell
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rcc.cr.modify(|_, w| w.csion().set_bit());
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while rcc.cr.read().csirdy().bit_is_clear() {}
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rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
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let syscfg = dp.SYSCFG;
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// enable I/O compensation cell
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syscfg.cccsr.modify(|_, w|
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w.en().set_bit()
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.cs().clear_bit()
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.hslv().clear_bit()
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);
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while syscfg.cccsr.read().ready().bit_is_clear() {}
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cp.SCB.enable_icache();
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cp.SCB.enable_dcache(&mut cp.CPUID);
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cp.DWT.enable_cycle_counter();
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init_log();
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// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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// info!("Built on {}", build_info::BUILT_TIME_UTC);
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// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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// FP_LED0
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let gpiod = dp.GPIOD;
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rcc.ahb4enr.modify(|_, w| w.gpioden().set_bit());
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gpiod.otyper.modify(|_, w| w.ot5().push_pull());
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gpiod.moder.modify(|_, w| w.moder5().output());
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gpiod.odr.modify(|_, w| w.odr5().set_bit());
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// FP_LED1
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gpiod.otyper.modify(|_, w| w.ot6().push_pull());
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gpiod.moder.modify(|_, w| w.moder6().output());
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gpiod.odr.modify(|_, w| w.odr6().set_bit());
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// LED_FP2
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let gpiog = dp.GPIOG;
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rcc.ahb4enr.modify(|_, w| w.gpiogen().set_bit());
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gpiog.otyper.modify(|_, w| w.ot4().push_pull());
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gpiog.moder.modify(|_, w| w.moder4().output());
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gpiog.odr.modify(|_, w| w.odr4().set_bit());
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// LED_FP3
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gpiod.otyper.modify(|_, w| w.ot12().push_pull());
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gpiod.moder.modify(|_, w| w.moder12().output());
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gpiod.odr.modify(|_, w| w.odr12().set_bit());
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// Set system clock to pll1_p
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p
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while rcc.cfgr.read().sws().bits() != 0b011 {}
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rcc.d1ccipr.write(|w| unsafe {
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w.ckpersrc().bits(1) // hse_ck
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@ -228,27 +180,39 @@ fn main() -> ! {
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rcc.d3ccipr.modify(|_, w| unsafe {
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w.spi6src().bits(1) // pll2_q
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});
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}
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// Set up peripheral clocks
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rcc.ahb1enr.modify(|_, w|
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w.dma1en().set_bit()
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.dma2en().set_bit()
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);
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rcc.apb1lenr.modify(|_, w|
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w.spi2en().set_bit()
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.spi3en().set_bit()
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);
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rcc.apb2enr.modify(|_, w|
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w.spi1en().set_bit()
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.spi4en().set_bit()
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.spi5en().set_bit()
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);
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rcc.apb4enr.modify(|_, w|
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w.spi6en().set_bit()
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fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
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// enable I/O compensation cell
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syscfg.cccsr.modify(|_, w|
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w.en().set_bit()
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.cs().clear_bit()
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.hslv().clear_bit()
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);
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while syscfg.cccsr.read().ready().bit_is_clear() {}
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}
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let gpioa = dp.GPIOA;
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rcc.ahb4enr.modify(|_, w| w.gpioaen().set_bit());
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fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
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gpioe: &stm32::GPIOE, gpiog: &stm32::GPIOG) {
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// FP_LED0
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gpiod.otyper.modify(|_, w| w.ot5().push_pull());
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gpiod.moder.modify(|_, w| w.moder5().output());
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gpiod.odr.modify(|_, w| w.odr5().set_bit());
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// FP_LED1
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gpiod.otyper.modify(|_, w| w.ot6().push_pull());
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gpiod.moder.modify(|_, w| w.moder6().output());
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gpiod.odr.modify(|_, w| w.odr6().set_bit());
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// LED_FP2
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gpiog.otyper.modify(|_, w| w.ot4().push_pull());
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gpiog.moder.modify(|_, w| w.moder4().output());
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gpiog.odr.modify(|_, w| w.odr4().set_bit());
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// LED_FP3
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gpiod.otyper.modify(|_, w| w.ot12().push_pull());
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gpiod.moder.modify(|_, w| w.moder12().output());
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gpiod.odr.modify(|_, w| w.odr12().set_bit());
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// AFE0_A0,1: PG2,PG3
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gpiog.otyper.modify(|_, w|
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@ -279,7 +243,34 @@ fn main() -> ! {
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gpiog.ospeedr.modify(|_, w| w.ospeedr10().very_high_speed());
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gpiog.afrh.modify(|_, w| w.afr10().af5());
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let spi1 = dp.SPI1;
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// SCK: PB10
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gpiob.moder.modify(|_, w| w.moder10().alternate());
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gpiob.otyper.modify(|_, w| w.ot10().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr10().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr10().af5());
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// MOSI: PB15
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gpiob.moder.modify(|_, w| w.moder15().alternate());
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gpiob.otyper.modify(|_, w| w.ot15().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr15().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr15().af5());
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// MISO: PB14
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// NSS: PB9
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gpiob.moder.modify(|_, w| w.moder9().alternate());
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gpiob.otyper.modify(|_, w| w.ot9().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr9().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr9().af5());
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// DAC0_LDAC: PE11
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gpioe.moder.modify(|_, w| w.moder11().output());
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gpioe.otyper.modify(|_, w| w.ot11().push_pull());
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gpioe.odr.modify(|_, w| w.odr11().clear_bit());
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// DAC_CLR: PE12
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gpioe.moder.modify(|_, w| w.moder12().output());
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gpioe.otyper.modify(|_, w| w.ot12().push_pull());
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gpioe.odr.modify(|_, w| w.odr12().set_bit());
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}
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fn spi1_setup(spi1: &stm32::SPI1) {
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spi1.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(0) // clk/2
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.dsize().bits(16 - 1)
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@ -305,42 +296,9 @@ fn main() -> ! {
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w.tsize().bits(1)
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});
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spi1.cr1.write(|w| w.spe().set_bit());
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}
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let gpiob = dp.GPIOB;
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rcc.ahb4enr.modify(|_, w| w.gpioben().set_bit());
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// SCK: PB10
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gpiob.moder.modify(|_, w| w.moder10().alternate());
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gpiob.otyper.modify(|_, w| w.ot10().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr10().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr10().af5());
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// MOSI: PB15
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gpiob.moder.modify(|_, w| w.moder15().alternate());
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gpiob.otyper.modify(|_, w| w.ot15().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr15().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr15().af5());
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// MISO: PB14
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// NSS: PB9
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gpiob.moder.modify(|_, w| w.moder9().alternate());
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gpiob.otyper.modify(|_, w| w.ot9().push_pull());
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gpiob.ospeedr.modify(|_, w| w.ospeedr9().very_high_speed());
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gpiob.afrh.modify(|_, w| w.afr9().af5());
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let gpioe = dp.GPIOE;
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rcc.ahb4enr.modify(|_, w| w.gpioeen().set_bit());
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// DAC0_LDAC: PE11
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gpioe.moder.modify(|_, w| w.moder11().output());
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gpioe.otyper.modify(|_, w| w.ot11().push_pull());
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gpioe.odr.modify(|_, w| w.odr11().clear_bit());
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// DAC_CLR: PE12
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gpioe.moder.modify(|_, w| w.moder12().output());
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gpioe.otyper.modify(|_, w| w.ot12().push_pull());
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gpioe.odr.modify(|_, w| w.odr12().set_bit());
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let spi2 = dp.SPI2;
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rcc.apb1lrstr.write(|w| w.spi2rst().set_bit());
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rcc.apb1lrstr.write(|w| w.spi2rst().clear_bit());
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rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit());
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fn spi2_setup(spi2: &stm32::SPI2) {
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spi2.cfg1.modify(|_, w| unsafe {
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w.mbr().bits(0) // clk/2
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.dsize().bits(16 - 1)
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@ -366,6 +324,49 @@ fn main() -> ! {
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w.tsize().bits(0)
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});
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spi2.cr1.write(|w| w.spe().set_bit());
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}
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#[entry]
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fn main() -> ! {
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = stm32::Peripherals::take().unwrap();
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let rcc = dp.RCC;
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rcc_reset(&rcc);
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init_log();
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// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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// info!("Built on {}", build_info::BUILT_TIME_UTC);
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// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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// go to VOS1 voltage scale high perf
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pwr_setup(&dp.PWR);
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rcc_pll_setup(&rcc, &dp.FLASH);
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rcc.apb4enr.modify(|_, w| w.syscfgen().set_bit());
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io_compensation_setup(&dp.SYSCFG);
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cp.SCB.enable_icache();
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cp.SCB.enable_dcache(&mut cp.CPUID);
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cp.DWT.enable_cycle_counter();
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rcc.ahb4enr.modify(|_, w|
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w.gpioaen().set_bit()
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.gpioben().set_bit()
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.gpioden().set_bit()
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.gpioeen().set_bit()
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.gpiogen().set_bit()
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);
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gpio_setup(&dp.GPIOA, &dp.GPIOB, &dp.GPIOD, &dp.GPIOE, &dp.GPIOG);
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rcc.ahb1enr.modify(|_, w| w.dma1en().set_bit());
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rcc.apb1lenr.modify(|_, w| w.spi2en().set_bit());
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rcc.apb2enr.modify(|_, w| w.spi1en().set_bit());
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let spi1 = dp.SPI1;
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spi1_setup(&spi1);
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let spi2 = dp.SPI2;
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spi2_setup(&spi2);
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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Reference in New Issue