dac tx: different work around
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parent
4ee7ccb762
commit
772b1b4101
16
src/main.rs
16
src/main.rs
@ -349,11 +349,9 @@ fn main() -> ! {
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.mssi().bits(0) // master SS idle
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});
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spi2.cr2.modify(|_, w| unsafe {
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w.tsize().bits(0) // infinite
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w.tsize().bits(1)
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});
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spi2.cr1.write(|w| w.spe().set_bit());
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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loop {
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#[cfg(feature = "bkpt")]
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@ -363,14 +361,22 @@ fn main() -> ! {
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spi1.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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while spi1.sr.read().eot().bit_is_clear() {}
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spi1.ifcr.write(|w| w.eotc().set_bit());
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while spi1.sr.read().rxp().bit_is_clear() {}
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if spi1.sr.read().rxp().bit_is_clear() {
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continue;
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}
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let a = spi1.rxdr.read().rxdr().bits() as i16;
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let d = (a as u16) ^ 0x8000;
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while spi2.sr.read().txp().bit_is_clear() {}
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if spi2.sr.read().txp().bit_is_clear() {
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continue;
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}
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let txdr = &spi2.txdr as *const _ as *mut u16;
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unsafe { ptr::write_volatile(txdr, d) };
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// at least one SCK between EOT and CSTART
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spi2.cr1.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 9)) });
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while spi2.sr.read().txc().bit_is_clear() {}
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while spi2.sr.read().eot().bit_is_clear() {}
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spi1.ifcr.write(|w| w.eotc().set_bit());
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#[cfg(feature = "bkpt")]
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cortex_m::asm::bkpt();
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