pac: rcc
parent
f1c43c6492
commit
bdb6955aa1
111
src/main.rs
111
src/main.rs
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@ -92,47 +92,43 @@ fn rcc_reset(rcc: &stm32::RCC) {
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}
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fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
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// Ensure HSI is on and stable
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rcc.cr.modify(|_, w| w.hsion().set_bit());
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while rcc.cr.read().hsirdy().bit_is_clear() {}
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// Set system clock to HSI
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0) }); // hsi
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while rcc.cfgr.read().sws().bits() != 0 {}
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// Clear registers to reset value
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rcc.cr.write(|w| w.hsion().set_bit());
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// Switch to HSI to mess with HSE
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rcc.cr.modify(|_, w| w.hsion().on());
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while rcc.cr.read().hsirdy().is_not_ready() {}
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rcc.cfgr.modify(|_, w| w.sw().hsi());
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while !rcc.cfgr.read().sws().is_hsi() {}
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rcc.cr.write(|w| w.hsion().on());
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rcc.cfgr.reset();
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// Ensure HSE is on and stable
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rcc.cr.modify(|_, w|
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w.hseon().set_bit()
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.hsebyp().clear_bit());
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while rcc.cr.read().hserdy().bit_is_clear() {}
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w.hseon().on()
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.hsebyp().not_bypassed());
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while !rcc.cr.read().hserdy().is_ready() {}
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rcc.pllckselr.modify(|_, w| unsafe {
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w.pllsrc().bits(0b10) // hse
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rcc.pllckselr.modify(|_, w|
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w.pllsrc().hse()
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.divm1().bits(1) // ref prescaler
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.divm2().bits(1) // ref prescaler
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});
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);
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// Configure PLL1: 8MHz /1 *100 /2 = 400 MHz
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rcc.pllcfgr.modify(|_, w| unsafe {
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w.pll1vcosel().clear_bit() // 192-836 MHz VCO
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.pll1rge().bits(0b11) // 8-16 MHz PFD
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.pll1fracen().clear_bit()
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.divp1en().set_bit()
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.pll2vcosel().set_bit() // 150-420 MHz VCO
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.pll2rge().bits(0b11) // 8-16 MHz PFD
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.pll2fracen().clear_bit()
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.divp2en().set_bit()
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.divq2en().set_bit()
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});
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rcc.pllcfgr.modify(|_, w|
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w.pll1vcosel().wide_vco() // 192-836 MHz VCO
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.pll1rge().range8() // 8-16 MHz PFD
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.pll1fracen().reset()
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.divp1en().enabled()
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.pll2vcosel().medium_vco() // 150-420 MHz VCO
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.pll2rge().range8() // 8-16 MHz PFD
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.pll2fracen().reset()
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.divp2en().enabled()
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.divq2en().enabled()
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);
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rcc.pll1divr.write(|w| unsafe {
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w.divn1().bits(100 - 1) // feebdack divider
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.divp1().bits(2 - 1) // p output divider
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.divp1().div2() // p output divider
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});
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rcc.cr.modify(|_, w| w.pll1on().set_bit());
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while rcc.cr.read().pll1rdy().bit_is_clear() {}
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rcc.cr.modify(|_, w| w.pll1on().on());
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while !rcc.cr.read().pll1rdy().is_ready() {}
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// Configure PLL2: 8MHz /1 *25 / 2 = 100 MHz
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rcc.pll2divr.write(|w| unsafe {
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@ -140,24 +136,22 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
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.divp1().bits(2 - 1) // p output divider
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.divq1().bits(2 - 1) // q output divider
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});
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rcc.cr.modify(|_, w| w.pll2on().set_bit());
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while rcc.cr.read().pll2rdy().bit_is_clear() {}
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rcc.cr.modify(|_, w| w.pll2on().on());
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while !rcc.cr.read().pll2rdy().is_ready() {}
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// hclk 200 MHz, pclk 100 MHz
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let dapb = 0b100;
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rcc.d1cfgr.write(|w| unsafe {
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w.d1cpre().bits(0) // sys_ck not divided
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.hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2
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.d1ppre().bits(dapb) // rcc_pclk3 = rcc_hclk3 / 2
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});
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rcc.d2cfgr.write(|w| unsafe {
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w.d2ppre1().bits(dapb) // rcc_pclk1 = rcc_hclk3 / 2
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.d2ppre2().bits(dapb) // rcc_pclk2 = rcc_hclk3 / 2
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});
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rcc.d3cfgr.write(|w| unsafe {
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w.d3ppre().bits(dapb) // rcc_pclk4 = rcc_hclk3 / 2
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});
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rcc.d1cfgr.write(|w|
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w.d1cpre().div1() // sys_ck not divided
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.hpre().div2() // rcc_hclk3 = sys_d1cpre_ck / 2
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.d1ppre().div2() // rcc_pclk3 = rcc_hclk3 / 2
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);
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rcc.d2cfgr.write(|w|
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w.d2ppre1().div2() // rcc_pclk1 = rcc_hclk3 / 2
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.d2ppre2().div2() // rcc_pclk2 = rcc_hclk3 / 2
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);
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rcc.d3cfgr.write(|w|
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w.d3ppre().div2() // rcc_pclk4 = rcc_hclk3 / 2
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);
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// 2 wait states, 0b10 programming delay
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// 185-210 MHz
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@ -168,24 +162,19 @@ fn rcc_pll_setup(rcc: &stm32::RCC, flash: &stm32::FLASH) {
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while flash.acr.read().latency().bits() != 2 {}
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// CSI for I/O compensationc ell
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rcc.cr.modify(|_, w| w.csion().set_bit());
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while rcc.cr.read().csirdy().bit_is_clear() {}
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rcc.cr.modify(|_, w| w.csion().on());
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while !rcc.cr.read().csirdy().is_ready() {}
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// Set system clock to pll1_p
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p
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while rcc.cfgr.read().sws().bits() != 0b011 {}
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rcc.cfgr.modify(|_, w| w.sw().pll1());
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while !rcc.cfgr.read().sws().is_pll1() {}
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rcc.d1ccipr.write(|w| unsafe {
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w.ckpersrc().bits(1) // hse_ck
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});
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rcc.d2ccip1r.modify(|_, w| unsafe {
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w.spi123src().bits(1) // pll2_p
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.spi45src().bits(1) // pll2_q
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});
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rcc.d3ccipr.modify(|_, w| unsafe {
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w.spi6src().bits(1) // pll2_q
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});
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rcc.d1ccipr.write(|w| w.ckpersel().hse());
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rcc.d2ccip1r.modify(|_, w|
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w.spi123sel().pll2_p()
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.spi45sel().pll2_q()
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);
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rcc.d3ccipr.modify(|_, w| w.spi6sel().pll2_q());
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}
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fn io_compensation_setup(syscfg: &stm32::SYSCFG) {
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