pac updates (~0.8)
parent
86dbdf98e2
commit
f1c43c6492
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@ -30,14 +30,17 @@ default-target = "thumbv7em-none-eabihf"
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cortex-m = { version = "0.6", features = ["inline-asm", "const-fn"] }
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cortex-m-rt = { version = "0.6", features = ["device"] }
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cortex-m-log = { version = "0.5", features = ["log-integration"] }
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stm32h7 = { path = "../stm32-rs/stm32h7", features = ["stm32h7x3", "rt"] }
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log = "0.4"
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panic-abort = "0.3"
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panic-semihosting = { version = "0.5.2", optional = true }
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[dependencies.stm32h7]
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path = "../stm32-rs/stm32h7"
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# version = "0.7"
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features = ["stm32h7x3", "rt"]
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[dependencies.smoltcp]
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#git = "https://github.com/m-labs/smoltcp"
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#rev = "cd893e6"
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version = "0.5"
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features = ["proto-ipv4", "socket-tcp"]
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default-features = false
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181
src/main.rs
181
src/main.rs
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@ -333,85 +333,81 @@ fn gpio_setup(gpioa: &stm32::GPIOA, gpiob: &stm32::GPIOB, gpiod: &stm32::GPIOD,
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// ADC0
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fn spi1_setup(spi1: &stm32::SPI1) {
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spi1.cfg1.modify(|_, w| {
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w.mbr().bits(1) // clk/4
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spi1.cfg1.modify(|_, w|
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w.mbr().div4()
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.dsize().bits(16 - 1)
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.fthlv().one_frame()
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});
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spi1.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().set_bit()
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.cpha().set_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b10) // simplex receiver
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.ioswp().clear_bit()
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.midi().bits(0) // master inter data idle
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.mssi().bits(6) // master SS idle
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});
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spi1.cr2.modify(|_, w| {
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w.tsize().bits(1)
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});
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);
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spi1.cfg2.modify(|_, w|
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w.afcntr().controlled()
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.ssom().not_asserted()
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.ssoe().enabled()
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.ssiop().active_low()
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.ssm().disabled()
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.cpol().idle_high()
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.cpha().second_edge()
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.lsbfrst().msbfirst()
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.master().master()
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.sp().motorola()
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.comm().receiver()
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.ioswp().disabled()
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.midi().bits(0)
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.mssi().bits(6)
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);
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spi1.cr2.modify(|_, w| w.tsize().bits(1));
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spi1.cr1.write(|w| w.spe().set_bit());
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}
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// ADC1
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fn spi5_setup(spi5: &stm32::SPI5) {
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spi5.cfg1.modify(|_, w| {
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w.mbr().bits(1) // clk/4
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spi5.cfg1.modify(|_, w|
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w.mbr().div4()
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.dsize().bits(16 - 1)
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.fthlv().one_frame()
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});
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spi5.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().set_bit()
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.cpha().set_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b10) // simplex receiver
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.ioswp().clear_bit()
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.midi().bits(0) // master inter data idle
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.mssi().bits(6) // master SS idle
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});
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spi5.cr2.modify(|_, w| {
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w.tsize().bits(1)
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});
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);
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spi5.cfg2.modify(|_, w|
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w.afcntr().controlled()
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.ssom().not_asserted()
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.ssoe().enabled()
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.ssiop().active_low()
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.ssm().disabled()
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.cpol().idle_high()
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.cpha().second_edge()
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.lsbfrst().msbfirst()
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.master().master()
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.sp().motorola()
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.comm().receiver()
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.ioswp().disabled()
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.midi().bits(0)
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.mssi().bits(6)
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);
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spi5.cr2.modify(|_, w| w.tsize().bits(1));
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spi5.cr1.write(|w| w.spe().set_bit());
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}
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// DAC0
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fn spi2_setup(spi2: &stm32::SPI2) {
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spi2.cfg1.modify(|_, w| {
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w.mbr().bits(0) // clk/2
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spi2.cfg1.modify(|_, w|
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w.mbr().div2()
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.dsize().bits(16 - 1)
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.fthlv().one_frame()
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});
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spi2.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().clear_bit()
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.cpha().clear_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b01) // simplex transmitter
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.ioswp().clear_bit()
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.midi().bits(0) // master inter data idle
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.mssi().bits(0) // master SS idle
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});
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);
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spi2.cfg2.modify(|_, w|
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w.afcntr().controlled()
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.ssom().not_asserted()
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.ssoe().enabled()
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.ssiop().active_low()
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.ssm().disabled()
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.cpol().idle_low()
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.cpha().first_edge()
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.lsbfrst().msbfirst()
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.master().master()
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.sp().motorola()
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.comm().transmitter()
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.ioswp().disabled()
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.midi().bits(0)
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.mssi().bits(0)
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);
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spi2.cr2.modify(|_, w| w.tsize().bits(0));
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spi2.cr1.write(|w| w.spe().enabled());
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spi2.cr1.modify(|_, w| w.cstart().started());
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@ -419,30 +415,28 @@ fn spi2_setup(spi2: &stm32::SPI2) {
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// DAC1
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fn spi4_setup(spi4: &stm32::SPI4) {
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spi4.cfg1.modify(|_, w| {
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w.mbr().bits(0) // clk/2
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spi4.cfg1.modify(|_, w|
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w.mbr().div2()
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.dsize().bits(16 - 1)
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.fthlv().one_frame()
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});
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spi4.cfg2.modify(|_, w| unsafe {
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w.afcntr().set_bit()
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.ssom().set_bit() // ss deassert between frames during midi
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.ssoe().set_bit() // ss output enable
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.ssiop().clear_bit() // ss active low
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.ssm().clear_bit() // PAD counts
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.cpol().clear_bit()
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.cpha().clear_bit()
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.lsbfrst().clear_bit()
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.master().set_bit()
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.sp().bits(0) // motorola
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.comm().bits(0b01) // simplex transmitter
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.ioswp().clear_bit()
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.midi().bits(0) // master inter data idle
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.mssi().bits(0) // master SS idle
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});
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spi4.cr2.modify(|_, w| {
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w.tsize().bits(0)
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});
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);
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spi4.cfg2.modify(|_, w|
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w.afcntr().controlled()
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.ssom().not_asserted()
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.ssoe().enabled()
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.ssiop().active_low()
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.ssm().disabled()
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.cpol().idle_low()
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.cpha().first_edge()
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.lsbfrst().msbfirst()
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.master().master()
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.sp().motorola()
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.comm().transmitter()
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.ioswp().disabled()
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.midi().bits(0)
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.mssi().bits(0)
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);
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spi4.cr2.modify(|_, w| w.tsize().bits(0));
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spi4.cr1.write(|w| w.spe().enabled());
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spi4.cr1.modify(|_, w| w.cstart().started());
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}
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@ -461,10 +455,10 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
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dma1.st[0].cr.modify(|_, w| w.en().clear_bit());
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while dma1.st[0].cr.read().en().bit_is_set() {}
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dma1.st[0].par.write(|w| unsafe { w.pa().bits(pa0 as u32) });
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dma1.st[0].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) });
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dma1.st[0].par.write(|w| unsafe { w.bits(pa0 as u32) });
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dma1.st[0].m0ar.write(|w| unsafe { w.bits(ma as u32) });
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dma1.st[0].ndtr.write(|w| unsafe { w.ndt().bits(1) });
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dmamux1.ccr[0].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up
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dmamux1.ccr[0].modify(|_, w| w.dmareq_id().tim2_up());
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dma1.st[0].cr.modify(|_, w| unsafe {
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w.pl().bits(0b01) // medium
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.circ().set_bit() // reload ndtr
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@ -484,10 +478,10 @@ fn dma1_setup(dma1: &stm32::DMA1, dmamux1: &stm32::DMAMUX1, ma: usize, pa0: usiz
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dma1.st[1].cr.modify(|_, w| w.en().clear_bit());
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while dma1.st[1].cr.read().en().bit_is_set() {}
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dma1.st[1].par.write(|w| unsafe { w.pa().bits(pa1 as u32) });
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dma1.st[1].m0ar.write(|w| unsafe { w.m0a().bits(ma as u32) });
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dma1.st[1].par.write(|w| unsafe { w.bits(pa1 as u32) });
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dma1.st[1].m0ar.write(|w| unsafe { w.bits(ma as u32) });
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dma1.st[1].ndtr.write(|w| unsafe { w.ndt().bits(1) });
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dmamux1.ccr[1].modify(|_, w| unsafe { w.dmareq_id().bits(22) }); // tim2_up
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dmamux1.ccr[1].modify(|_, w| w.dmareq_id().tim2_up());
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dma1.st[1].cr.modify(|_, w| unsafe {
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w.pl().bits(0b01) // medium
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.circ().set_bit() // reload ndtr
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@ -611,9 +605,8 @@ fn main() -> ! {
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rcc.apb1lenr.modify(|_, w| w.tim2en().set_bit());
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// work around the SPI stall erratum
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//let dbgmcu = dp.DBGMCU;
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//dbgmcu.apb1lfz1.modify(|_, w| w.stop_tim2().set_bit()); // stop tim2 in debug
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unsafe { ptr::write_volatile(0x5c00_103c as *mut usize, 0x0000_0001) };
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let dbgmcu = dp.DBGMCU;
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dbgmcu.apb1lfz1.modify(|_, w| w.tim2().set_bit());
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unsafe {
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let t = 2e-6*2.;
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