speed up
parent
44c36b203d
commit
a20e0fa3e5
2
.gdbinit
2
.gdbinit
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@ -8,7 +8,7 @@ monitor arm semihosting enable
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# monitor itm port 0 on
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load
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# tbreak cortex_m_rt::reset_handler
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monitor reset halt
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# monitor reset halt
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# cycle counter delta tool, place two bkpts around the section
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define qq
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16
memory.x
16
memory.x
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@ -1,11 +1,11 @@
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MEMORY
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{
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ITCM : ORIGIN = 0x00000000, LENGTH = 64K
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RAM : ORIGIN = 0x20000000, LENGTH = 128K
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RAM_D1 : ORIGIN = 0x24000000, LENGTH = 512K
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RAM_D2 : ORIGIN = 0x30000000, LENGTH = 288K
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RAM_D3 : ORIGIN = 0x38000000, LENGTH = 64K
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RAM_B : ORIGIN = 0x38800000, LENGTH = 4K
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FLASH : ORIGIN = 0x08000000, LENGTH = 1024K
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FLASH1 : ORIGIN = 0x08100000, LENGTH = 1024K
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ITCM (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
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RAM_D1 (rwx) : ORIGIN = 0x24000000, LENGTH = 512K
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RAM_D2 (rwx) : ORIGIN = 0x30000000, LENGTH = 288K
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RAM_D3 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K
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RAM_B (rwx) : ORIGIN = 0x38800000, LENGTH = 4K
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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FLASH1 (rx) : ORIGIN = 0x08100000, LENGTH = 1024K
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}
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170
src/main.rs
170
src/main.rs
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@ -49,32 +49,166 @@ mod build_info {
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#[entry]
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fn main() -> ! {
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init_log();
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info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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info!("Built on {}", build_info::BUILT_TIME_UTC);
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let mut cp = cortex_m::Peripherals::take().unwrap();
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let dp = stm32::Peripherals::take().unwrap();
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// go to VOS1 voltage scale high perf
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let pwr = dp.PWR;
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pwr.pwr_cr3.write(|w|
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w.sden().set_bit()
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.ldoen().set_bit()
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.bypass().clear_bit()
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);
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while pwr.pwr_csr1.read().actvosrdy().bit_is_clear() {}
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pwr.pwr_d3cr.write(|w| unsafe { w.vos().bits(0b11) }); // vos1
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while pwr.pwr_d3cr.read().vosrdy().bit_is_clear() {}
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let rcc = dp.RCC;
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// Reset all peripherals
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rcc.ahb1rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb1rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb1lrstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb1lrstr.write(|w| unsafe { w.bits(0)});
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rcc.ahb2rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb2rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb2rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb2rstr.write(|w| unsafe { w.bits(0)});
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/* breaks semihosting
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rcc.ahb3rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb3rstr.write(|w| unsafe { w.bits(0)});
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*/
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rcc.apb3rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb3rstr.write(|w| unsafe { w.bits(0)});
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rcc.ahb4rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.ahb4rstr.write(|w| unsafe { w.bits(0)});
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rcc.apb4rstr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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rcc.apb4rstr.write(|w| unsafe { w.bits(0)});
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// Ensure HSI is on and stable
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rcc.cr.modify(|_, w| w.hsion().set_bit());
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while rcc.cr.read().hsirdy().bit_is_clear() {}
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// Set system clock to HSI
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0) }); // hsi
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while rcc.cfgr.read().sws().bits() != 0 {}
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// Clear registers to reset value
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rcc.cr.write(|w| w.hsion().set_bit());
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rcc.cfgr.reset();
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// Ensure HSE is on and stable
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rcc.cr.modify(|_, w| w.hseon().set_bit());
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while rcc.cr.read().hserdy().bit_is_clear() {}
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rcc.pllckselr.modify(|_, w| unsafe {
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w.pllsrc().bits(0b10) // hse
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.divm1().bits(1) // ref prescaler
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.divm2().bits(4) // ref prescaler
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});
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// Configure PLL1: 8MHz /1 *100 /2 = 400 MHz
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rcc.pllcfgr.modify(|_, w| unsafe {
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w.pll1vcosel().clear_bit() // 192-836 MHz VCO
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.pll1rge().bits(0b11) // 8-16 MHz PFD
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.pll1fracen().clear_bit()
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.divp1en().set_bit()
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.pll2vcosel().set_bit() // 150-420 MHz VCO
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.pll2rge().bits(0b01) // 2-4 MHz PFD
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.pll2fracen().clear_bit()
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.divp2en().set_bit()
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.divq2en().set_bit()
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});
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rcc.pll1divr.write(|w| unsafe {
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w.divn1().bits(100 - 1) // feebdack divider
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.divp1().bits(2 - 1) // p output divider
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});
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rcc.cr.modify(|_, w| w.pll1on().set_bit());
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while rcc.cr.read().pll1rdy().bit_is_clear() {}
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// Configure PLL2: 8MHz /4 * 125 = 250 MHz
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rcc.pll2divr.write(|w| unsafe {
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w.divn1().bits(125 - 1) // feebdack divider
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.divp1().bits(2 - 1) // p output divider
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.divq1().bits(2 - 1) // q output divider
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});
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rcc.cr.modify(|_, w| w.pll2on().set_bit());
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while rcc.cr.read().pll2rdy().bit_is_clear() {}
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// hclk 200 MHz, pclk 100 MHz
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rcc.d1cfgr.write(|w| unsafe {
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w.d1cpre().bits(0) // sys_ck not divided
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.d1ppre().bits(0b100) // rcc_pclk3 = rcc_hclk3 / 2
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.hpre().bits(0b1000) // rcc_hclk3 = sys_d1cpre_ck / 2
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});
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rcc.d2cfgr.write(|w| unsafe {
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w.d2ppre1().bits(0b100) // rcc_pclk1 = rcc_hclk3 / 2
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.d2ppre2().bits(0b100) // rcc_pclk2 = rcc_hclk3 / 2
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});
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rcc.d3cfgr.write(|w| unsafe {
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w.d3ppre().bits(0b100) // rcc_pclk4 = rcc_hclk3 / 2
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});
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let flash = dp.FLASH;
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// 2 wait states, 0b10 programming delay
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// 185-210 MHz
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flash.acr.write(|w| unsafe {
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w.wrhighfreq().bits(2)
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.latency().bits(2)
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});
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while flash.acr.read().latency().bits() != 2 {}
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// Set system clock to HSI
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rcc.cfgr.modify(|_, w| unsafe { w.sw().bits(0b011) }); // pll1p
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while rcc.cfgr.read().sws().bits() != 0b011 {}
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cp.SCB.enable_icache();
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cp.SCB.enable_dcache(&mut cp.CPUID);
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cp.DWT.enable_cycle_counter();
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let mut dp = stm32::Peripherals::take().unwrap();
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/*
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let clocks = dp.RCC.constrain()
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.cfgr
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.sysclk(84.mhz())
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.hclk(84.mhz())
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.pclk1(16.mhz())
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.pclk2(32.mhz())
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.freeze();
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let gpiod = dp.GPIOD.split();
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let mut led_fp0 = gpiod.pd5.into_push_pull_output();
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*/
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init_log();
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// info!("Version {} {}", build_info::PKG_VERSION, build_info::GIT_VERSION.unwrap());
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info!("Built on {}", build_info::BUILT_TIME_UTC);
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// info!("{} {}", build_info::RUSTC_VERSION, build_info::TARGET);
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// FP_LED0
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let gpiod = dp.GPIOD;
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rcc.ahb4enr.modify(|_, w| w.gpioden().set_bit());
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gpiod.otyper.modify(|_, w| w.ot5().push_pull());
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gpiod.moder.modify(|_, w| w.moder5().output());
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gpiod.odr.modify(|_, w| w.odr5().set_bit());
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// FP_LED1
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gpiod.otyper.modify(|_, w| w.ot6().push_pull());
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gpiod.moder.modify(|_, w| w.moder6().output());
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gpiod.odr.modify(|_, w| w.odr6().set_bit());
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// LED_FP0
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let gpiog = dp.GPIOG;
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rcc.ahb4enr.modify(|_, w| w.gpiogen().set_bit());
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gpiog.otyper.modify(|_, w| w.ot4().push_pull());
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gpiog.moder.modify(|_, w| w.moder4().output());
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gpiog.odr.modify(|_, w| w.odr4().set_bit());
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// LED_FP0
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gpiod.otyper.modify(|_, w| w.ot12().push_pull());
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gpiod.moder.modify(|_, w| w.moder12().output());
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gpiod.odr.modify(|_, w| w.odr12().set_bit());
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rcc.d2ccip1r.modify(|_, w| unsafe {
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w.spi123src().bits(1) // pll2_p
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.spi45src().bits(1) // pll2_q
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});
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rcc.d3ccipr.modify(|_, w| unsafe {
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w.spi6src().bits(1) // pll2_q
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});
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cortex_m::interrupt::free(|_cs| {
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});
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loop {
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cortex_m::asm::wfi();
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// cortex_m::asm::wfi();
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}
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}
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