|
|
ee19bc49e7
|
Add bounded fairness constraints for liveness check
|
2020-09-15 17:12:58 +08:00 |
|
|
|
e3b124f4eb
|
Fix minor bug in SRL instruction specification
|
2020-09-15 16:35:05 +08:00 |
|
|
|
c4daa89a88
|
Fix minor bug in JAL instruction specification
|
2020-09-15 16:12:34 +08:00 |
|
|
|
0f4a2a76bd
|
Tweak parameters for Minerva verification tasks
|
2020-09-15 15:44:02 +08:00 |
|
|
|
a9f1431959
|
Record failing instructions in individual instruction checks
|
2020-09-07 15:43:39 +08:00 |
|
|
|
d84852e368
|
Replace unconditional pass and OOM issue with assertion failure
|
2020-09-07 12:32:14 +08:00 |
|
|
|
d25785c4b4
|
Update README.md to reflect support for 64-bit ISAs
|
2020-08-28 12:33:14 +08:00 |
|
|
|
b3acff2bf3
|
Update README.md
|
2020-08-28 12:30:39 +08:00 |
|
|
|
e117fad73d
|
Add RV64M Standard Extension
|
2020-08-28 12:20:56 +08:00 |
|
|
|
9b4644e905
|
Add REMUW instruction
|
2020-08-28 12:04:51 +08:00 |
|
|
|
64964655ff
|
Add REMW instruction
|
2020-08-28 12:01:00 +08:00 |
|
|
|
f1a5da1a34
|
Add DIVUW instruction
|
2020-08-28 11:55:11 +08:00 |
|
|
|
b9f96a8ad0
|
Add DIVW instruction
|
2020-08-28 11:52:09 +08:00 |
|
|
|
1eab79538a
|
Add MULW instruction
|
2020-08-28 11:45:45 +08:00 |
|
|
|
8fa2a33ecf
|
Add RV64M R-Type Instruction
|
2020-08-28 11:37:54 +08:00 |
|
|
|
5d17b917b4
|
Update README.md
|
2020-08-27 16:25:54 +08:00 |
|
|
|
fe5e73b6cb
|
Add RV64I Base ISA
|
2020-08-27 16:21:53 +08:00 |
|
|
|
e7066b8c89
|
Add SRAW instruction
|
2020-08-27 16:04:00 +08:00 |
|
|
|
d188b9cdac
|
Add SRLW instruction
|
2020-08-27 15:56:36 +08:00 |
|
|
|
b60b590fe1
|
Add SLLW instruction
|
2020-08-27 15:54:01 +08:00 |
|
|
|
956be6570d
|
Add SUBW instruction
|
2020-08-27 15:50:30 +08:00 |
|
|
|
2055f5159b
|
Add ADDW instruction
|
2020-08-27 15:48:11 +08:00 |
|
|
|
6e4ecdcee0
|
Add RV64I R-Type Instruction
|
2020-08-27 15:39:09 +08:00 |
|
|
|
cf295596ef
|
Update README.md
|
2020-08-27 13:53:49 +08:00 |
|
|
|
ade3d46b5b
|
Add SRAIW instruction
|
2020-08-27 13:52:20 +08:00 |
|
|
|
94c19ed7f7
|
Add SRLIW instruction
|
2020-08-27 13:42:38 +08:00 |
|
|
|
d837f6f8f6
|
Add SLLIW instruction
|
2020-08-27 13:39:11 +08:00 |
|
|
|
2790cb1f4c
|
Add RV64I I-Type Instruction (Shift Variation)
|
2020-08-27 13:28:29 +08:00 |
|
|
|
a15e57e12e
|
Update README.md
|
2020-08-27 13:12:23 +08:00 |
|
|
|
3a332c5c1d
|
Add ADDIW instruction
|
2020-08-27 13:11:23 +08:00 |
|
|
|
dae95900b6
|
Update README.md
|
2020-08-27 12:54:28 +08:00 |
|
|
|
0954ee7fa9
|
Add SD instruction
|
2020-08-27 12:53:07 +08:00 |
|
|
|
472e0a70f8
|
Update README.md
|
2020-08-27 12:30:57 +08:00 |
|
|
|
94da2671dc
|
Add LD instruction
|
2020-08-27 12:28:19 +08:00 |
|
|
|
bd76a47a52
|
Add LWU instruction
|
2020-08-27 12:25:19 +08:00 |
|
|
|
92e34efe0d
|
Add RV64I I-Type Instruction (Load Variation)
|
2020-08-27 12:20:17 +08:00 |
|
|
|
0af1f20423
|
Add RV64I I-Type Instruction
|
2020-08-27 11:46:04 +08:00 |
|
|
|
fe835e272d
|
Replace RV32I with RV32M for Minerva verification tasks
|
2020-08-27 10:48:35 +08:00 |
|
|
|
1ea25a4886
|
Add RV32M Standard Extension
|
2020-08-27 10:32:49 +08:00 |
|
|
|
3f3ec597a1
|
Update README.md
|
2020-08-26 17:21:27 +08:00 |
|
|
|
46e6ca3f70
|
Add REMU instruction
|
2020-08-26 17:15:27 +08:00 |
|
|
|
fb91df7bb8
|
Add REM instruction
|
2020-08-26 17:11:03 +08:00 |
|
|
|
33ace9147a
|
Add DIVU instruction
|
2020-08-26 17:03:49 +08:00 |
|
|
|
0708f6b962
|
Add DIV instruction
|
2020-08-26 16:58:50 +08:00 |
|
|
|
b74a0cf699
|
Add MULHU instruction
|
2020-08-26 16:43:21 +08:00 |
|
|
|
a58842ea94
|
Add MULHSU instruction
|
2020-08-26 16:39:17 +08:00 |
|
|
|
15580a74c6
|
Add MULH instruction
|
2020-08-26 16:30:54 +08:00 |
|
|
|
585965ee0a
|
Add MUL instruction
|
2020-08-26 15:57:32 +08:00 |
|
|
|
dd17606902
|
Add RV32M R-Type Instruction
|
2020-08-26 15:48:55 +08:00 |
|
|
|
ca9e9c9ca6
|
Add prototype for instruction/data bus implementation
|
2020-08-25 12:41:30 +08:00 |
|
